JP3645152B2 - Video signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing apparatus that performs processing for displaying various video signals having different scanning frequencies or resolutions on a screen of a video display apparatus.
[0002]
[Prior art]
In recent years, a matrix display device centering on a liquid crystal display device has been developed as an image display device replacing a cathode ray tube. The matrix display device is used, for example, for displaying a video signal output from a personal computer. In this case, the level of the video signal output from the personal computer changes with a dot period (pixel period). When such a video signal is displayed on the screen of the matrix display device or when signal processing is performed by writing it in a memory, a sampling clock that matches the dot cycle is required.
[0003]
Since personal computers usually do not have an output terminal for outputting a sampling clock, a video display device extracts a horizontal sync signal from a video signal, and multiplies the extracted horizontal sync signal using a PLL (phase locked loop) circuit or the like. Thus, it is necessary to regenerate the sampling clock.
[0004]
[Problems to be solved by the invention]
When a PLL circuit is used, an output signal whose frequency and phase match the input signal can be obtained. However, the output signal of the PLL circuit is used to generate a timing signal necessary for display control through a subsequent logic processing circuit. Therefore, a phase delay occurs. Since this phase delay depends on the frequency of the input video signal, the amount of phase delay is not uniquely determined in the case of a video display device corresponding to various video signals. This variation in phase delay becomes a problem particularly when a video signal is sampled using a sampling clock.
[0005]
In Japanese Patent Laid-Open No. 9-149291, the sampling clock delay amount is changed, the self-function of the analog-digital converted video signal between the frames is obtained for each delay amount, and the point at which the correlation value decreases is disclosed. A technique is disclosed in which signal change points are set, and an optimal sampling point is set near the center between the signal change points. However, this method requires a dedicated memory to obtain the correlation value. Along with this, peripheral circuits such as a memory control circuit are also required, which increases the cost.
[0006]
Further, only the effective display area of the video signal is displayed on the screen of the matrix display device represented by the liquid crystal display device. Therefore, it is necessary to control the input timing of the video signal so that the effective display area of the video signal is positioned on the screen of the matrix display device.
[0007]
However, the number of dots (number of pixels) in the blanking period outside the effective display area of the video signal output from the personal computer differs for each manufacturer of the personal computer. Therefore, when the input timing of the video signal to the matrix display device is controlled simply in synchronization with the horizontal synchronization signal and the vertical synchronization signal, the display position of the image on the screen of the matrix display device is shifted for each personal computer manufacturer. Therefore, the user needs to adjust the horizontal and vertical image display positions displayed on the screen of the matrix display device when the matrix display device is connected to the personal computer.
[0008]
An object of the present invention is to provide a video signal processing apparatus capable of realizing an optimal image display state for various video signals at low cost and at high speed.
[0009]
[Means for Solving the Problems]
(1) First invention
A video signal processing apparatus according to a first aspect of the present invention is a video signal processing apparatus in which an analog video signal including an effective display area to be displayed on a screen of a video display apparatus is input together with a synchronization signal, and the input synchronization is A sampling clock generating means for generating a sampling clock by dividing the signal; a phase control means for controlling the phase of the sampling clock generated by the sampling clock generating means; and a sampling clock controlled by the phase control means. The signal conversion means for sampling the input analog video signal and converting it to a digital video signal, the storage means for storing the image data, and the signal conversion means obtained during the image display optimization process Digital video signal is written as image data to storage means, and image display operation In addition, a resolution conversion means for obtaining a video signal having a predetermined scanning frequency and a predetermined resolution by writing the digital video signal obtained by the signal conversion means to the storage means as image data and reading the image data stored in the storage means And a signal discriminating means for discriminating a scanning frequency and resolution of an analog video signal inputted based on the inputted synchronizing signal, Correction control means, the correction control means, During image display optimization processing (1) Effective display area of analog video signal is detected based on image data stored in storage means Processing , (2) Based on the discrimination result of the signal discrimination means and the detection result of the effective display area, the division ratio of the sampling clock generation means is determined. Processing for setting division ratio correction data for correction, (3) Phase of sampling clock controlled by phase control means Processing for setting phase correction data for correcting the error, and (4) Correction of writing position of image data to storage means by resolution conversion means Process to set correction data for this in this order Is.
[0010]
In the video signal processing apparatus according to the present invention, the scanning frequency and resolution of the analog video signal are discriminated by the signal discriminating means on the basis of the inputted synchronization signal. A sampling clock is generated by the sampling clock generation means by dividing the input synchronization signal, and the phase of the generated sampling clock is controlled by the phase control means. In response to the sampling clock, the analog video signal is sampled by the signal conversion means and converted into a digital video signal. At the time of image display operation, the digital video signal obtained by the signal conversion means is written as image data by the resolution conversion means to the storage means, and the image data stored in the storage means is read out, and a predetermined scanning frequency and predetermined A video signal with a resolution of 1 is obtained.
[0011]
At the time of image display optimization processing, the digital video signal obtained by the signal conversion means is written into the storage means, and an effective display area of the analog video signal is created based on the image data stored in the storage means by the correction control means. Based on the detection result of the signal discrimination means and the detection result of the effective display area, the frequency division ratio of the sampling clock generation means The division ratio correction data for correcting The phase of the sampling clock controlled by the phase control means Phase correction data is set to correct Writing position of image data to storage means by resolution conversion means Correction data for correcting Is done.
[0012]
As described above, the frequency division ratio of the sampling clock generation means, the phase of the sampling clock, and the writing position of the image data to the storage means are optimized during the image display optimization process. Is effectively displayed on the screen of the video display device. As a result, an optimal image display state can be obtained for various video signals.
[0013]
In this case, since the storage means used for scanning frequency conversion and resolution conversion at the time of image display operation is used for image display optimization processing, dedicated hardware for image display optimization processing is used. There is no need to add. Therefore, the cost can be reduced.
[0014]
Further, based on the image data stored in the storage means, the division ratio of the sampling clock generation means by intra-frame processing, the phase of the sampling clock controlled by the phase control means, and the writing of the image data to the storage means by the resolution conversion means Since the position is corrected, the image display optimization process can be performed at high speed.
[0015]
(2) Second invention
A video signal processing device according to a second invention is the configuration of the video signal processing device according to the first invention. The correction control means is Resolution conversion means Against , During the image display optimization process, The storage area of the storage means Digital video signal obtained by signal conversion means If it is larger than the effective display area of the data, Write the video signal in the effective display area to the storage means together with the video signal outside the effective display area To control Is.
[0016]
In this case, the image data in the effective display area can be stored in the storage unit by writing the digital video signal to the storage unit once during the image display optimization process. Therefore, it is possible to significantly reduce the time for the image display optimization process.
[0017]
(3) Third invention
According to a third aspect of the present invention, there is provided a video signal processing device according to the first aspect of the present invention. The correction control means is Resolution conversion means Against The digital video signal obtained by the signal conversion means during the image display optimization process If the effective display area is larger than the storage area of the storage means, the video signal And writes the compressed video signal of the effective display area to the storage means To control Is.
[0018]
In this case, the compressed video signal of the effective display area is written in the storage means during the image display optimization process. Therefore, even when the effective display area of the digital video signal obtained by the signal conversion means is larger than the storage capacity of the storage means, the image display optimization process can be performed.
[0019]
(4) Fourth invention
According to a fourth aspect of the present invention, there is provided a video signal processing device according to the first aspect of the present invention. The correction control means is Resolution conversion means Against The digital video signal obtained by the signal conversion means during the image display optimization process If the effective display area is larger than the storage area of the storage means, the video signal Of the effective display area is written to the storage means To control Is.
[0020]
In this case, a part of the video signal in the effective display area is written in the storage means, and an image display optimization process is performed using the part of the video signal in the effective display area. Therefore, even when the effective display area of the digital video signal obtained by the signal conversion means is larger than the storage capacity of the storage means, the image display optimization process can be performed.
[0021]
(5) Fifth invention
A video signal processing device according to a fifth invention is the configuration of the video signal processing device according to any one of the first to fourth inventions, and a plurality of input units that receive a plurality of analog video signals and a plurality of synchronization signals. An input detection means for detecting an input unit to which an analog video signal that can be displayed on the screen of the video display device is input based on a synchronization signal input to each input unit; The image processing apparatus further includes selection means for selectively giving the video signal and the synchronization signal input to the input unit detected by the input detection means to the signal conversion means and the signal determination means, respectively, during the optimization process.
[0022]
In this case, a plurality of analog video signals and a plurality of synchronization signals can be input to a plurality of input units. During the image display optimization process, the input unit that receives an analog video signal that can be displayed on the screen of the video display device is detected, and the detected video signal and synchronization signal are automatically input to the detected input unit. To the signal converting means and the signal discriminating means. Therefore, it is possible to realize an optimal image display state with a minimum operation.
[0023]
(6) Sixth invention
According to a sixth aspect of the present invention, there is provided a video signal processor according to any one of the first to fifth aspects of the present invention. The image processing apparatus further includes distortion correction means for correcting the video signal obtained by the resolution conversion means so as to correct image distortion caused by the tilt.
[0024]
In this case, the tilt of the video display device is detected by the tilt detecting unit, and the video signal obtained by the resolution converting unit is corrected so that the distortion of the image due to the detected tilt is corrected. Therefore, even when the video display device is tilted, it is possible to realize an optimal image display state in consideration of the tilt.
[0025]
(7) Seventh invention
According to a seventh aspect of the present invention, there is provided a video signal processing device including: a configuration determining unit configured to determine a format of an input analog video signal in the configuration of the video signal processing device according to any one of the first to sixth aspects; Based on the discrimination result of the discrimination means, it further comprises a form conversion means for converting the analog video signal into a predetermined form or giving it to the signal conversion means without conversion.
[0026]
In this case, it is possible to realize an optimal image display state according to the form of the analog video signal.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a video signal processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.
[0028]
(1) First embodiment
FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to the first embodiment of the present invention.
[0029]
1 includes an A / D converter (analog / digital converter) 1, a resolution conversion circuit 2, a phase control circuit 3, a PLL (phase locked loop) circuit 4, a signal discrimination circuit 5, and an image memory 6. And a microcomputer (hereinafter referred to as a microcomputer) 7.
[0030]
An analog video signal VI input to the video signal input terminal 101 from a predetermined video source such as a personal computer is supplied to the A / D converter 1. In the present embodiment, the video signal VI is an RGB signal. Here, an area to be displayed on the screen of the video signal VI is referred to as an effective display area.
[0031]
The A / D converter 1 samples the video signal VI in response to a sampling clock SCK, which will be described later, converts it into a digital video signal, and gives it to the resolution conversion circuit 2. The resolution conversion circuit 2 writes a digital video signal in the image memory 6 as image data. The resolution conversion circuit 2 reads image data corresponding to an image to be displayed on the screen from the image memory 6 and outputs it from the video signal output terminal 103 as a digital video signal VO. The video signal VO output from the video signal output terminal 103 is given to a video display device such as a matrix display device.
[0032]
A synchronization signal SY input from the video source to the synchronization signal input terminal 102 is supplied to the signal discrimination circuit 5. Here, the synchronization signal SY includes a horizontal synchronization signal and a vertical synchronization signal. The signal discriminating circuit 5 discriminates the scanning frequency and effective resolution of the video source based on the synchronization signal SY and gives the discrimination result to the microcomputer 7. The effective resolution means the resolution of the effective display area VR of the video signal.
[0033]
The microcomputer 7 sets the initial value of the frequency division ratio in the PLL circuit 4 based on the determination result of the signal determination circuit 5, sets the initial value of the phase of the sampling clock in the phase control circuit 3, and sets the initial value in the resolution conversion circuit 2. And set the initial value of vertical image display position. These initial values are values determined to be optimal with respect to the scanning frequency and effective resolution of the video source. As will be described later, these initial values are optimized.
[0034]
The PLL circuit 4 outputs a sampling clock by dividing the synchronization signal output from the signal discrimination circuit 5. The phase control circuit 3 controls the phase of the sampling clock output by the PLL circuit 4 and supplies the controlled sampling clock SCK to the A / D converter 1.
[0035]
The microcomputer 7 executes an image display optimization process from such a state. As an image display optimization process, first, the correction of the division ratio is given to the PLL circuit 4 to optimize the horizontal total sampling number (optimization of the division ratio of the PLL circuit 4). The phase of the sampling clock is optimized by giving correction data of the sampling clock to the phase control circuit 3, and the horizontal and vertical image display positions are optimized by giving correction data of the image display position to the resolution conversion circuit 2. I do.
[0036]
The video signal VO output may be stopped during the execution of the image display optimization process, and the image may not be displayed on the screen of the video display device (image mute). Alternatively, the video signal VO may be output from the resolution conversion circuit 2 during execution of the image display optimization process.
[0037]
In the present embodiment, the PLL circuit 4 corresponds to sampling clock generation means, the phase control circuit 3 corresponds to phase control means, and the A / D converter 1 corresponds to signal conversion means. The image memory 6 corresponds to a storage unit, the resolution conversion circuit 2 corresponds to a resolution conversion unit, and the signal determination circuit 5 corresponds to a signal determination unit. Further, the microcomputer 7 corresponds to correction control means.
[0038]
First, the optimization of the total horizontal sampling number will be described with reference to FIG. FIG. 2 is a waveform diagram of a video signal for explaining optimization of the total horizontal sampling number.
[0039]
Here, the horizontal total sampling number corresponds to the number of dots (number of pixels) of one horizontal line in the effective display area. Each address in the image memory 6 corresponds to one dot (one pixel). The microcomputer 7 detects the horizontal start address A0 and the horizontal end address A1 of the effective display area of the image data stored in the image memory 6.
[0040]
The effective display area of the image data corresponds to the effective display area of the video signal VI. The horizontal start address A0 means the address of the image memory 6 in which image data corresponding to the first pixel of the effective display area is stored in each horizontal line, and the horizontal end address A1 is effective in each horizontal line. It means the address of the image memory 6 in which image data corresponding to the last pixel in the display area is stored.
[0041]
In FIG. 2, the luminance outside the effective display area of the video signal is a, the luminance in consideration of a margin for preventing erroneous discrimination due to noise is b, and the luminance of an arbitrary address detected by the microcomputer 7 is c. . When a + b ≧ c is continuously established, it is determined that it is outside the effective display area. The microcomputer 7 obtains the first address at which a + b <c is established as the horizontal start address A0 in the storage area of the image memory 6 in which image data of a certain horizontal line is stored, and obtains the last address at which a + b <c is established. Obtained as the horizontal end address A1. Then, the difference | A1-A0 | between the horizontal end address A1 and the horizontal start address A0 is calculated.
[0042]
Assuming that the number of horizontal dots in the effective display area of the video source is Hdot, the following formula is established when the total horizontal sampling number matches the number of horizontal dots Hdot in the effective display area of the video source. The microcomputer 7 obtains the number of horizontal dots Hdot in the effective display area of the video source based on the effective resolution given from the signal discrimination circuit 5.
[0043]
| A1-A0 | = Hdot-1 (1)
The frequency division ratio of the PLL circuit 4 is set so that the difference | A1-A0 | between the horizontal end address A1 and the horizontal start address A0 satisfies the above equation (1). In this case, the microcomputer 7 sets the division ratio correction data in the PLL circuit 4 to change the division ratio, fetches the image data from the image memory 6, and the horizontal end address A1 and the horizontal start address A0. The process of calculating the difference | A1-A0 | is repeated until the above expression (1) is satisfied. Thereby, the sampling clock SCK supplied to the A / D converter 1 is optimized.
[0044]
In the present embodiment, first, the image data of all the horizontal lines in the image memory 6 is taken in, one horizontal line whose horizontal start address A0 is located at the left end is detected, and the detected image data of one horizontal line is detected. The above process is repeated.
[0045]
Next, the optimization of the phase of the sampling clock will be described with reference to FIG. 3A and 3B are diagrams for explaining the optimization of the sampling clock phase. FIG. 3A shows a state in which the video signal is sampled at the optimum sampling clock phase, and FIG. A state in which the video signal is sampled by phase is shown.
[0046]
The optimization of the phase of the sampling clock uses the property that the luminance level of the video signal changes with the dot period in images such as characters that are often displayed on the screen of a personal computer.
[0047]
The microcomputer 7 detects a portion where the luminance level changes more than a certain value between adjacent pixels from the range of the effective display area detected when the total horizontal sampling number is optimized in the image memory 6. In FIG. 3, the rising edge of the sampling clock SCK is the sampling point of the video signal VI. Sampling point SP0 and sampling point SP1 correspond to adjacent pixels. Therefore, the absolute value of the difference between the luminance S1 of the video signal at the sampling point SP1 and the luminance S0 of the video signal at the sampling point SP0 corresponds to the luminance difference between adjacent pixels.
[0048]
As shown in FIG. 3A, when the phase of the sampling clock SCK is optimal, the luminance difference | S1-S0 | between adjacent pixels is maximized. As shown in FIG. 3B, when the phase of the sampling clock SCK is not appropriate, the luminance difference | S1-S0 | between adjacent pixels becomes small.
[0049]
The microcomputer 7 sets the phase of the sampling clock SCK output from the phase control circuit 3 so that the luminance difference | S1-S0 | between adjacent pixels is maximized. In this case, the microcomputer 7 sets the correction data of the sampling clock SCK in the phase control circuit 3 to change the phase of the sampling clock SCK, the process of taking image data from the image memory 6, and the luminance between adjacent pixels. The process of calculating the difference | S1-S0 | is repeated until the luminance difference | S1-S0 | between adjacent pixels is maximized. Thereby, the phase of the sampling clock SCK given to the A / D converter 1 is optimized.
[0050]
Note that the characteristic that the luminance difference | S1-S0 | between adjacent pixels is minimized when the phase of the sampling clock SCK is farthest from the optimum value (when the phase of the sampling clock SCK is 180 degrees away from the optimum value) is used. Then, the phase of the sampling clock SCK may be optimized. In this case, the microcomputer 7 obtains the phase of the sampling clock SCK that minimizes the luminance difference | S1-S0 | between adjacent pixels based on the image data captured from the image memory 6, and is shifted by 180 degrees from the obtained phase. Let the phase be the optimum value of the phase of the sampling clock SCK.
[0051]
In the present embodiment, the above processing is repeated for a part of the image data of one horizontal line that is first detected when the total number of horizontal samplings is optimized.
[0052]
Next, optimization of horizontal and vertical image display positions will be described with reference to FIG. FIG. 4 is a diagram for explaining optimization of horizontal and vertical image display positions.
[0053]
FIG. 4 shows the relationship between the storage area MR of the image memory 6 in FIG. 1 and the effective display area VR of the image data written in the image memory 6 by the resolution conversion circuit 2.
[0054]
P0 indicates the position of the first pixel of each frame of the image data written to the image memory 6, and P1 indicates the position of the first pixel of each frame of the image data read from the image memory 6. The horizontal and vertical image display positions on the screen of the video display device are determined by the position of the effective display area VR of the image data written in the storage area MR of the image memory 6.
[0055]
When the horizontal and vertical image display positions are not optimal, as shown in FIG. 4, the position P0 of the first pixel of each frame of image data written to the image memory 6 and each frame of image data read from the image memory 6 Is different from the first pixel position P1. Conversely, when the horizontal and vertical image display positions are optimum, the position P0 of the first pixel of each frame written in the image memory 6 and the position P1 of the first pixel of each frame of image data read from the image memory 6 Match.
[0056]
The microcomputer 7 detects the effective display area VR of the image data based on the image data stored in the image memory 6, and controls the resolution conversion circuit 2 so that P0 = P1. In this case, the microcomputer 7 sets the correction data of the image display position in the resolution conversion circuit 2 to change the writing position of the image data in the storage area MR of the image memory 6 and the process of taking the image data from the image memory 6. The process of detecting the effective display area VR of the image data written in the image memory 6 is repeated until P0 = P1. Thereby, the horizontal and vertical image display positions are optimized.
[0057]
In the present embodiment, it is assumed that the image data is written into the image memory 6 such that the horizontal start position and end position of the effective display area VR of the image data exist in the storage area MR of the image memory 6. . When the horizontal start position or end position of the effective display area VR of the image data deviates from the storage area MR of the image memory 6, the image data is shifted and written to the image memory 6 again.
[0058]
In the present embodiment, the above processing is repeatedly performed on the image data of one horizontal line that is first detected when the total number of horizontal samplings is optimized.
[0059]
With the procedure as described above, it is possible to display an image on the screen of the video display device in an optimal state for various video sources.
[0060]
FIG. 5 is a flowchart showing image display optimization processing by the microcomputer 7 in the video signal processing apparatus of FIG.
[0061]
First, the microcomputer 7 takes in the discrimination result of the signal discrimination circuit 5 (step S1). The microcomputer 7 sets an initial value of the frequency division ratio in the PLL circuit 4, sets an initial value of the phase of the sampling clock in the phase control circuit 3, and sets an initial value of the image display position in the resolution conversion circuit 2. (Step S2).
[0062]
Next, the microcomputer 7 fetches image data from the image memory 6 (step S3), and determines whether or not the total horizontal sampling number is optimal (step S4). If the horizontal total sampling number is not optimal, the division ratio correction data is set in the PLL circuit 4 (step S5), and the process returns to step S3, and the processes of steps S3 to S5 are performed until the horizontal total sampling number is optimal. repeat.
[0063]
When the total horizontal sampling number becomes optimum, image data is taken from the image memory 6 (step S6), and it is determined whether or not the phase of the sampling clock is optimum (step S7). If the phase of the sampling clock is not optimal, the correction data for the phase of the sampling clock is set in the phase control circuit 3 (step S8), the process returns to step S6, and steps S6 to S8 are performed until the phase of the sampling clock is optimal. Repeat the process.
[0064]
When the phase of the sampling clock becomes optimum, image data is taken from the image memory 6 (step S9), and it is determined whether or not the image display position is optimum (step S10). If the image display position is not optimal, the correction data for the image display position is set in the resolution conversion circuit 2 (step S11), the process returns to step S9, and the processing of steps S9 to S11 is performed until the image display position becomes optimal. repeat. When the image display position is optimized, the process is terminated.
[0065]
During the image display operation, the A / D converter 1 samples the analog video signal VI in response to the sampling clock SCK supplied from the phase control circuit 3 and converts it into a digital video signal. give. The resolution conversion circuit 2 writes a digital video signal as image data into the image memory 6 and reads out the image data stored in the image memory from the image memory 6 to thereby have a predetermined scanning frequency and a predetermined effective resolution. VO is output from the video signal output terminal 103.
[0066]
As described above, in the video signal processing apparatus according to the present embodiment, the image memory 6 used for the conversion of the scanning frequency and the conversion of the effective resolution during the image display operation is used for the image display optimization process. Therefore, there is no need to add dedicated hardware for image display optimization processing. Therefore, the cost can be reduced.
[0067]
Further, based on the image data stored in the image memory 6, the frequency division ratio of the PLL circuit 4, the phase of the sampling clock SCK output from the phase control circuit 3 and the resolution conversion circuit 2 to the image memory 6 by intra-frame processing. Since the image data writing position is corrected, image display optimization processing can be performed at high speed.
[0068]
The video signal processing apparatus according to the present embodiment is applied to a matrix display device such as a liquid crystal display device, a PDP (plasma display panel) display device, a DLP (digital light processing; trademark of Texas Instruments Incorporated) system, or the like. The present invention can also be applied to a CRT (cathode ray tube) display that displays an image by digital processing.
[0069]
(2) Second embodiment
Next, a video signal processing apparatus according to the second embodiment of the present invention will be described. The configuration of the video signal processing apparatus according to the present embodiment is the same as that shown in FIG. The operation of the video signal processing apparatus according to the present embodiment is different from the operation of the video signal processing apparatus according to the first embodiment as follows.
[0070]
FIG. 6 is a diagram showing the relationship between the storage area MR of the image memory 6 and the effective display area VR of the image data written in the image memory 6 in the video signal processing apparatus of the second embodiment. In the present embodiment, the storage area MR of the image memory 6 is larger than that of the first embodiment.
[0071]
P4 indicates the position of the first pixel of each frame of the image data written to the image memory 6, and P3 indicates the position of the first pixel of each frame of the image data read from the image memory 6. The horizontal and vertical image display positions are determined by the position of the effective display area VR of the image data written in the storage area MR of the image memory 6.
[0072]
The resolution conversion circuit 2 in FIG. 1 writes the entire image data of the effective display area VR in the storage area MR of the image memory 6 together with the image data outside the effective display area VR. In this case, when a part of the effective display area VR of the image data is not written in the storage area MR of the image memory 6, it is not necessary to shift the image data again and write it into the image memory 6.
[0073]
The microcomputer 7 takes in the image data written in the storage area MR of the image memory 6, and optimizes the total number of horizontal samplings, optimizes the phase of the sampling clock, and optimizes the horizontal and vertical image display positions. The method of optimizing the total number of horizontal samplings, optimizing the phase of the sampling clock, and optimizing the horizontal and vertical image display positions are the same as in the first embodiment.
[0074]
In the present embodiment, the microcomputer 7 can quickly fetch predetermined image data in the effective display area VR from the image memory 6, and the time required for optimizing the image display can be greatly shortened.
[0075]
(3) Third embodiment
Next, a video signal processing apparatus according to the third embodiment of the present invention will be described. The configuration of the video signal processing apparatus according to the present embodiment is the same as that shown in FIG. The operation of the video signal processing apparatus according to the present embodiment is different from the operation of the video signal processing apparatus according to the first embodiment as follows.
[0076]
FIG. 7 shows the storage area MR of the image memory 6 in the video signal processing apparatus of the third embodiment, the effective display area VR0 of the image data given from the A / D converter 1 to the resolution conversion circuit 2, and the resolution conversion circuit 2. It is a figure which shows the relationship of the effective display area VR1 of the compressed image data.
[0077]
As shown in FIG. 7, when the effective display area VR0 of the image data given from the A / D converter 1 to the resolution conversion circuit 2 is larger than the storage area MR of the image memory 6, the effective display area VR0 of the image data. Cannot be written in the storage area MR of the image memory 6. Therefore, the resolution conversion circuit 2 compresses the image data by the resolution conversion function, and writes the effective display area VR1 of the compressed image data in the image memory 6.
[0078]
P6 indicates the position of the first pixel of each frame of the compressed image data written to the image memory 6, and P5 indicates the position of the first pixel of each frame of the image data read from the image memory 6. The horizontal and vertical image display positions are determined by the position of the effective display area VR of the image data written in the storage area MR of the image memory 6.
[0079]
The microcomputer 7 takes in the compressed image data written in the storage area MR of the image memory 6 and optimizes the total horizontal sampling number and the horizontal and vertical image display positions. The method of optimizing the total horizontal sampling number and optimizing the horizontal and vertical image display positions are the same as in the first embodiment.
[0080]
However, if the phase of the sampling clock SCK is optimized based on the compressed image data, sufficient accuracy cannot be obtained. Therefore, the resolution conversion circuit 2 writes the image data supplied from the A / D converter 1 into the image memory 6 without compression when optimizing the phase of the sampling clock SCK.
[0081]
At this time, since the effective display area VR0 of the image data is larger than the storage area MR of the image memory 6, the entire effective display area VR0 of the image data cannot be written to the storage area MR of the image memory 6. However, as described with reference to FIG. 3, the optimization of the phase of the sampling clock SCK does not need to use all of the effective display area VR0 of the image data, and uses a part of the effective display area VR0 of the image data. It can be carried out.
[0082]
As described above, in the video signal processing apparatus according to the present embodiment, even when the effective display area VR0 of the image data is larger than the storage area MR of the image memory 6, it is possible to realize an optimal image display state. Become.
[0083]
(4) Fourth embodiment
Next, a video signal processing apparatus according to the fourth embodiment of the present invention will be described. The configuration of the video signal processing apparatus according to the present embodiment is the same as that shown in FIG. The operation of the video signal processing apparatus according to the present embodiment is different from the operation of the video signal processing apparatus according to the first embodiment as follows.
[0084]
FIG. 8 shows the relationship between the storage area MR of the image memory 6 and the effective display area VR of the image data written in the image memory 6 in the video signal processing apparatus of the fourth embodiment, and (a) shows the validity of the image data. The horizontal and vertical start positions of the display area VR are written in the storage area MR of the image memory 6, and (b) shows the horizontal and vertical end positions of the effective display area VR of the image data stored in the image memory 6. The state written in the area MR is shown.
[0085]
Here, the addresses of the image memory 6 at the horizontal and vertical start positions of the effective display area VR of the image data are Hstart and Vstart, respectively, and the addresses of the image memory 6 at the horizontal and vertical end positions of the effective display area VR of the image data are set. Are Hend and Vend, respectively. Further, the horizontal and vertical displacement amounts of the address of the image memory 6 in which pixel data serving as a reference between the cases of FIG. 8A and FIG. 8B is written are Hoffset and Voffset, respectively. Let Hact and Vact be the number of horizontal dots and the number of vertical lines in the effective display area VR, respectively. In this case, the following expression is established for the effective display area VR of the image data.
[0086]
Hend−Hstart + Hoffset = Hact (2)
Vend−Vstart + Voffset = Vact (3)
If the above equations (2) and (3) are used, the effective display area VR of the image data can be detected. In other words, by shifting the image data in the storage area MR of the image memory 6 and writing it twice, the capacity of the image memory 6 can be expanded in a pseudo manner.
[0087]
The microcomputer 7 detects the effective display area VR using the above equations (1) and (2), thereby optimizing the horizontal total sampling number, optimizing the phase of the sampling clock, and adjusting the horizontal and vertical image display positions. Perform optimization. The method of optimizing the total number of horizontal samplings, optimizing the phase of the sampling clock, and optimizing the horizontal and vertical image display positions are the same as in the first embodiment.
[0088]
As described above, in the video signal processing apparatus according to the present embodiment, even when the effective display area VR of the image data is larger than the storage area MR of the image memory 6, it is possible to realize an optimal image display state. Become.
[0089]
(5) Fifth embodiment
FIG. 9 is a block diagram showing the configuration of the video signal processing apparatus according to the fifth embodiment of the present invention. The video signal processing apparatus of FIG. 9 differs from the video signal processing apparatus of FIG. 1 in the following points.
[0090]
The video signal processing apparatus in FIG. 9 includes a plurality of video signal input terminals 101a, 101b, 101c and a plurality of synchronization signal input terminals 102a, 102b, 102c. Video signals VIa, VIb, and VIc are supplied to the video signal input terminals 101a, 101b, and 101c, respectively. Synchronization signals SYa, SYb, and SYc are applied to the synchronization signal input terminals 102a, 102b, and 102c, respectively. The video signal VIa and the synchronization signal SYa are input from the same video source, the video signal VIb and the synchronization signal SYb are input from the same video source, and the video signal VIc and the synchronization signal SYc are input from the same video source.
[0091]
9 includes a video signal input changeover switch 8 and a synchronization signal input changeover switch 9. The video signal input change-over switch 8 selects one of the video signals VIa, VIb, and VIc input to the video signal input terminals 101a, 101b, and 101c under the control of the microcomputer 7 and supplies the selected signal to the A / D converter 1. . The synchronization signal input changeover switch 9 selects one of the synchronization signals Sya, SYb, and SYc input to the synchronization signal input terminals 102 a, 102 b, and 102 c under the control of the microcomputer 7, and supplies the selected signal to the signal determination circuit 5.
[0092]
The signal discriminating circuit 5 discriminates the scanning frequency and effective resolution of the video source based on the synchronizing signal selected by the synchronizing signal input changeover switch 9 and gives the discrimination result to the microcomputer 7.
[0093]
The microcomputer 7 determines whether or not the selected video signal is a valid signal for the video signal processing device based on the determination result of the signal determination circuit 5. When the selected video signal is a valid signal for the video signal processing device, the microcomputer 7 executes an image display optimization process in the same manner as the video signal processing devices of the first to fourth embodiments. To do.
[0094]
On the other hand, when the selected video signal is a signal that is not valid for the video signal processing apparatus or when no video signal is input, the microcomputer 7 receives a video signal input to another video signal input terminal and The video signal input changeover switch 8 and the synchronization signal input changeover switch 9 are controlled so as to select a synchronization signal input to another synchronization signal input terminal. In this case, the signal determination circuit 5 determines the scanning frequency and effective resolution of the video source based on the synchronization signal selected by the synchronization signal input selector switch 9.
[0095]
The microcomputer 7 repeats the above processing and controls the video signal input selector switch 8 and the synchronization signal input selector switch 9 until a video signal effective for the video signal processing apparatus is selected. When signals that are not valid for the video signal processing apparatus are input to all the video signal input terminals 101a, 101b, and 101c and the synchronization signal input terminals 102a, 102b, and 102c, the video signal input terminal that is selected first and The video signal input changeover switch 8 and the synchronization signal input changeover switch 9 are controlled so as to select the synchronization signal input terminal, and the process is terminated without executing the optimization of the image display.
[0096]
By performing the above processing, in the video signal processing apparatus of FIG. 9, in addition to the same effects as those of the video signal processing apparatuses of the first to fourth embodiments, a minimum of a plurality of video signals is obtained. There is an effect that it is possible to realize an optimal image display state by operation.
[0097]
In the present embodiment, the plurality of video signal input terminals 101a, 101b, 101c and the plurality of synchronization signal input terminals 102a, 102b, 102c correspond to a plurality of input units, the microcomputer 7 corresponds to an input detection means, and the video signal The input changeover switch 8 and the synchronization signal input changeover switch 9 correspond to selection means.
[0098]
(6) Sixth embodiment
FIG. 10 is a block diagram showing the configuration of the video signal processing apparatus according to the sixth embodiment of the present invention. This video signal processing apparatus is used for a projection video display apparatus such as a liquid crystal projector. The video signal processing apparatus of FIG. 10 differs from the video signal processing apparatus of FIG. 1 in the following points.
[0099]
The video signal processing apparatus in FIG. 10 further includes a trapezoidal distortion correction circuit 11 and an inclination detection circuit 12.
[0100]
The tilt detection circuit 12 detects the tilt of the video display device and gives the detection result to the microcomputer 7. The microcomputer 7 sets an optimal correction value in the trapezoidal distortion correction circuit 11 based on the detection result of the inclination detection circuit 12. The trapezoidal distortion correction circuit 11 performs trapezoidal distortion correction and linearity correction (linearity correction) on the video signal VO output from the resolution conversion circuit 2 in accordance with the correction value set by the microcomputer 7, and the corrected video signal VOa is converted into an image. The signal is output from the signal output terminal 103.
[0101]
For example, when the liquid crystal projector is tilted rearward, an originally rectangular image is displayed in a trapezoidal shape on the screen. In this case, the video signal VO is corrected so that an originally rectangular image is displayed in a rectangular shape on the screen.
[0102]
In the video signal processing device according to the present embodiment, in addition to the same effects as those of the video signal processing devices according to the first to fourth embodiments, even when the video display device is tilted, an optimal image display state in consideration of tilt The effect that it becomes possible to implement | achieve is acquired.
[0103]
In the present embodiment, the inclination detection circuit 12 corresponds to an inclination detection unit, and the trapezoidal distortion correction circuit 11 corresponds to a distortion correction unit.
[0104]
(7) Seventh embodiment
FIG. 11 is a block diagram showing the configuration of the video signal processing apparatus according to the seventh embodiment of the present invention. The video signal processing apparatus of FIG. 11 differs from the video signal processing apparatus of FIG. 1 in the following points.
[0105]
The video signal processing apparatus of FIG. 11 further includes a luminance color difference signal-RGB signal matrix conversion circuit 13. In this video signal processing apparatus, a video signal VI in the form of a luminance color difference signal and an RGB signal can be input to the video signal input terminal 101. The luminance color difference signal-RGB signal matrix conversion circuit 13 converts the luminance color difference signal given from the A / D converter 1 into an RGB signal and outputs the RGB signal. The signal discriminating circuit 5 discriminates the scanning frequency and effective resolution of the video source based on the synchronization signal SY and gives the discrimination result to the microcomputer 7. The signal determination circuit 5 determines whether the video signal VI is an RGB signal or a luminance color difference signal based on the synchronization signal SY, and gives the determination result to the microcomputer 7.
[0106]
When the video signal VI input from the video source is an RGB signal, the sync signal SY is a separate sync or a horizontal sync signal and a vertical sync signal in which the horizontal sync signal and the vertical sync signal are separated. When the video signal VI input from the video source is a luminance / color difference signal, the synchronization signal SY is a sync on green in which the synchronization signal is superimposed on the luminance signal. The signal discriminating circuit 5 discriminates the form of the video signal VI using this fact.
[0107]
When the video signal VI is an RGB signal, the microcomputer 7 controls the resolution conversion circuit 2 to directly receive the video signal output from the A / D converter 1. The microcomputer 7 controls the resolution conversion circuit 2 to receive the video signal output from the luminance / color difference signal-RGB signal matrix conversion circuit 13 when the video signal VI is a luminance / color difference signal.
[0108]
In the video signal processing apparatus according to the present embodiment, in addition to the same effects as those of the video signal processing apparatuses according to the first to fourth embodiments, an optimal image display according to the form of the input video signal VI is displayed. The effect that the state can be realized is obtained.
[0109]
In the present embodiment, the signal discriminating circuit 5 corresponds to the form discriminating means, and the luminance / color difference signal-RGB signal matrix conversion circuit 13 corresponds to the form converting means.
[0110]
【The invention's effect】
As described above, according to the first invention, it is possible to realize an optimal image display state for various video signals at low cost and at high speed without adding dedicated hardware.
[0111]
According to the second invention, it is possible to realize an optimal image display state in a short time.
[0112]
According to the third aspect, even when the storage capacity of the storage unit is small, it is possible to realize an optimal image display state.
[0113]
According to the fourth invention, even when the storage capacity of the storage unit is small, it is possible to realize an optimal image display state.
[0114]
According to the fifth aspect, it is possible to realize an optimal image display state with a minimum operation with respect to the input of a plurality of video signals.
[0115]
According to the sixth aspect, even when the video display device is tilted, it is possible to realize an optimal image display state in consideration of the tilt.
[0116]
According to the seventh aspect, it is possible to automatically realize an optimal image display state according to the form of the input video signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a waveform diagram of a video signal for explaining optimization of the total number of horizontal samplings
FIG. 3 is a diagram for explaining the optimization of the phase of the sampling clock;
FIG. 4 is a diagram for explaining optimization of horizontal and vertical image display positions;
FIG. 5 is a flowchart showing image display optimization processing by a microcomputer in the video signal processing apparatus of FIG. 1;
FIG. 6 is a diagram showing a relationship between a storage area of an image memory and an effective display area of image data written in the image memory in the video signal processing apparatus according to the second embodiment of the present invention.
FIG. 7 is a diagram showing a relationship among a storage area of an image memory, an effective display area of image data, and an effective display area of compressed image data in a video signal display apparatus according to a third embodiment of the present invention.
FIG. 8 is a diagram showing a relationship between a storage area of an image memory and an effective display area of image data written in the image memory in a video signal processing apparatus according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a video signal processing apparatus according to a fifth embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a video signal processing apparatus according to a sixth embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a video signal processing apparatus according to a seventh embodiment of the present invention.
[Explanation of symbols]
1 A / D converter
2 Resolution conversion circuit
3 Phase control circuit
4 PLL circuit
5 Signal discrimination circuit
6 Image memory
7 Microcomputer
8 Video signal input selector switch
9 Sync signal input selector switch
11 Trapezoidal distortion correction circuit
12 Tilt detection circuit
13 Luminance color difference signal-RGB signal matrix conversion circuit
101, 101a, 101b, 101c Video signal input terminal
102, 102a, 102b, 102c Sync signal input terminal
103 Video signal output terminal
VI, VIa, VIb, VIc Video signal
SY, SYa, SYb, SYc Sync signal
VO video signal

Claims (7)

A video signal processing apparatus in which an analog video signal including an effective display area to be displayed on a screen of a video display apparatus is input together with a synchronization signal,
Sampling clock generating means for generating a sampling clock by dividing the input synchronization signal;
Phase control means for controlling the phase of the sampling clock generated by the sampling clock generation means;
In response to a sampling clock controlled by the phase control means, signal conversion means for sampling the input analog video signal and converting it to a digital video signal;
Storage means for storing image data;
At the time of image display optimization processing, the digital video signal obtained by the signal conversion means is written into the storage means as image data, and at the time of image display operation, the digital video signal obtained by the signal conversion means is converted into an image. Resolution conversion means for obtaining a video signal having a predetermined scanning frequency and a predetermined resolution by reading the image data stored in the storage means and writing the data in the storage means;
Signal discriminating means for discriminating a scanning frequency and resolution of the inputted analog video signal based on the inputted synchronizing signal;
Correction control means,
The correction control means, during the optimization process of the image display ,
(1) Processing for detecting an effective display area of the analog video signal based on image data stored in the storage means;
(2) A process of setting frequency division ratio correction data for correcting the frequency division ratio of the sampling clock generation means based on the determination result of the signal determination means and the detection result of the effective display area ;
(3) a process of setting phase correction data for correcting the phase of the sampling clock controlled by the phase control means ; and
(4) A video signal processing apparatus characterized in that processing for setting correction data for correcting a writing position of image data to the storage means by the resolution conversion means is performed in this order . The correction control means is configured such that the storage area of the storage means is larger than the effective display area of the digital video signal data obtained by the signal conversion means during the image display optimization process with respect to the resolution conversion means . 2. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus controls the video signal in the effective display area to be written in the storage unit together with the video signal outside the effective display area. The correction control means, when the effective display area of the digital video signal obtained by the signal conversion means is larger than the storage area of the storage means during the image display optimization process with respect to the resolution conversion means 2. The video signal processing apparatus according to claim 1 , wherein the video signal is compressed, and the compressed video signal of the effective display area is controlled to be written in the storage means. The correction control means, when the effective display area of the digital video signal obtained by the signal conversion means is larger than the storage area of the storage means during the image display optimization process with respect to the resolution conversion means 2. The video signal processing apparatus according to claim 1, wherein control is performed so that a part of the video signal in the effective display area is written in the storage unit. A plurality of input units for receiving a plurality of analog video signals and a plurality of synchronization signals;
An input detection unit for detecting an input unit to which an analog video signal that can be displayed on the screen of the video display device is input among the plurality of input units based on a synchronization signal input to each input unit;
And a selection means for selectively giving the video signal and the synchronization signal input to the input unit detected by the input detection means to the signal conversion means and the signal determination means, respectively, during the image display optimization process. The video signal processing apparatus according to claim 1, wherein the video signal processing apparatus is a video signal processing apparatus. Tilt detecting means for detecting the tilt of the video display device;
The image processing apparatus further comprises distortion correction means for correcting the video signal obtained by the resolution conversion means so as to correct image distortion caused by the inclination detected by the inclination detection means. The video signal processing device according to claim 5. Form discriminating means for discriminating the form of the input analog video signal;
The apparatus further comprises a form converting means for converting the analog video signal into a predetermined form based on a result of the form distinguishing means and giving the signal to the signal converting means without conversion. The video signal processing device according to any one of claims 6 to 9.

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