JP6186183B2 - Power converter - Google Patents
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- JP6186183B2 JP6186183B2 JP2013124288A JP2013124288A JP6186183B2 JP 6186183 B2 JP6186183 B2 JP 6186183B2 JP 2013124288 A JP2013124288 A JP 2013124288A JP 2013124288 A JP2013124288 A JP 2013124288A JP 6186183 B2 JP6186183 B2 JP 6186183B2
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本発明は、電力用半導体素子を用いてなる電力変換装置に係り、特に、電力変換装置回路の配線インダクタンスを低減するのに好適な電力変換装置に関する。
The present invention relates to a power conversion device using a power semiconductor element, and more particularly to a power conversion device suitable for reducing wiring inductance of a power conversion device circuit.
電力用半導体素子を用いて、直流電力を交流電力に変換する、交流電力を直流電力に変換する、又は、直流電力を直流電力に変換する電力変換装置において、近年、電力用半導体素子の大電流化とスイッチング速度の高速化が著しい。 In recent years, in power converters that use power semiconductor elements to convert DC power into AC power, convert AC power into DC power, or convert DC power into DC power, large currents in power semiconductor elements And the increase in switching speed is remarkable.
これに伴い、電力用半導体素子のオン、オフの際に生じる電流変化（ｄｉ／ｄｔ）が数ｋＡ／μｓにもなる。 Along with this, the current change (di / dt) that occurs when the power semiconductor element is turned on and off is several kA / μs.
このような電流が流れる配線はインダクタンスＬを有するため、電力用半導体素子スイッチング時にはＬｄｉ／ｄｔで表されるサージ電圧が発生し、このサージ電圧に電力変換装置直流部の電圧を加えた電圧が電力用半導体素子に印加される。 Since the wiring through which such a current flows has an inductance L, a surge voltage represented by Ldi / dt is generated when the power semiconductor element is switched, and a voltage obtained by adding the voltage of the DC unit of the power converter to the surge voltage is the power. Applied to the semiconductor element.
印加される電圧が電力用半導体素子の耐電圧を超えてしまう場合は、電圧変換器直流部の電圧を低下させるか、スナバ回路でサージ電圧を吸収させる等の対策が必要になり、電力用半導体素子の電圧利用率低下や回路の大形化を招く。 If the applied voltage exceeds the withstand voltage of the power semiconductor element, measures such as reducing the voltage of the DC part of the voltage converter or absorbing the surge voltage with a snubber circuit are required. The voltage utilization factor of the element is reduced and the circuit size is increased.
一般に、電力変換を行うには、電力用半導体素子を複数直列に設け、この直列に接続した電力用半導体素子に並列に電力貯蔵部を設けるような構成としている。この各々の電力用半導体素子を動作させて電力貯蔵部との間で電力を授受することで電力変換を行う。 Generally, in order to perform power conversion, a plurality of power semiconductor elements are provided in series, and a power storage unit is provided in parallel with the power semiconductor elements connected in series. Power conversion is performed by operating each of these power semiconductor elements and transferring power to and from the power storage unit.
ここで、電力用半導体素子と電力貯蔵部を電気的に接続するためには導体を用いるところ、この導体に電流が流れるときに、インダクタンスＬに応じて電力用半導体素子スイッチング時にはＬｄｉ／ｄｔで表されるサージ電圧が発生する。 Here, a conductor is used to electrically connect the power semiconductor element and the power storage unit. When a current flows through the conductor, it is expressed by Ldi / dt when the power semiconductor element is switched according to the inductance L. Generated surge voltage.
電力用半導体素子と電力貯蔵部との間を接続するための導体に流れるサージ電圧を抑制するために、例えば特許第３７５０３３８号公報に記載されているように、この導体を覆うように、別の導体を配置する技術が知られている。この導体に誘導電流を生じさせ、電力用半導体素子と電力貯蔵部との間の導体の磁束を打ち消すことで、配線インダクタンスを低減している。 In order to suppress the surge voltage flowing in the conductor for connecting between the power semiconductor element and the power storage unit, for example, as described in Japanese Patent No. 3750338, another conductor is covered so as to cover the conductor. Techniques for arranging conductors are known. By inducing an induced current in the conductor and canceling out the magnetic flux of the conductor between the power semiconductor element and the power storage unit, the wiring inductance is reduced.
しかしながら、サージ電圧を発生させるものは、上記の従来技術で意識されているところの、電力用半導体素子と電力貯蔵部との間の導体の磁束だけではなく、複数配列した電力用半導体素子が作る電気回路の他の部分でも起こり得るものであり、特に、サージ電圧は、電力用半導体素子の配列方向の配線インダクタンスにもよっても発生する。 However, what generates the surge voltage is not only the magnetic flux of the conductor between the power semiconductor element and the power storage unit, which is recognized in the above-described prior art, but also a plurality of arranged power semiconductor elements. This can also occur in other parts of the electric circuit. In particular, the surge voltage is also generated due to the wiring inductance in the arrangement direction of the power semiconductor elements.
例えば、具体的な例を挙げて説明すると、近年、大容量の電力変換装置に対して大電流定格の平型の電力用半導体素子が適用されてきている。電力用半導体素子を４直列接続した３レベル変換器や素子を直列接続して高耐圧化を図った２レベル変換器では積層する素子数が多くなり、素子積層方向の配線インダクタンスが大きくなるという課題があった。 For example, to give a specific example, in recent years, a flat power semiconductor element having a large current rating has been applied to a large-capacity power converter. In a three-level converter in which four power semiconductor elements are connected in series and a two-level converter in which elements are connected in series to increase the breakdown voltage, the number of elements to be stacked increases, and the wiring inductance in the element stacking direction increases. was there.
本発明の目的は、電力用半導体素子の配列方向の配線インダクタンスをも低減でき、電力用半導体素子スイッチング時のサージ電圧を抑制することが可能な電力変換装置を提供することにある。
The objective of this invention is providing the power converter device which can also reduce the wiring inductance of the arrangement direction of a power semiconductor element, and can suppress the surge voltage at the time of power semiconductor element switching.
上記目的を達成するために、本発明は、電力用半導体素子を配列し、前記電力用半導体素子はスイッチング素子を含んだものであり、前記配列は、各々の電力用半導体素子を選択的に動作させることで第１の導体と第２の導体を電力貯蔵部に接続可能となるように構成されるものであって、前記配列方向に沿って延びた導体板を備え、前記導体板は、前記電力用半導体素子、前記第１の導体と前記第２の導体とは絶縁されており、前記導体板は、前記配列に近接配置されると共に、前記電力用半導体素子のうちの少なくとも２つうちの少なくとも一部を覆うように設けられる構成とした。
In order to achieve the above object, the present invention includes power semiconductor elements arranged, and the power semiconductor elements include switching elements, and the arrangement selectively operates each power semiconductor element. The first conductor and the second conductor are configured to be connectable to the power storage unit by including a conductor plate extending along the arrangement direction, and the conductor plate includes the conductor plate, The power semiconductor element, the first conductor and the second conductor are insulated, and the conductor plate is disposed in proximity to the array and includes at least two of the power semiconductor elements. It was set as the structure provided so that at least one part might be covered.
本発明によれば、電力用半導体素子と電力貯蔵部間の配線インダクタンスだけでなく、電力用半導体素子の配列方向の配線インダクタンスをも低減でき、電力用半導体素子スイッチング時のサージ電圧を抑制できる。
ADVANTAGE OF THE INVENTION According to this invention, not only the wiring inductance between a power semiconductor element and a power storage part but the wiring inductance of the arrangement direction of a power semiconductor element can be reduced, and the surge voltage at the time of power semiconductor element switching can be suppressed.
以下、本発明の実施形態を図面ともに説明する。なお、以下の実施例は本発明の一形態を示すものであり、本発明は要旨を逸脱しない限り、他の形態を含むものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following examples show one form of the present invention, and the present invention includes other forms unless departing from the gist.
実施例1では、双方向チョッパ回路を例として、図１〜図６を用いて本発明の実施形態を説明する。 In Example 1, an embodiment of the present invention will be described using a bidirectional chopper circuit as an example with reference to FIGS.
図１は本発明による第１の実施形態を表した図である。図２に図１の双方向チョッパ回路の回路図を示す。双方向チョッパ回路は２個の電力用半導体素子１と電力貯蔵部２から構成される。 FIG. 1 is a diagram showing a first embodiment according to the present invention. FIG. 2 shows a circuit diagram of the bidirectional chopper circuit of FIG. The bidirectional chopper circuit includes two power semiconductor elements 1 and a power storage unit 2.
図１及び図２を用いて回路構成について説明する。電力貯蔵部２の一方極性は第１の導体３に接続される。第１の導体３と端子１００との間には、放熱器６を介して、電力用半導体素子１−１が接続される。ここで、電力用半導体素子１−１…を電力用半導体素子１と総称する。また、スイッチング素子１ａ、ダイオード１ｂ、導体３、４、及び電力貯蔵部２についても、同様に、各々添字記号が付されたものの総称とする。 The circuit configuration will be described with reference to FIGS. One polarity of the power storage unit 2 is connected to the first conductor 3. A power semiconductor element 1-1 is connected between the first conductor 3 and the terminal 100 through a radiator 6. Here, the power semiconductor elements 1-1... Are collectively referred to as the power semiconductor elements 1. Similarly, the switching element 1a, the diode 1b, the conductors 3 and 4, and the power storage unit 2 are also generically named with subscripts attached thereto.
この電力用半導体素子１−１は他の電力用半導体素子１…と同様に、スイッチング素子１ａとダイオード１ｂで構成される。スイッチング素子１ａは例えばＩＧＢＴ素子が用いられるが、ＩＧＢＴの代わりにバイポーラトランジスタ，パワーＭＯＳトランジスタ，ゲートターンオフサイリスタ，静電誘導サイリスタ等が使用できる。 This power semiconductor element 1-1 is composed of a switching element 1a and a diode 1b in the same manner as the other power semiconductor elements 1. For example, an IGBT element is used as the switching element 1a, but a bipolar transistor, a power MOS transistor, a gate turn-off thyristor, an electrostatic induction thyristor, or the like can be used instead of the IGBT.
電力用半導体素子１については両側が平型形状をなしており、この両方の平型形状の部分が端子を形成する。すなわち、この平型形状の端子が他の伝導体と接触することで、この電力用半導体素子１を構成するスイッチング素子１ａ及びダイオード１ｂと電気的な接続を確保する。具体的には、該他の伝導体との間に付勢力を付することで電気的な接続を確保される。 Both sides of the power semiconductor element 1 have a flat shape, and both flat portions form terminals. That is, the flat-shaped terminal is in contact with another conductor, thereby ensuring electrical connection with the switching element 1a and the diode 1b constituting the power semiconductor element 1. Specifically, an electrical connection is ensured by applying a biasing force to the other conductor.
電力貯蔵部２の他方極性は第２の導体４に接続される。第２の導体４は端子１０１に接続される。第２の導体４（端子１０１）と端子１００との間には、放熱器６を介して、電力用半導体素子１−２が接続される。第１の導体３と第２の導体４は各々ボルト２００によって電力貯蔵部２に機械的に固定することで電気的な接続を得ている。 The other polarity of the power storage unit 2 is connected to the second conductor 4. The second conductor 4 is connected to the terminal 101. A power semiconductor element 1-2 is connected between the second conductor 4 (terminal 101) and the terminal 100 via a radiator 6. The first conductor 3 and the second conductor 4 are each electrically fixed to the power storage unit 2 by bolts 200 to obtain an electrical connection.
第１の導体３、電力用半導体素子１−１、電力用半導体素子１−２、第２の導体４は順に互いに接するように垂直方向に配列され、第１の導体３と第２の導体４を両端外側から押圧することで、これら素子の電気的な接続を保つように構成される。第１の導体３、電力用半導体素子１−１、電力用半導体素子１−２、第２の導体４の図１における配列は例示的であり、これらの電気素子が互いに電機気的に接続されるのであれば、どのような方向に配列しても良い。 The first conductor 3, the power semiconductor element 1-1, the power semiconductor element 1-2, and the second conductor 4 are arranged in a vertical direction so as to be in contact with each other in order, and the first conductor 3 and the second conductor 4. Is configured to keep the electrical connection of these elements by pressing from the outside of both ends. The arrangement of the first conductor 3, the power semiconductor element 1-1, the power semiconductor element 1-2, and the second conductor 4 in FIG. 1 is exemplary, and these electric elements are electrically connected to each other. If so, they may be arranged in any direction.
電力用半導体素子１−１のスイッチング素子１ａと電力用半導体素子１−２のスイッチング素子１ａの一方を導通させる（このときに他方は遮断する）ことで、電力貯蔵部２の電圧を端子１００と端子１０１の間に出力させたり、あるいは、単に端子１００と端子１０１を接続することで、電力変換を行う。 By making one of the switching element 1a of the power semiconductor element 1-1 and the switching element 1a of the power semiconductor element 1-2 conductive (the other is cut off at this time), the voltage of the power storage unit 2 is connected to the terminal 100. Power conversion is performed by outputting between the terminals 101 or simply connecting the terminals 100 and 101.
図１において、第１の導体３、電力用半導体素子１−１、電力用半導体素子１−２、第２の導体４に近接して、導体板５を配置する。導体板５は絶縁体８を介して放熱器６に近接配置もしくは、取り付けられる。例えば、絶縁体８は放熱器６に接するように、導体板５は絶縁体８に接するように設けられる。 In FIG. 1, a conductor plate 5 is disposed adjacent to the first conductor 3, the power semiconductor element 1-1, the power semiconductor element 1-2, and the second conductor 4. The conductor plate 5 is disposed close to or attached to the radiator 6 via the insulator 8. For example, the conductor 8 is provided in contact with the insulator 8 so that the insulator 8 is in contact with the radiator 6.
導体板５は、上下方向としては、少なくとも第１の導体３から第２の導体４まで延びている。具体的には、第１の導体３の少し上側から、第２の導体４の少し下側まで延びている。導体板５は、左右方向としては、少なくとも、左側において放熱器６の一方端から右側において電力貯蔵部２まで延びている。具体的には、左側において放熱器６より少し突出するように、右側においては電力貯蔵部２と重なるように延びている。 The conductor plate 5 extends at least from the first conductor 3 to the second conductor 4 in the vertical direction. Specifically, it extends from a little above the first conductor 3 to a little below the second conductor 4. In the left-right direction, the conductor plate 5 extends at least from the one end of the radiator 6 on the left side to the power storage unit 2 on the right side. Specifically, it extends to overlap with the power storage unit 2 on the right side so that it protrudes slightly from the radiator 6 on the left side.
ここで、上下或いは左右との文言を用いて説明したが、図１における例示に沿って説明したのであり、各素子の配置は異なっていても良く、その場合には、その配置に沿った表記になるのはもちろんである。 Here, the description is made using the terms “upper” and “left”, “right”, but it has been described according to the example in FIG. 1, and the arrangement of each element may be different. Of course.
図１では、導体板５を、双方向チョッパ回路の配線インダクタンス低減を目的として、第１の導体３と第２の導体４の配列方向に直行する方向に近接配置している。そのため、電力用半導体素子１のスイッチング時の回路の電流変化により導体板５に誘導電流が発生する。この誘導電流により回路の配線インダクタンスを低減できる。 In FIG. 1, the conductor plate 5 is disposed close to the direction perpendicular to the arrangement direction of the first conductor 3 and the second conductor 4 for the purpose of reducing the wiring inductance of the bidirectional chopper circuit. Therefore, an induced current is generated in the conductor plate 5 due to a current change in the circuit during switching of the power semiconductor element 1. This induced current can reduce the wiring inductance of the circuit.
図１の双方向チョッパ回路と導体板５の間の距離は短い方が回路の配線インダクタンスの低減効果は大きい。そのため、双方向チョッパ回路と導体板５の間に絶縁体８を挟み、双方向チョッパ回路と導体板５の間の絶縁性を確保できる範囲でその間の距離を極力短くした方が配線インダクタンスの低減効果が大きい。 The shorter the distance between the bidirectional chopper circuit of FIG. 1 and the conductor plate 5, the greater the effect of reducing the wiring inductance of the circuit. For this reason, the wiring inductance is reduced when the insulator 8 is sandwiched between the bidirectional chopper circuit and the conductor plate 5 and the distance between the bidirectional chopper circuit and the conductor plate 5 is shortened as much as possible within a range in which insulation can be ensured. Great effect.
尚、図示していないが、導体板５が浮遊電位となるため、高抵抗の抵抗体の片端を接続し、その抵抗体の他端は基準電位に接続しておくことで導体板５に電荷が蓄積することを防ぐことができる。 Although not shown, since the conductor plate 5 has a floating potential, one end of a high-resistance resistor is connected, and the other end of the resistor is connected to a reference potential, whereby the conductor plate 5 is charged. Can be prevented from accumulating.
図３（１）に双方向チョッパ回路の電力貯蔵部２を直流電源７とし、高圧側端子１００と低圧側端子１０１の間に負荷抵抗３０４と負荷インダクタンス３０５を接続し、回路の配線インダクタンス（３００〜３０３）を考慮した回路図を示す。図３を用いて、回路の配線インダクタンスによって電力用半導体素子１のスイッチング時にサージ電圧が発生する原理を説明する。 In FIG. 3 (1), the power storage unit 2 of the bidirectional chopper circuit is a DC power source 7, a load resistor 304 and a load inductance 305 are connected between the high-voltage side terminal 100 and the low-voltage side terminal 101, and the circuit wiring inductance (300 To 303) are shown. The principle that a surge voltage is generated when the power semiconductor element 1 is switched due to the wiring inductance of the circuit will be described with reference to FIG.
図３（２）に図３（１）において、高圧側の電力用半導体素子１オン時の電流経路４００を示す。このときは、高圧側の電力用半導体素子１を介して、負荷に電流が流れる。図３（３）に高圧側の電力用半導体素子１ターンオフ後の電流経路４０１を示す。高圧側の電力用半導体素子１がターンオフすると電流は低圧側の電力用半導体素子１の還流ダイオード１ｂを介して負荷を還流する。図３（４）に高圧側の電力用半導体素子１がターンオフしたことにより、電流変化が起こる経路４０２を示す。この経路４０２の配線インダクタンスが回路の電流変化を妨げる方向にサージ電圧を発生させる。 FIG. 3B shows a current path 400 when the high-voltage power semiconductor element 1 is turned on in FIG. At this time, a current flows through the load via the power semiconductor element 1 on the high voltage side. FIG. 3C shows the current path 401 after the high-voltage side power semiconductor element 1 is turned off. When the power semiconductor element 1 on the high voltage side is turned off, the current flows back to the load via the return diode 1b of the power semiconductor element 1 on the low voltage side. FIG. 3 (4) shows a path 402 in which a current change occurs when the high-voltage power semiconductor element 1 is turned off. The wiring inductance of the path 402 generates a surge voltage in a direction that hinders the current change of the circuit.
図４に高圧側の電力用半導体素子１ターンオフ時のコレクタ電流ｉcとコレクタ−エミッタ間電圧Ｖceの波形示す。ここで、Ｖdcは直流電源７の電圧である。高圧側の電力用半導体素子１ターンオフに伴うコレクタ電流ｉcのｄｉc／ｄｔと電流変化が起こる経路４０２の配線インダクタンスの合計値の乗算により、サージ電圧ＶLの大きさは決まる。 4 the collector current i c and collector when the power semiconductor device 1 turns off the high-pressure side - shows the waveform of the emitter voltage V ce. Here, V dc is the voltage of the DC power supply 7. The magnitude of the surge voltage V L is determined by multiplying di c / dt of the collector current ic accompanying the turn-off of the power semiconductor element 1 on the high voltage side and the total value of the wiring inductance of the path 402 where the current change occurs.
図５は図１の双方向チョッパ回路の側面図である。図５を用いて導体板５により、回路の配線インダクタンスが低減できる原理について説明する。図５（１）において電流経路４０３に反時計回りに流れる電流がつくる磁束が導体板と鎖交する向き４０４は紙面の裏側から表側である。これにより、図５（２）に示すように、導体板には時計周りに誘導電流４０５が発生する。この誘導電流４０５は電流経路４０３を流れる電流がつくる磁束を打ち消す向き４０６（紙面の表側から裏側）に磁束をつくる。この導体板５の誘導電流４０５がつくる磁束が電流経路４０３を流れる電流がつくる磁束を打ち消すことで、電流経路４０３の配線インダクタンスを低減できる。 FIG. 5 is a side view of the bidirectional chopper circuit of FIG. The principle that the wiring inductance of the circuit can be reduced by the conductor plate 5 will be described with reference to FIG. In FIG. 5A, the direction 404 in which the magnetic flux generated by the current flowing counterclockwise in the current path 403 is linked to the conductor plate is from the back side to the front side of the drawing. As a result, as shown in FIG. 5B, an induced current 405 is generated clockwise in the conductor plate. The induced current 405 generates a magnetic flux in a direction 406 (from the front side to the back side of the paper) that cancels out the magnetic flux generated by the current flowing through the current path 403. The magnetic flux generated by the induced current 405 of the conductor plate 5 cancels out the magnetic flux generated by the current flowing through the current path 403, whereby the wiring inductance of the current path 403 can be reduced.
図５（２）に示した誘導電流４０５は大きいほど、電流経路４０３の配線インダクタンスを低減効果も大きい。誘導電流４０５の大きさは導体板５に鎖交する磁束の変化によって発生した誘導起電力と導体板５の抵抗値で決まる。そのため、導体板５は導電性に優れた銅やアルミ等が望ましい。また、電力用半導体素子１のスイッチング時に発生する高周波の誘導電流は、表皮効果により導体板５の表面にのみ流れることから、その厚みを薄くしても本発明の効果を得られる。 As the induced current 405 shown in FIG. 5B is larger, the effect of reducing the wiring inductance of the current path 403 is larger. The magnitude of the induced current 405 is determined by the induced electromotive force generated by the change of the magnetic flux linked to the conductor plate 5 and the resistance value of the conductor plate 5. For this reason, the conductive plate 5 is preferably made of copper, aluminum or the like having excellent conductivity. In addition, since the high-frequency induced current generated when the power semiconductor element 1 is switched flows only on the surface of the conductor plate 5 due to the skin effect, the effect of the present invention can be obtained even if the thickness is reduced.
図１の導体板５は、図６のように環状でもよい。 The conductor plate 5 in FIG. 1 may be annular as shown in FIG.
以下、他の実施例を示すが、実施例１と異なる部分を中心に説明する。よって、説明が省略されている部分は、基本的には、実施例１と同様である。同じ構成要素には同じ符号が付されている。 In the following, other embodiments will be described, but the description will focus on the differences from the first embodiment. Therefore, the parts that are not described are basically the same as those in the first embodiment. The same components are denoted by the same reference numerals.
図７は本発明による第２の実施形態を表した図である。本実施例では、素子２直列の双方向チョッパ回路に本発明を適用した例を説明する。すなわち、図１及び図２における電力用半導体素子１−１の代わりに２つの電力用半導体素子である電力用半導体素子１−１−１及び電力用半導体素子１−１−２を配置し、電力用半導体素子１−２の代わりに２つの電力用半導体素子である電力用半導体素子１−２−１及び電力用半導体素子１−２−２を配置した。 FIG. 7 is a diagram showing a second embodiment according to the present invention. In this embodiment, an example in which the present invention is applied to a bidirectional chopper circuit in which elements 2 are in series will be described. That is, the power semiconductor element 1-1-1 and the power semiconductor element 1-1-2 which are two power semiconductor elements are arranged instead of the power semiconductor element 1-1 in FIGS. Instead of the power semiconductor element 1-2, the power semiconductor element 1-2-1 and the power semiconductor element 1-2-2 which are two power semiconductor elements are arranged.
ここで、第１の導体３、電力用半導体素子１−１−１、電力用半導体素子１−１−２、電力用半導体素子１−２−１、電力用半導体素子１−２−２、第２の導体４の順に垂直方向に配列される。導体板５は、上下方向としては、少なくとも第１の導体３から第２の導体４まで延びている。具体的には、第１の導体３の少し上側から、第２の導体４の少し下側まで延びている。 Here, the first conductor 3, the power semiconductor element 1-1-1, the power semiconductor element 1-1-2, the power semiconductor element 1-2-1, the power semiconductor element 1-2-2, Two conductors 4 are arranged in the vertical direction in this order. The conductor plate 5 extends at least from the first conductor 3 to the second conductor 4 in the vertical direction. Specifically, it extends from a little above the first conductor 3 to a little below the second conductor 4.
図７の回路構成を図８に示す。図７は双方向チョッパ回路の高圧側と低圧側の電力用半導体素子１を各々２直列接続し、素子の高圧化を図ったものである。素子２直列の双方向チョッパ回路は４個の電力用半導体素子１と電力貯蔵部２から構成される。 The circuit configuration of FIG. 7 is shown in FIG. FIG. 7 shows an example in which two high-voltage and low-voltage power semiconductor elements 1 of a bidirectional chopper circuit are connected in series to increase the voltage of the elements. The bidirectional chopper circuit in series with the element 2 includes four power semiconductor elements 1 and a power storage unit 2.
素子２直列の双方向チョッパ回路は図２の双方向チョッパ回路と比較して、積層する
電力用半導体素子１の数が２個多く、積層方向の配線インダクタンスも増加する。そのため、導体板５による配線インダクタンス低減効果も高い。
Compared with the bidirectional chopper circuit of FIG. 2, the bidirectional chopper circuit in series with the element 2 has two more power semiconductor elements 1 to be stacked, and the wiring inductance in the stacking direction also increases. Therefore, the wiring inductance reduction effect by the conductor plate 5 is also high.
図７の導体板５は図６のように環状でもよい。 The conductor plate 5 of FIG. 7 may be annular as shown in FIG.
図９は本発明による第３の実施形態を表した図である。本実施例では、複数枚の導体板５を配置し、回路の配線インダクタンス低減効果を高めた例を説明する。 FIG. 9 is a diagram showing a third embodiment according to the present invention. In the present embodiment, an example will be described in which a plurality of conductor plates 5 are arranged to increase the effect of reducing the wiring inductance of the circuit.
図９では回路の配線インダクタンスの低減効果を高めることを目的として２枚の導体板５を素子２直列の双方向チョッパ回路の第１の導体３と第２の導体４の配列方向に直行する方向に近接配置している。図７の構成と比較して、図９の構成のほうが回路の配線インダクタンス低減効果が高い。 In FIG. 9, the direction in which the two conductor plates 5 are orthogonal to the arrangement direction of the first conductor 3 and the second conductor 4 of the bidirectional chopper circuit in series with the element 2 for the purpose of enhancing the effect of reducing the wiring inductance of the circuit. Is located close to. Compared with the configuration of FIG. 7, the configuration of FIG. 9 has a higher effect of reducing the wiring inductance of the circuit.
図１０に素子２直列の双方向チョッパ回路の正面図を示す。図１０に示すように回路と導体板５との間隔をｄとしたときの図７の構成と図９の構成の配線インダクタンス低減効果を図１１に示す。図７の構成と比較して、図９の構成のほうが回路の配線インダクタンス低減効果が高いことがわかる。また、間隔ｄが短い方が配線インダクタンス低減効果が高いことがわかる。ここで図１１縦軸の配線インダクタンス低減効果[％]は、導体板５なしの場合の図１２に示す電力貯蔵部２の正極端子から負極端子までの経路４０７の配線インダクタンスを１００％としたときの導体板５による配線インダクタンス低減値の比を示す。 FIG. 10 shows a front view of a bidirectional chopper circuit in which the elements 2 are in series. FIG. 11 shows the wiring inductance reduction effect of the configuration of FIG. 7 and the configuration of FIG. 9 when the distance between the circuit and the conductor plate 5 is d as shown in FIG. It can be seen that the configuration of FIG. 9 is more effective in reducing the wiring inductance of the circuit than the configuration of FIG. It can also be seen that the shorter the distance d, the higher the wiring inductance reduction effect. Here, the wiring inductance reduction effect [%] on the vertical axis in FIG. 11 is obtained when the wiring inductance of the path 407 from the positive terminal to the negative terminal of the power storage unit 2 shown in FIG. The ratio of the wiring inductance reduction value by the conductor plate 5 is shown.
図９では、片方の導体板５に孔をあけて電力用半導体素子１の水冷用配管９を通している。２枚の導体板５を配置する場合、放熱器６への水冷用配管９の取り付けが困難になるため、導体板５に孔をあけることで、導体板５が配置されている面からでも水冷用配管９の取り付けが可能になる。水冷用配管９は、回路と導体板５間を絶縁するために絶縁体である必要がある。 In FIG. 9, a hole is made in one conductor plate 5 and the water cooling pipe 9 of the power semiconductor element 1 is passed through. When two conductor plates 5 are arranged, it is difficult to attach the water cooling pipe 9 to the radiator 6. Therefore, by making a hole in the conductor plate 5, water cooling is performed even from the surface where the conductor plate 5 is arranged. The piping 9 can be attached. The water cooling pipe 9 needs to be an insulator in order to insulate between the circuit and the conductor plate 5.
図９の導体板５は図６のように環状でもよい。 The conductor plate 5 of FIG. 9 may be annular as shown in FIG.
図１３は本発明による第４の実施形態を表した図である。本実施例では、シングルスタック構成の３レベルインバータに本発明を適用した例について説明する。 FIG. 13 is a diagram showing a fourth embodiment according to the present invention. In this embodiment, an example in which the present invention is applied to a three-level inverter having a single stack configuration will be described.
図１３の回路構成を図１４に示す。３レベルインバータ回路は４個の電力用半導体素子１と２個のダイオードと２個の電力貯蔵部２から構成される。また、図１５にシングルスタック構成の３レベルインバータの側面図を示す。シングルスタック構成では１つのスタックに４個の電力用半導体素子１と２個のダイオードが積層されている。 The circuit configuration of FIG. 13 is shown in FIG. The three-level inverter circuit includes four power semiconductor elements 1, two diodes, and two power storage units 2. FIG. 15 is a side view of a three-level inverter having a single stack configuration. In the single stack configuration, four power semiconductor elements 1 and two diodes are stacked in one stack.
図において、電力貯蔵部２−１と電力貯蔵部２−２が直列に接続され、その直列接続された両端は、各々、第１の導体３−１と第２の導体４−２に接続される。ここで、第１の導体３−１は高電位を形成しており、一方、第２の導体４−２は低電位を形成する。 In the figure, the power storage unit 2-1 and the power storage unit 2-2 are connected in series, and both ends connected in series are connected to the first conductor 3-1 and the second conductor 4-2, respectively. The Here, the first conductor 3-1 forms a high potential, while the second conductor 4-2 forms a low potential.
第１の導体３−１と第２の導体４−２の間には、電力用半導体素子１−１０、電力用半導体素子１−１１、電力用半導体素子１−１２、電力用半導体素子１−１３が直列に接続される。この直列接続された電力用半導体素子１−１０、電力用半導体素子１−１１、電力用半導体素子１−１２、電力用半導体素子１−１３において、電力用半導体素子１−１１と電力用半導体素子１−１２の接続点は端子１０２が形成される。また、電力用半導体素子１−１０と電力用半導体素子１−１１の接続点と、電力用半導体素子１−１２と電力用半導体素子１−１３の接続点の間には、ダイオード１ｂ−1とダイオード１ｂ−２が直列に接続される。さらに、ダイオード１ｂ−1とダイオード１ｂ−２の接続点は、電力貯蔵部２−１と電力貯蔵部２−２の接続点と接続される。この接続点は、第１の導体３−２あるいは第２の導体４−１として形成され、中間電位を形成する。 Between the first conductor 3-1 and the second conductor 4-2, a power semiconductor element 1-10, a power semiconductor element 1-11, a power semiconductor element 1-12, and a power semiconductor element 1- 13 are connected in series. In the power semiconductor element 1-10, the power semiconductor element 1-11, the power semiconductor element 1-12, and the power semiconductor element 1-13 that are connected in series, the power semiconductor element 1-11 and the power semiconductor element A terminal 102 is formed at a connection point 1-12. Between the connection point between the power semiconductor element 1-10 and the power semiconductor element 1-11 and between the connection point between the power semiconductor element 1-12 and the power semiconductor element 1-13, the diode 1b-1 Diode 1b-2 is connected in series. Furthermore, the connection point between the diode 1b-1 and the diode 1b-2 is connected to the connection point between the power storage unit 2-1 and the power storage unit 2-2. This connection point is formed as the first conductor 3-2 or the second conductor 4-1, and forms an intermediate potential.
このような構成において、電力用半導体素子１−１０のスイッチング素子１ａ、電力用半導体素子１−１１のスイッチング素子１ａ、電力用半導体素子１−１２のスイッチング素子１ａ、電力用半導体素子１−１３のスイッチング素子１ａの各々を選択的に動作させることで、端子１０２には、低電位、中間電位、高電位のいずれかが出力されて直流電力を交流電力に変換動作するか、あるいは、端子１０２に加えられた交流電力を直流の低電位と高電位に係る直流電力に変換動作する。 In such a configuration, the switching element 1a of the power semiconductor element 1-10, the switching element 1a of the power semiconductor element 1-11, the switching element 1a of the power semiconductor element 1-12, and the power semiconductor element 1-13 By selectively operating each of the switching elements 1a, either a low potential, an intermediate potential, or a high potential is output to the terminal 102 to convert DC power into AC power, or The applied AC power is converted into DC power having a low DC potential and a high potential.
図１３の導体板５は図６のように環状でもよい。 The conductor plate 5 of FIG. 13 may be annular as shown in FIG.
図１６は本発明による第５の実施形態を表した図である。本実施例では、ダブルスタック構成Ａの３レベルインバータに本発明を適用した例について説明する。 FIG. 16 is a diagram showing a fifth embodiment according to the present invention. In this embodiment, an example in which the present invention is applied to a three-level inverter having a double stack configuration A will be described.
図１６の回路構成は図１３と同様に図１４である。また、図１７にダブルスタック構成Ａの３レベルインバータの正面図を示す。ダブルスタック構成Ａでは１つ目のスタックに４個の電力用半導体素子１が、２つ目のスタックに２個のダイオード１ｂがそれぞれ積層されている。 The circuit configuration of FIG. 16 is FIG. 14 as in FIG. FIG. 17 is a front view of a three-level inverter having a double stack configuration A. In the double stack configuration A, four power semiconductor elements 1 are stacked in the first stack, and two diodes 1b are stacked in the second stack.
図１７に示す導体板５と回路間の間隔ｘが小さいほうが回路の配線インダクタンス低減効果は大きい。そのため、導体板５の両側を絶縁体８で挟みこみ間隔ｘをできるだけ、短くすることが望ましい。尚、図１７で導体板５の絶縁体８に挟まれていない残り２面も回路との絶縁距離をとる必要がある。 As the distance x between the conductor plate 5 and the circuit shown in FIG. Therefore, it is desirable to sandwich the both sides of the conductor plate 5 with the insulator 8 and make the interval x as short as possible. In FIG. 17, the remaining two surfaces of the conductor plate 5 that are not sandwiched between the insulators 8 need to have an insulation distance from the circuit.
図１６のようなダブルスタック構成についても図１８のように複数枚の導体板５を配置し、回路の配線インダクタンス低減効果を高めることができる。 Also in the double stack configuration as shown in FIG. 16, a plurality of conductor plates 5 can be arranged as shown in FIG. 18 to increase the effect of reducing the wiring inductance of the circuit.
図１６、図１８の導体板５は図６のように環状でもよい。 The conductor plate 5 of FIGS. 16 and 18 may be annular as shown in FIG.
図１９は本発明による第６の実施形態を表した図である。本実施例では、ダブルスタック構成Ａの３レベルインバータの第１の導体３と第２の導体４の配列方向に直行する方向に導体板５近接配置したことに加え、第１の導体３と第２の導体４の板厚方向に対する投影面と少なくとも一部で重なる部分と、重ならない部分ができるように他の導体板１１を近接配置した例である。 FIG. 19 is a diagram showing a sixth embodiment according to the present invention. In the present embodiment, the first conductor 3 and the second conductor 4 are arranged close to each other in the direction orthogonal to the arrangement direction of the first conductor 3 and the second conductor 4 of the three-level inverter of the double stack configuration A. This is an example in which another conductor plate 11 is arranged close to each other so that a portion that overlaps at least a part of the projection surface of the second conductor 4 with respect to the plate thickness direction and a portion that does not overlap.
図２０は図１９の右側面図である。図２０からわかるように、第１の導体３−１と第２の導体４−２の板圧方向に対する投影面に間隔ｌをあけて他の導体板１１を近接配置している。他の導体板１１と第１の導体３−１や第２の導体４−２は、電気的に１点で接続されている。他の導体板１１と第１の導体３−１や第２の導体４−２の間の間隔ｌは短い方が配線インダクタンスの低減効果が高い。 20 is a right side view of FIG. As can be seen from FIG. 20, the other conductor plate 11 is disposed close to the projection surface of the first conductor 3-1 and the second conductor 4-2 with respect to the plate pressure direction with an interval l. The other conductor plate 11 and the first conductor 3-1 and the second conductor 4-2 are electrically connected at one point. The shorter the distance l between the other conductor plate 11 and the first conductor 3-1 or the second conductor 4-2, the higher the effect of reducing the wiring inductance.
図２０のように導体板５により、素子積層方向の配線インダクタンスを低減し、他の導体板１１により、素子と電力貯蔵部２の間の配線インダクタンスを低減することで、図１６の構成と比較して配線インダクタンスの低減効果を高めることができる。 Compared with the configuration of FIG. 16 by reducing the wiring inductance in the element stacking direction with the conductor plate 5 as shown in FIG. 20 and reducing the wiring inductance between the element and the power storage unit 2 with the other conductor plate 11. Thus, the effect of reducing the wiring inductance can be enhanced.
図１９の導体板５は図６のように環状でもよい。 The conductor plate 5 in FIG. 19 may be annular as shown in FIG.
図１９の導体板５を図１８のように複数枚配置することで配線インダクタンス低減効果を高めることができる。 By arranging a plurality of the conductor plates 5 of FIG. 19 as shown in FIG. 18, the effect of reducing the wiring inductance can be enhanced.
図２１は本発明による第７の実施形態を表した図である。本実施例では、ダブルスタック構成Ｂの３レベルインバータに本発明を適用した例である。 FIG. 21 is a diagram showing a seventh embodiment according to the present invention. In this embodiment, the present invention is applied to a three-level inverter having a double stack configuration B.
本実施例では、実施例６における電力用半導体素子１−１０、電力用半導体素子１−１１、電力用半導体素子１−１２、電力用半導体素子１−１３の各々からダイオード１ｂを除き、その代わりに、電力用半導体素子１−１０のダイオード１ｂ、電力用半導体素子１−１１のダイオード１ｂのダイオード１ｂ、電力用半導体素子１−１２のダイオード１ｂ、電力用半導体素子１−１３のダイオード１ｂに代えて、ダイオード１ｂ-１０、ダイオード１ｂ-１１、ダイオード１ｂ-１２、ダイオード１ｂ-１３として構成している。 In the present embodiment, the diode 1b is excluded from each of the power semiconductor element 1-10, the power semiconductor element 1-11, the power semiconductor element 1-12, and the power semiconductor element 1-13 in the sixth embodiment, and instead In place of the diode 1b of the power semiconductor element 1-10, the diode 1b of the diode 1b of the power semiconductor element 1-11, the diode 1b of the power semiconductor element 1-12, and the diode 1b of the power semiconductor element 1-13. The diode 1b-10, the diode 1b-11, the diode 1b-12, and the diode 1b-13 are configured.
図２１の回路構成は図１３と同様に図１４である。また、図２２にダブルスタック構成Ｂの３レベルインバータの正面図を示す。ダブルスタック構成Ｂでは、変換器の電流容量を増加させるために、４つの電力用半導体素子１をそれぞれ４つの自己消孤型素子１ａとダイオード１ｂに分割している。 The circuit configuration of FIG. 21 is FIG. 14 as in FIG. FIG. 22 is a front view of a three-level inverter having a double stack configuration B. In the double stack configuration B, in order to increase the current capacity of the converter, the four power semiconductor elements 1 are divided into four self-extinguishing elements 1a and diodes 1b, respectively.
図２１の導体板５は図６のように環状でもよい。 The conductor plate 5 of FIG. 21 may be annular as shown in FIG.
図２１の導体板５は図１８のように複数枚配置することで配線インダクタンス低減効果を高めることができる。 The conductor plate 5 of FIG. 21 can enhance the wiring inductance reduction effect by arranging a plurality of conductor plates 5 as shown in FIG.
図２１に図１９のように第１の導体３と第２の導体４の板厚方向に対する投影面と少なくとも一部で重なる部分と、重ならない部分ができるように他の導体板１１を近接配置することで、配線インダクタンス低減効果を高めることができる。
As shown in FIG. 21, the other conductor plates 11 are arranged close to each other so that a portion that overlaps at least a portion of the projection surface of the first conductor 3 and the second conductor 4 with respect to the plate thickness direction and a portion that does not overlap are formed. By doing so, the wiring inductance reduction effect can be enhanced.
１ 電力用半導体素子
１ａ 自己消孤型素子
１ｂ ダイオード
２ 電力貯蔵部
３ 第１の導体
４ 第２の導体
５ 導体板
６ 放熱器
７ 直流電源
８ 絶縁体
９ 水冷用配管
１０ 平型の絶縁体
１１ 他の導体板
１００ 双方向チョッパ回路の高圧側端子
１０１ 双方向チョッパ回路の低圧側端子
１０２ ３レベルインバータ回路の出力端子
１０３ スタック間配線導体
２００ ネジ
３００ 双方向チョッパ回路の直流電源７と高圧側の電力用半導体素子１の間の配線インダクタンス
３０１ 双方向チョッパ回路の高圧側の電力用半導体素子１と高圧側端子１００の間の配線インダクタンス
３０２ 双方向チョッパ回路の高圧側端子１００と低圧側の電力用半導体素子端子１の間の配線インダクタンス
３０３ 双方向チョッパ回路の低圧側の電力用半導体素子端子１と直流電源７の間の配線インダクタンス
３０４ 負荷抵抗
３０５ 負荷インダクタンス
４００ 双方向チョッパ回路の高圧側の電力用半導体素子１がオン時の電流経路
４０１ 双方向チョッパ回路の高圧側の電力用半導体素子１ターンオフ後の電流経路
４０２ 双方向チョッパ回路の高圧側電力用半導体素子１ターンオフにより電流変化が起こる経路
４０３ 電流経路
４０４ 電流経路４０３を反時計方向に流れる電流が作る磁束が導体板と鎖交する向き（紙面表側から裏側）
４０５ 電流経路４０３を流れる電流が作る磁束により導体板に発生する誘導電流
４０６ 誘導電流がつくる磁束の方向（紙面裏側から表側）
４０７ 素子２直列の双方向チョッパ回路の電力貯蔵部２の正極端子から負極端子までの経路
DESCRIPTION OF SYMBOLS 1 Power semiconductor element 1a Self-extinguishing element 1b Diode 2 Power storage part 3 1st conductor 4 2nd conductor 5 Conductor plate 6 Radiator 7 DC power supply 8 Insulator 9 Water cooling pipe 10 Flat insulator 11 Other conductor plate 100 High-voltage side terminal 101 of bidirectional chopper circuit Low-voltage side terminal 102 of bidirectional chopper circuit Output terminal 103 of 3-level inverter circuit Inter-stack wiring conductor 200 Screw 300 DC power supply 7 of the bidirectional chopper circuit and the high-voltage side Wiring inductance 301 between power semiconductor element 1 Wiring inductance 302 between high-voltage side power semiconductor element 1 and high-voltage side terminal 100 of the bidirectional chopper circuit High-voltage side terminal 100 and low-voltage side power for bidirectional chopper circuit Wiring inductance 303 between semiconductor element terminals 1 Power semiconductor element terminal 1 on the low voltage side of the bidirectional chopper circuit and DC power supply Wiring inductance 304 between 7 Load resistance 305 Load inductance 400 Current path 401 when the power semiconductor element 1 on the high voltage side of the bidirectional chopper circuit is on Current after turning off the power semiconductor element 1 on the high voltage side of the bidirectional chopper circuit Path 402 Path 403 in which current change occurs due to turn-off of high-voltage power semiconductor element 1 of bidirectional chopper circuit Current path 404 Direction in which magnetic flux generated by current flowing in current path 403 counterclockwise crosses the conductor plate (from the front side of the drawing) Back side)
405 Induced current 406 generated in the conductor plate by the magnetic flux generated by the current flowing through the current path 403 Direction of the magnetic flux generated by the induced current (from the back side of the paper to the front side)
407 Path from the positive electrode terminal to the negative electrode terminal of the power storage unit 2 of the bidirectional chopper circuit in series with the element 2
Claims (13)
前記放熱器に接続された複数の導体と、
前記複数の導体のうち、少なくとも２つの導体に接続された電力貯蔵部と、
前記複数の導体のうち、少なくとも１つの導体に接続された端子と、
前記配列構造の配列方向に沿って延びた導体板と、を備え、
前記配列構造は、各々の電力用半導体素子を選択的に動作させることで前記端子と前記電力貯蔵部とを接続可能となるように構成されており、
前記導体板は、前記電力用半導体素子、および前記電力貯蔵部の前記少なくとも２つの導体とは絶縁されており、
前記導体板は、前記配列構造に近接配置されると共に、少なくとも２つの前記電力用半導体素子の少なくとも一部を覆うように設けられることを特徴とする電力変換装置。 An array structure in which a plurality of power semiconductor elements including a switching element and a radiator connected to the power semiconductor elements are arrayed,
A plurality of conductors connected to the radiator;
A power storage unit connected to at least two conductors of the plurality of conductors;
A terminal connected to at least one of the plurality of conductors;
A conductor plate extending along the arrangement direction of the arrangement structure,
The array structure is composed and said power storage unit and the terminal by selectively operating the semiconductor device for each of the power so as to be connected,
The conductor plate is insulated from the power semiconductor element and the at least two conductors of the power storage unit ,
The conductive plate, while being disposed close to said array structure, the power conversion device and which are located so as to cover part even without least of at least two of the power semiconductor device.
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