JP6181844B2 - デュアルホスト組込み共有デバイスコントローラ - Google Patents

デュアルホスト組込み共有デバイスコントローラ Download PDF

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Publication number
JP6181844B2
JP6181844B2 JP2016500857A JP2016500857A JP6181844B2 JP 6181844 B2 JP6181844 B2 JP 6181844B2 JP 2016500857 A JP2016500857 A JP 2016500857A JP 2016500857 A JP2016500857 A JP 2016500857A JP 6181844 B2 JP6181844 B2 JP 6181844B2
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processor
shared
shadow
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access
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JP2016512361A (ja
JP2016512361A5 (enExample
Inventor
アサフ・シャチャム
アミット・ジル
エレツ・ツィードン
ヤンル・リ
アゼディン・トウズニ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/463—Program control block organisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
JP2016500857A 2013-03-13 2014-03-07 デュアルホスト組込み共有デバイスコントローラ Expired - Fee Related JP6181844B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/798,803 2013-03-13
US13/798,803 US9431077B2 (en) 2013-03-13 2013-03-13 Dual host embedded shared device controller
PCT/US2014/021834 WO2014164310A1 (en) 2013-03-13 2014-03-07 Dual host embedded shared device controller

Publications (3)

Publication Number Publication Date
JP2016512361A JP2016512361A (ja) 2016-04-25
JP2016512361A5 JP2016512361A5 (enExample) 2017-01-19
JP6181844B2 true JP6181844B2 (ja) 2017-08-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016500857A Expired - Fee Related JP6181844B2 (ja) 2013-03-13 2014-03-07 デュアルホスト組込み共有デバイスコントローラ

Country Status (5)

Country Link
US (1) US9431077B2 (enExample)
EP (1) EP2972860B1 (enExample)
JP (1) JP6181844B2 (enExample)
CN (1) CN105190561B (enExample)
WO (1) WO2014164310A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE49652E1 (en) 2013-12-16 2023-09-12 Qualcomm Incorporated Power saving techniques in computing devices
WO2018038703A1 (en) * 2016-08-22 2018-03-01 Hewlett-Packard Development Company, L.P. Connected devices information
IT201700034731A1 (it) 2017-03-29 2018-09-29 St Microelectronics Srl Modulo e metodo di gestione dell'accesso ad una memoria
CN107357666B (zh) * 2017-06-26 2020-04-21 西安微电子技术研究所 一种基于硬件保护的多核并行系统处理方法
US10769092B2 (en) * 2018-12-20 2020-09-08 Dell Products, L.P. Apparatus and method for reducing latency of input/output transactions in an information handling system using no-response commands
EP3786750B1 (en) * 2019-08-30 2024-02-28 Kabushiki Kaisha Yaskawa Denki Data collection system, data collection method, and program
KR102586074B1 (ko) * 2019-09-30 2023-10-05 삼성전기주식회사 카메라 모듈
TWI716167B (zh) * 2019-10-29 2021-01-11 新唐科技股份有限公司 儲存裝置及其映射方法
US11561912B2 (en) 2020-06-01 2023-01-24 Samsung Electronics Co., Ltd. Host controller interface using multiple circular queue, and operating method thereof
US11622414B2 (en) * 2020-07-17 2023-04-04 Qualcomm Incorporated Enhanced connection release techniques for wireless communications systems
US11755518B2 (en) * 2021-06-28 2023-09-12 Dell Products L.P. Control of Thunderbolt/DisplayPort multiplexor for discrete USB-C graphics processor
CN113835757B (zh) * 2021-09-29 2023-08-15 深圳大普微电子科技有限公司 多主机共享寄存器模型的方法、装置及电子设备
CN114020659B (zh) * 2021-10-29 2025-05-06 浙江万胜智能科技股份有限公司 一种基于应用层驱动液晶显示的能源控制器系统
US20250044857A1 (en) * 2023-07-31 2025-02-06 Mediatek Inc. Fast power control mechanism for multi users
CN116991764B (zh) * 2023-08-03 2024-04-05 广州安凯微电子股份有限公司 一种高性能的Flash控制器和嵌入式系统
US20250068585A1 (en) * 2023-08-21 2025-02-27 Cirrus Logic International Semiconductor Ltd. Efficient processing on a dual core processing system

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139727A1 (en) 1983-04-15 1985-05-08 Convergent Technologies Inc. Multi-computer computer architecture
US6018785A (en) 1993-12-30 2000-01-25 Cypress Semiconductor Corp. Interrupt-generating hardware semaphore
US5854638A (en) * 1996-02-02 1998-12-29 Opti Inc. Unified memory architecture with parallel access by host and video controller
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture
US6163831A (en) 1997-11-14 2000-12-19 Lucent Technologies, Inc. Minimum refractory period in a multiple agent resource sharing environment
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6393590B1 (en) 1998-12-22 2002-05-21 Nortel Networks Limited Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system
JP2001216284A (ja) * 1999-11-25 2001-08-10 Denso Corp 電子制御装置
DE10048732A1 (de) * 2000-09-29 2002-04-18 Philips Corp Intellectual Pty Multiprozessor-Anordnung
US6874049B1 (en) 2001-02-02 2005-03-29 Cradle Technologies, Inc. Semaphores with interrupt mechanism
JP3704573B2 (ja) 2001-03-14 2005-10-12 東芝ソリューション株式会社 クラスタシステム
US7206776B2 (en) 2002-08-15 2007-04-17 Microsoft Corporation Priority differentiated subtree locking
US7979048B2 (en) 2005-09-15 2011-07-12 Silicon Laboratories Inc. Quasi non-volatile memory for use in a receiver
US7421529B2 (en) * 2005-10-20 2008-09-02 Qualcomm Incorporated Method and apparatus to clear semaphore reservation for exclusive access to shared memory
US8209527B2 (en) 2006-10-26 2012-06-26 Samsung Electronics Co., Ltd. Memory system and memory management method including the same
US7512723B2 (en) * 2006-12-29 2009-03-31 Freescale Semiconductor, Inc. Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system
US8185685B2 (en) * 2007-12-14 2012-05-22 Hitachi Global Storage Technologies Netherlands B.V. NAND flash module replacement for DRAM module
KR20090095955A (ko) 2008-03-07 2009-09-10 삼성전자주식회사 불휘발성 메모리의 공유 구조에서 다이렉트 억세스 기능을제공하는 멀티포트 반도체 메모리 장치 및 그를 채용한멀티 프로세서 시스템
JP2009277007A (ja) * 2008-05-14 2009-11-26 Mitsubishi Electric Corp 計算機装置及びプログラム
JP5241384B2 (ja) 2008-08-29 2013-07-17 ルネサスエレクトロニクス株式会社 分散共有メモリ型マルチプロセッサ及びデータ処理方法
KR20100041309A (ko) * 2008-10-14 2010-04-22 삼성전자주식회사 각 프로세서들의 어플리케이션 기능을 모두 활용 가능한 멀티 프로세서 시스템
WO2010077923A2 (en) 2008-12-16 2010-07-08 The Regents Of The University Of Michigan Computer energy conservation with a scalable psu configuration
KR20110013867A (ko) 2009-08-04 2011-02-10 삼성전자주식회사 메모리 링크 아키텍쳐에서 플래시 레스 부팅 기능을 갖는 멀티 프로세서 시스템
US8639852B2 (en) * 2009-11-13 2014-01-28 Qualcomm Incorporated Burst access protocol
JP2011232956A (ja) * 2010-04-27 2011-11-17 Clarion Co Ltd コンピュータシステムとプログラム
US8850262B2 (en) 2010-10-12 2014-09-30 International Business Machines Corporation Inter-processor failure detection and recovery
US8438416B2 (en) 2010-10-21 2013-05-07 Advanced Micro Devices, Inc. Function based dynamic power control
CA2823732A1 (en) 2011-03-25 2012-10-04 Research In Motion Limited Dynamic power management of cache memory in a multi-core processing system
US8745427B2 (en) 2011-08-10 2014-06-03 Intel Corporation Memory link power management
US9400677B2 (en) * 2013-01-02 2016-07-26 Apple Inc. Adaptive handling of priority inversions using transactions

Also Published As

Publication number Publication date
CN105190561B (zh) 2018-04-20
CN105190561A (zh) 2015-12-23
US9431077B2 (en) 2016-08-30
JP2016512361A (ja) 2016-04-25
WO2014164310A1 (en) 2014-10-09
US20140281283A1 (en) 2014-09-18
EP2972860A1 (en) 2016-01-20
EP2972860B1 (en) 2021-03-03

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