IT201700034731A1 - Modulo e metodo di gestione dell'accesso ad una memoria - Google Patents
Modulo e metodo di gestione dell'accesso ad una memoriaInfo
- Publication number
- IT201700034731A1 IT201700034731A1 IT102017000034731A IT201700034731A IT201700034731A1 IT 201700034731 A1 IT201700034731 A1 IT 201700034731A1 IT 102017000034731 A IT102017000034731 A IT 102017000034731A IT 201700034731 A IT201700034731 A IT 201700034731A IT 201700034731 A1 IT201700034731 A1 IT 201700034731A1
- Authority
- IT
- Italy
- Prior art keywords
- management
- access
- module
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1052—Security improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7207—Details relating to flash memory management management of metadata or control data
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT102017000034731A IT201700034731A1 (it) | 2017-03-29 | 2017-03-29 | Modulo e metodo di gestione dell'accesso ad una memoria |
US15/797,940 US10387334B2 (en) | 2017-03-29 | 2017-10-30 | Circuit and method for managing access to memory |
EP18163468.4A EP3382566B1 (en) | 2017-03-29 | 2018-03-22 | Module and method for managing the access to a memory |
US16/455,155 US10901919B2 (en) | 2017-03-29 | 2019-06-27 | Circuit and method for managing access to memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT102017000034731A IT201700034731A1 (it) | 2017-03-29 | 2017-03-29 | Modulo e metodo di gestione dell'accesso ad una memoria |
Publications (1)
Publication Number | Publication Date |
---|---|
IT201700034731A1 true IT201700034731A1 (it) | 2018-09-29 |
Family
ID=59521571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT102017000034731A IT201700034731A1 (it) | 2017-03-29 | 2017-03-29 | Modulo e metodo di gestione dell'accesso ad una memoria |
Country Status (3)
Country | Link |
---|---|
US (2) | US10387334B2 (it) |
EP (1) | EP3382566B1 (it) |
IT (1) | IT201700034731A1 (it) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116194904A (zh) * | 2021-03-29 | 2023-05-30 | 华为技术有限公司 | 一种闪存访问方法及装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2488516A (en) * | 2011-02-15 | 2012-09-05 | Advanced Risc Mach Ltd | Using priority dependent delays to ensure that the average delay between accesses to a memory remains below a threshold |
US20140281283A1 (en) * | 2013-03-13 | 2014-09-18 | Qualcomm Incorporated | Dual host embedded shared device controller |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100725417B1 (ko) * | 2006-02-22 | 2007-06-07 | 삼성전자주식회사 | 우선 순위에 따른 플래시 메모리의 연산 처리 장치 및 방법 |
JP5243711B2 (ja) * | 2006-11-10 | 2013-07-24 | セイコーエプソン株式会社 | プロセッサ |
JP4612710B2 (ja) * | 2008-06-02 | 2011-01-12 | 株式会社日立製作所 | トランザクション並行制御方法、データベース管理システム、およびプログラム |
US9606833B2 (en) * | 2014-04-09 | 2017-03-28 | Samsung Electronics Co., Ltd | Method and apparatus for providing a preemptive task scheduling scheme in a real time operating system |
US9575536B2 (en) * | 2014-08-22 | 2017-02-21 | Intel Corporation | Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system |
-
2017
- 2017-03-29 IT IT102017000034731A patent/IT201700034731A1/it unknown
- 2017-10-30 US US15/797,940 patent/US10387334B2/en active Active
-
2018
- 2018-03-22 EP EP18163468.4A patent/EP3382566B1/en active Active
-
2019
- 2019-06-27 US US16/455,155 patent/US10901919B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2488516A (en) * | 2011-02-15 | 2012-09-05 | Advanced Risc Mach Ltd | Using priority dependent delays to ensure that the average delay between accesses to a memory remains below a threshold |
US20140281283A1 (en) * | 2013-03-13 | 2014-09-18 | Qualcomm Incorporated | Dual host embedded shared device controller |
Also Published As
Publication number | Publication date |
---|---|
US10901919B2 (en) | 2021-01-26 |
EP3382566A1 (en) | 2018-10-03 |
US20180285284A1 (en) | 2018-10-04 |
US20190317902A1 (en) | 2019-10-17 |
EP3382566B1 (en) | 2020-03-04 |
US10387334B2 (en) | 2019-08-20 |
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