JP6170363B2 - 制御装置、コンピュータシステム、制御方法、及びプログラム - Google Patents

制御装置、コンピュータシステム、制御方法、及びプログラム Download PDF

Info

Publication number
JP6170363B2
JP6170363B2 JP2013148828A JP2013148828A JP6170363B2 JP 6170363 B2 JP6170363 B2 JP 6170363B2 JP 2013148828 A JP2013148828 A JP 2013148828A JP 2013148828 A JP2013148828 A JP 2013148828A JP 6170363 B2 JP6170363 B2 JP 6170363B2
Authority
JP
Japan
Prior art keywords
access
page
address
memory
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013148828A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015022437A5 (https=
JP2015022437A (ja
Inventor
高村　明裕
明裕 高村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2013148828A priority Critical patent/JP6170363B2/ja
Priority to US14/324,933 priority patent/US9760508B2/en
Publication of JP2015022437A publication Critical patent/JP2015022437A/ja
Publication of JP2015022437A5 publication Critical patent/JP2015022437A5/ja
Application granted granted Critical
Publication of JP6170363B2 publication Critical patent/JP6170363B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2013148828A 2013-07-17 2013-07-17 制御装置、コンピュータシステム、制御方法、及びプログラム Active JP6170363B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013148828A JP6170363B2 (ja) 2013-07-17 2013-07-17 制御装置、コンピュータシステム、制御方法、及びプログラム
US14/324,933 US9760508B2 (en) 2013-07-17 2014-07-07 Control apparatus, computer system, control method and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013148828A JP6170363B2 (ja) 2013-07-17 2013-07-17 制御装置、コンピュータシステム、制御方法、及びプログラム

Publications (3)

Publication Number Publication Date
JP2015022437A JP2015022437A (ja) 2015-02-02
JP2015022437A5 JP2015022437A5 (https=) 2016-08-18
JP6170363B2 true JP6170363B2 (ja) 2017-07-26

Family

ID=52344550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013148828A Active JP6170363B2 (ja) 2013-07-17 2013-07-17 制御装置、コンピュータシステム、制御方法、及びプログラム

Country Status (2)

Country Link
US (1) US9760508B2 (https=)
JP (1) JP6170363B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018205859A (ja) * 2017-05-31 2018-12-27 キヤノン株式会社 メモリコントローラとその制御方法
US12112786B2 (en) * 2021-09-01 2024-10-08 Micron Technology, Inc. Command scheduling component for memory

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128716A (en) * 1998-01-23 2000-10-03 Motorola Inc. Memory controller with continuous page mode and method therefor
JP2000331476A (ja) 1999-05-20 2000-11-30 Nec Ibaraki Ltd ページ一致制御回路およびページ一致制御方法
US6381672B1 (en) * 2000-05-11 2002-04-30 Advanced Micro Devices, Inc. Speculative opening of a new page when approaching page boundary during read/write of isochronous streams
JP4370063B2 (ja) * 2001-06-27 2009-11-25 富士通マイクロエレクトロニクス株式会社 半導体記憶装置の制御装置および半導体記憶装置の制御方法
JP2004013618A (ja) * 2002-06-07 2004-01-15 Renesas Technology Corp 同期型半導体記憶装置のアクセス制御装置
US7386658B2 (en) * 2004-03-15 2008-06-10 Intel Corporation Memory post-write page closing apparatus and method
JP2006127110A (ja) * 2004-10-28 2006-05-18 Canon Inc Ｄｒａｍメモリアクセス制御手法、および手段
US20110055495A1 (en) * 2009-08-28 2011-03-03 Qualcomm Incorporated Memory Controller Page Management Devices, Systems, and Methods
JP5759276B2 (ja) 2011-06-09 2015-08-05 キヤノン株式会社 処理装置及び情報処理方法
US9336164B2 (en) * 2012-10-04 2016-05-10 Applied Micro Circuits Corporation Scheduling memory banks based on memory access patterns
US9251048B2 (en) * 2012-10-19 2016-02-02 International Business Machines Corporation Memory page management
JP2014115851A (ja) 2012-12-10 2014-06-26 Canon Inc データ処理装置及びその制御方法

Also Published As

Publication number Publication date
US20150026375A1 (en) 2015-01-22
US9760508B2 (en) 2017-09-12
JP2015022437A (ja) 2015-02-02

Similar Documents

Publication Publication Date Title
US20180275921A1 (en) Storage device
CN108139994B (zh) 内存访问方法及内存控制器
CN104850501B (zh) 一种ddr存储器访存地址映射方法及访存地址映射单元
US8954644B2 (en) Apparatus and method for controlling memory
CN103915119A (zh) 数据储存装置以及快闪存储器控制方法
JP3819004B2 (ja) メモリ制御装置
US9772957B2 (en) Processor and method for accessing memory
US20140344512A1 (en) Data Processing Apparatus and Memory Apparatus
JP2014154119A (ja) メモリ制御装置及び半導体記憶装置
JP6170363B2 (ja) 制御装置、コンピュータシステム、制御方法、及びプログラム
JP5801158B2 (ja) Ｒａｍ記憶装置
KR100607987B1 (ko) 명령어 스케줄링을 수행하는 메모리 제어장치 및 방법
JP2019185447A (ja) メモリコントローラ、画像処理装置及びデータ転送方法
JP6226200B2 (ja) メモリーコントローラー
US8966166B2 (en) Information processing apparatus and information processing method
US20060195665A1 (en) Access control device, method for changing memory addresses, and memory system
US8452920B1 (en) System and method for controlling a dynamic random access memory
JP2004127305A (ja) メモリ制御装置
JP4071930B2 (ja) シンクロナスｄｒａｍ
CN112835513A (zh) 控制数据读写装置与方法
US9235504B2 (en) Prioritizing read-command issuance in a data storage apparatus
JP2007172129A (ja) 不揮発性メモリアクセス制御装置および不揮発性メモリ制御システム
US20130286762A1 (en) Memory control apparatus and method
JPH09237490A (ja) メモリ制御方法
JP2000099391A (ja) プリンタ装置およびプリンタ制御方法、並びに記録媒体

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160704

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160704

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170316

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170321

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170508

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170602

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170630

R151 Written notification of patent or utility model registration

Ref document number: 6170363

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151