JP5801158B2 - Ram記憶装置 - Google Patents
Ram記憶装置 Download PDFInfo
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- JP5801158B2 JP5801158B2 JP2011231550A JP2011231550A JP5801158B2 JP 5801158 B2 JP5801158 B2 JP 5801158B2 JP 2011231550 A JP2011231550 A JP 2011231550A JP 2011231550 A JP2011231550 A JP 2011231550A JP 5801158 B2 JP5801158 B2 JP 5801158B2
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- ram
- access
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- data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
- Debugging And Monitoring (AREA)
Description
11 シングルポートRAM
12 CPU側IF
13 RAM制御信号記憶部
14 マルチプレクサ(選択部)
15 フラッシュ側IF
20 ホストインターフェース
30 フラッシュインターフェース
40 CPU
50 ECC
60 内部バス
100 メモリ制御装置(フラッシュコントローラ)
200 ホスト装置
300 半導体記憶装置(フラッシュメモリ)
Claims (5)
- 書込み又は読出しの第1制御信号と第1情報データとを含む第1アクセスを中継する第1インターフェースと、書込み又は読出しの第2制御信号と第2情報データとを含む第2アクセスを中継する第2インターフェースと、前記第1アクセス及び前記第2アクセスに応じてクロック信号に同期して前記第1情報データ及び前記第2情報データの書込み又は読出しを行なうRAMと、を含むRAM記憶装置であって、
前記第1インターフェースからの待機指令信号に応じて、前記第2インターフェースに到来した前記第2アクセスを記憶する記憶動作をなす記憶部と、
前記第1制御信号に応じて、前記クロック信号による1のサイクル内において前記第1インターフェースに到来した前記第1アクセスを前記RAMに供給し、前記第2制御信号に応じて、前記1のサイクルに続く次のサイクル以降において前記記憶部に記憶されている前記第2アクセスを前記RAMに供給する選択供給動作をなす選択部と、
を含むことを特徴とするRAM記憶装置。 - 前記第1及び第2制御信号の各々は、選択指令信号と前記待機指令信号とを含み、
前記選択部は前記選択指令信号に応じて前記選択供給動作をなし、前記記憶部は前記待機指令信号に応じて前記記憶動作をなすことを特徴とする請求項1に記載のRAM記憶装置。 - 前記RAMは、シングルポートRAMであることを特徴とする請求項1又は2に記載のRAM記憶装置。
- 前記第1及び第2情報データの各々は、フラッシュメモリのページアドレスと前記フラッシュメモリの記憶データについてのエラー情報とを含むことを特徴とする請求項1乃至3のいずれか1つに記載のRAM記憶装置。
- 半導体記憶装置を制御するメモリ制御装置に含まれ、
前記第1アクセス及び前記第2アクセスは、前記半導体記憶装置の制御に関連して前記メモリ制御装置から供給されたものであることを特徴とする請求項1乃至4のいずれか1つに記載のRAM記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011231550A JP5801158B2 (ja) | 2011-10-21 | 2011-10-21 | Ram記憶装置 |
US13/653,141 US9256556B2 (en) | 2011-10-21 | 2012-10-16 | RAM memory device capable of simultaneously accepting multiple accesses |
CN201210399530.9A CN103064802B (zh) | 2011-10-21 | 2012-10-19 | Ram存储装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011231550A JP5801158B2 (ja) | 2011-10-21 | 2011-10-21 | Ram記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013089161A JP2013089161A (ja) | 2013-05-13 |
JP5801158B2 true JP5801158B2 (ja) | 2015-10-28 |
Family
ID=48107433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011231550A Active JP5801158B2 (ja) | 2011-10-21 | 2011-10-21 | Ram記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9256556B2 (ja) |
JP (1) | JP5801158B2 (ja) |
CN (1) | CN103064802B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150103593A1 (en) * | 2013-10-14 | 2015-04-16 | Skymedi Corporation | Method of Writing Data in Non-Volatile Memory and Non-Volatile Storage Device Using the Same |
US9612904B2 (en) * | 2015-02-02 | 2017-04-04 | Sandisk Technologies Llc | Memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode |
CN104716954A (zh) * | 2015-03-17 | 2015-06-17 | 广东高云半导体科技股份有限公司 | 带有片上用户非易失性存储器的可编程逻辑器件 |
CN106528464A (zh) * | 2016-11-08 | 2017-03-22 | 英业达科技有限公司 | 内存访问冲突控制的计算机系统 |
CN115485673A (zh) * | 2020-08-03 | 2022-12-16 | Oppo广东移动通信有限公司 | 共享内存处理装置、调制解调器以及方法和存储介质 |
Family Cites Families (27)
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JPH0574151A (ja) | 1991-09-18 | 1993-03-26 | Hitachi Ltd | ダイナミツクメモリの競合回路 |
US5448714A (en) * | 1992-01-02 | 1995-09-05 | Integrated Device Technology, Inc. | Sequential-access and random-access dual-port memory buffer |
JPH06161870A (ja) * | 1992-11-26 | 1994-06-10 | Nec Corp | デュアルポートram回路 |
JPH0877066A (ja) | 1994-08-31 | 1996-03-22 | Tdk Corp | フラッシュメモリコントローラ |
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JP2006185352A (ja) * | 2004-12-28 | 2006-07-13 | Fujitsu Ltd | 外部記憶制御装置およびそのためのプログラム |
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JP2006276967A (ja) * | 2005-03-28 | 2006-10-12 | Renesas Technology Corp | 半導体装置 |
KR100648292B1 (ko) * | 2005-07-28 | 2006-11-23 | 삼성전자주식회사 | 오토 듀얼 버퍼링 방식의 메모리 장치 |
JP4153535B2 (ja) * | 2006-05-30 | 2008-09-24 | Tdk株式会社 | メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びに、フラッシュメモリの制御方法 |
JP4823009B2 (ja) * | 2006-09-29 | 2011-11-24 | 株式会社東芝 | メモリカード及びホスト機器 |
KR100909364B1 (ko) * | 2007-02-06 | 2009-07-24 | 삼성전자주식회사 | 시스템 클록의 노출을 차단하는 메모리 컨트롤러와 그 방법 |
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-
2011
- 2011-10-21 JP JP2011231550A patent/JP5801158B2/ja active Active
-
2012
- 2012-10-16 US US13/653,141 patent/US9256556B2/en not_active Expired - Fee Related
- 2012-10-19 CN CN201210399530.9A patent/CN103064802B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN103064802B (zh) | 2018-09-07 |
JP2013089161A (ja) | 2013-05-13 |
US9256556B2 (en) | 2016-02-09 |
US20130104004A1 (en) | 2013-04-25 |
CN103064802A (zh) | 2013-04-24 |
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