JP6131781B2 - THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, AND LIQUID CRYSTAL DISPLAY DEVICE - Google Patents

Description

  The present invention relates to a thin film transistor including an oxide semiconductor layer and a manufacturing method thereof. The present invention also relates to a liquid crystal display device using the thin film transistor.

  In recent years, a thin film transistor using an InGaZnO-based oxide semiconductor for a channel layer has been actively developed. An oxide semiconductor has higher mobility than amorphous silicon and can be formed at a lower temperature. Therefore, the oxide semiconductor is formed over a glass substrate and used as a pixel transistor of a display device.

  Thin film transistors can operate at higher speeds as the mobility becomes higher, and therefore, developments aiming at higher mobility are being carried out. Patent Document 1 discloses a thin film transistor which realizes a well-type potential structure using an InGaZnO system as an oxide semiconductor layer and achieves high mobility using two-dimensional electrons.

JP 2011-124360 A

  However, in a thin film transistor having a well-type potential structure in a semiconductor layer as in Patent Document 1, a current between a source and a drain flows through a well layer, but most of the current is taken out as a current by a source electrode and a drain electrode as a barrier layer. Via. This is because the contact area between the end face of the well layer and the source and drain electrodes is much smaller than the contact area between the upper barrier layer and the source and drain electrodes, and most of the current is extracted via the upper barrier layer. . Therefore, the characteristics of the thin film transistor are easily affected by the resistance component, defect level, and surface level of the barrier layer, and there are problems such as unstable operation.

  The present invention has been made to solve the above-described problems, and provides a thin film transistor, a manufacturing method thereof, and a liquid crystal display device in which the influence of the resistance component, defect level, and surface level of the barrier layer is reduced. It is intended to do.

A thin film transistor according to the present invention includes a gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, a first barrier layer, a well layer, and a second layer on the gate electrode via the gate insulating film. A thin film transistor including a well-type potential-structure oxide semiconductor layer formed by stacking a plurality of barrier layers in order, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first barrier Of the layers, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer , and the well layer has a region that is not covered with the second barrier layer in a top view. The source electrode or the drain electrode is formed in contact with a region of the upper surface of the well layer that is not covered with the second barrier layer, and has a gap between the second barrier layer and the well electrode . .

According to another aspect of the thin film transistor of the present invention, the gate electrode formed on the substrate, the gate insulating film formed on the gate electrode, and the first insulating film on the gate electrode via the gate insulating film A thin film transistor including an oxide semiconductor layer having a well-type potential structure in which a barrier layer, a well layer, and a second barrier layer are stacked in this order, and a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer In the first barrier layer, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer, and the well layer is the second barrier layer in a top view. The source electrode or the drain electrode has an uncovered region, and is formed in contact with a region of the upper surface of the well layer that is not covered with the second barrier layer, and is provided with an etching stopper on the second barrier layer. Further comprising a thin film transistor.
Furthermore, according to another aspect of the thin film transistor according to the present invention, the gate electrode formed on the substrate, the gate insulating film formed on the gate electrode, and the first insulating film on the gate electrode via the gate insulating film. A thin film transistor including an oxide semiconductor layer having a well-type potential structure in which a barrier layer, a well layer, and a second barrier layer are stacked in this order, and a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer In the first barrier layer, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer, and the well layer is the second barrier layer in a top view. The source electrode or the drain electrode is formed in contact with a region not covered with the second barrier layer on the upper surface of the well layer and between the second barrier layer. Have voids, Further comprising an etching stopper layer on the second barrier layer, a thin film transistor.

  Since the thin film transistor according to the present invention is configured as described above, it is possible to increase the number of carriers injected and extracted without passing through the barrier layer. As a result, the influence of the resistance component, defect level, and surface level of the barrier layer on the carriers is suppressed, and a thin film transistor with high mobility and stable operation can be obtained.

1 is a top view of a thin film transistor according to a first embodiment of the present invention. It is sectional drawing in the II-II line | wire in FIG. It is a schematic diagram which shows the manufacturing process of the thin-film transistor which concerns on Embodiment 1 of this invention. It is a figure which shows the relationship between the pressure at the time of film-forming of an InGaZnO type oxide semiconductor layer, and Ga composition. It is a figure which shows the relationship between the discharge power at the time of film-forming of an InGaZnO type oxide semiconductor layer, and Ga composition. It is a schematic diagram which shows the band gap of the semiconductor layer of the thin-film transistor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the thin-film transistor which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the structure of the thin-film transistor which concerns on Embodiment 3 of this invention. It is a schematic diagram which shows the manufacturing process of the thin-film transistor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 3 of this invention. It is a top view which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 3 of this invention. It is sectional drawing in the XIII-XIII line | wire in FIG. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the thin-film transistor which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the structure of the thin-film transistor which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 5 of this invention. It is a schematic diagram which shows the manufacturing process of the thin-film transistor which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the modification of the thin-film transistor which concerns on Embodiment 5 of this invention. It is a schematic diagram which shows the manufacturing process of the thin-film transistor which concerns on Embodiment 6 of this invention. It is a top view of the pixel part of the liquid crystal display device which concerns on Embodiment 7 of this invention. It is sectional drawing in the XXIII-XXIII line | wire in FIG. It is a circuit diagram of the pixel of the liquid crystal display device which concerns on Embodiment 7 of this invention.

<Embodiment 1>
First, the structure of the thin film transistor according to the first embodiment of the present invention will be described with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. The drawings are schematic and do not reflect the exact size of the components shown. In addition, the dimensions, materials, shapes, and relative arrangements of the components exemplified in the embodiments of the present invention are appropriately changed depending on the configuration of the apparatus to which the present invention is applied and various conditions. The present invention is not limited to these examples.

  FIG. 1 is a top view of a thin film transistor 100 according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the thin film transistor 100 taken along line II-II in FIG. As shown in the figure, the thin film transistor 100 includes a substrate 8, a gate electrode 1, an insulating layer 2, a semiconductor layer 9, a source electrode 6, and a drain electrode 7. In FIG. 1, the insulating layer 2 is seen through. In addition, a portion of the gate electrode 1 covered with the source and drain electrodes 6 and 7 is indicated by a broken imaginary line.

  The substrate 8 may be of any material and structure as long as the surface is insulative, such as an insulating material or an insulating thin film formed on a conductive substrate. On the substrate 8, a gate electrode 1, an insulating layer 2, a semiconductor layer 9, a source electrode 6, and a drain electrode 7 are formed.

  The gate electrode 1 is formed of a conductive material on the upper surface of the substrate 8. The gate electrode 1 is covered with an insulating layer 2. The insulating layer 2 is also called a gate insulating film.

  The semiconductor layer 9 includes a first semiconductor layer 3, a second semiconductor layer 5, and a third semiconductor layer 4. The semiconductor layer 9 is formed by laminating the first semiconductor layer 3, the third semiconductor layer 4, and the second semiconductor layer 5 in this order on the gate electrode 1 with the insulating layer 2 interposed therebetween. The third semiconductor layer 4 is sandwiched between the first semiconductor layer 3 and the second semiconductor layer 5 and has a narrower band gap than the first and second semiconductor layers 3 and 5. Therefore, the semiconductor layer 9 forms a well-type potential. That is, the first semiconductor layer 3 is a barrier layer (also referred to as a first barrier layer), the third semiconductor layer 4 is a well layer (potential well layer), and the second semiconductor layer 5 is a barrier layer (second barrier layer). Also referred to as a layer). The first semiconductor layer 3 is also referred to as a lower barrier layer because it is formed below the well layer. The second semiconductor layer 5 is also called an upper barrier layer because it is formed on the well layer.

  The semiconductor layer 9 is formed of an InGaZnO-based oxide semiconductor. In order to realize the potential well of the semiconductor layer 9 with an InGaZnO-based oxide semiconductor having a three-layer structure, the Ga composition of the first and second semiconductor layers 3 and 5 is compared with the Ga composition of the third semiconductor layer 4. You should try to increase as much as possible.

  Further, the semiconductor layer 9 is configured such that the film thickness of the third semiconductor layer 4 is larger than the film thicknesses of the first and second semiconductor layers 3 and 5. That is, the third semiconductor layer 4 which is a well layer among the layers constituting the semiconductor layer 9 is the thickest. For example, the thickness of the first semiconductor layer 3 is 0.1 μm, the thickness of the third semiconductor layer 4 is 0.3 μm, and the thickness of the second semiconductor layer 5 is 0.1 μm.

  The source electrode 6 and the drain electrode 7 are formed of a conductive material, and end surfaces (side surfaces) 3 a and 4 a of the first semiconductor layer 3, the second semiconductor layer 5, and the third semiconductor layer 4 constituting the semiconductor layer 9. , 5a and is electrically connected. That is, the source electrode 6 and the drain electrode 7 are continuous from the upper end portion of the end surface 5a of the second semiconductor layer 5 that is the upper barrier layer to the lower end portion of the end surface 3a of the first semiconductor layer 3 that is the lower barrier layer. And are formed so as to contact each other. In FIG. 2, the entire upper surface of the second semiconductor layer 5 is exposed, and the source electrode 6 and the drain electrode 7 are not in contact with the upper surface 5 b of the second semiconductor layer 5.

  When the shape of the semiconductor layer 9 in FIG. 2 in the depth direction on the paper is the same, the contact area between each layer constituting the semiconductor layer 9 and the source electrode 6 and the drain electrode 7 is the largest thickness of the third semiconductor layer 4. Therefore, the maximum value is obtained in the third semiconductor layer 4.

  Next, a method for manufacturing the thin film transistor 100 according to the first embodiment of the present invention will be described. 3A to 3F are schematic views schematically showing a manufacturing flow of the thin film transistor 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 3A, a patterned gate electrode 1 and an insulating layer 2 covering the gate electrode 1 are formed on a glass substrate 8. Further, the first semiconductor layer 3, the third semiconductor layer 4, and the second semiconductor layer 5 are formed by sputtering. The semiconductor layer 9 including the first semiconductor layer 3, the second semiconductor layer 5, and the third semiconductor layer 4 is formed by continuously forming an InGaZnO-based oxide semiconductor layer. At this time, the first and second semiconductor layers 3 and 5 that are barrier layers are formed to have a Ga-rich composition as compared with the third semiconductor layer 4 that is a well layer. For example, the Ga ratio of the first and second semiconductor layers 3 and 5 that are barrier layers is 7%, and the Ga ratio of the third semiconductor layer 4 that is a well layer is 5%. In this way, a well-type potential in which the band gap of the first and second semiconductor layers 3 and 5 is wider than the band gap of the third semiconductor layer 4 can be formed.

  Here, the relationship between the Ga ratio of the InGaZnO-based oxide semiconductor layer and the parameters during film formation will be described. FIG. 4 shows the experimental results showing the relationship between the pressure and the Ga ratio when forming the InGaZnO-based oxide semiconductor layer. FIG. 5 shows the experimental results showing the relationship between the discharge power and the Ga ratio when forming the InGaZnO-based oxide semiconductor layer. From the figure, it can be seen that the Ga ratio increases by increasing the deposition pressure or increasing the discharge power. That is, a Ga-rich composition film can be formed by changing parameters such as pressure and discharge power during film formation. In this manner, in the InGaZnO-based oxide semiconductor layer, the composition can be changed by changing the conditions during film formation. Therefore, the three oxide semiconductor layers constituting the semiconductor layer 9 are continuously formed. It can be realized in the process.

  Next, as shown in FIG. 3B, the first semiconductor layer 3, the third semiconductor layer 4, and the second semiconductor layer 5 are formed using the resist 80 formed above the gate electrode 1 as a mask. The oxide semiconductor layer is patterned. Patterning is performed by dry etching. By patterning, the end surfaces of the first semiconductor layer 3, the third semiconductor layer 4, and the second semiconductor layer 5 are formed.

  Thereafter, as shown in FIG. 3C, the resist is removed, and a metal film 81 serving as an electrode is formed on the entire surface of the substrate by sputtering or the like. The metal film 81 is in contact with the end surface and the upper surface of the semiconductor layer 9. The metal film 81 serving as an electrode may be formed using Ti, Mo, ITO, or the like.

  Next, as shown in FIGS. 3D and 3E, the metal film 81 on the semiconductor layer 9 is etched by photolithography using a resist 82 to form the source electrode 6 and the gate electrode 7.

  Finally, as shown in FIG. 3F, the resist 82 is removed. Through the above steps, a thin film transistor in which the source electrode 6 and the gate electrode 7 are in contact with the end surfaces of the first semiconductor layer 3, the third semiconductor layer 4, and the second semiconductor layer 5 can be manufactured.

  The operation of the thin film transistor 100 having the above structure will be described with reference to the drawings. FIG. 6 is a schematic diagram showing an energy band structure in an equilibrium state of the semiconductor layer 9 having a three-layer structure. FIG. 6 shows an energy state in a cross section from the gate electrode 1 upward (Z direction shown in FIG. 2) at a position between the source and the drain electrode 7. The horizontal direction coincides with the Z direction in FIG. 2 and shows the stacked layers. The vertical direction indicates energy. In the figure, Ec represents the lower end of the conduction band, and Ev represents the upper end of the valence band. Eg is a band gap which is a difference between Ec and Ev. The band gap Eg of the third semiconductor layer 4 that is the well layer is smaller than the band gap Eg of the first and second semiconductor layers 3 and 5 that are the barrier layers.

  The current between the source and drain electrodes 6 and 7 of the thin film transistor 100 is a flow of electrons existing on the conduction band Ec in the direction perpendicular to the paper surface of FIG. Since electrons always try to move in a direction where energy is low, in the band structure shown in FIG. 6, the electrons gather in the third semiconductor layer 4 having a narrow band gap Eg. When a bias is applied between the source and drain electrodes 6 and 7 in such a state, an energy gradient is generated in the direction perpendicular to the paper surface. Hereinafter, as an example, a case where 5 V is applied to the drain electrode 7 and the source electrode 6 is set to the ground potential will be described. When a bias is applied between the source and drain electrodes 6 and 7, electrons move toward the drain electrode 7 having low energy, and a current flows between the source and drain electrodes 6 and 7. In the configuration in which the semiconductor layer 9 employs the well-type potential structure as in the present application, the number of electrons in the narrow band gap region is larger than that in the wide band gap region. The movement of electrons in the third semiconductor layer 4 becomes the main current between the source and drain electrodes 6 and 7.

Next, electrons injected into the third semiconductor layer 4 having a narrow band gap will be described.
When a positive bias is applied to the gate electrode 1, mainly three types of electrons shown in the following (A1) to (A3) are injected into the third semiconductor layer 4 which is a well layer.
(A1) Electrons present in the valence band of the second semiconductor layer 5 from the beginning (A2) Electrons flowing into the valence band of the second semiconductor layer 5 via the source electrode 6 and the drain electrode 7 (A3) Electrons directly injected into the valence band of the third semiconductor layer 4 from the source electrode 6 and the drain electrode 7 Note that the electrons present in the first semiconductor layer 3 from the beginning are positive bias applied to the gate electrode 1. Therefore, the electrons injected from the first semiconductor layer 3 into the third semiconductor layer 4 are only due to diffusion. Therefore, the influence of the first semiconductor layer 3 on the electrons injected into the third semiconductor layer 4 is minimal.

  Among the above three types of electrons, the electrons injected into the third semiconductor layer 4 that is the well layer via the second semiconductor layer 5 as in (A1) and (A2) are the second semiconductor. It is strongly influenced by the film quality of the layer 5. Specifically, when passing through the second semiconductor layer 5, some electrons are trapped in the defect level, surface level, or the like of the second semiconductor layer 5, or the resistance of the second semiconductor layer 5. It may be affected by ingredients. As a result, electrons injected into the third semiconductor layer 4 are reduced. Therefore, for example, even if the contact areas of the source electrode 6 and the drain electrode 7 in the second semiconductor layer 5 and the third semiconductor layer 4 are the same, the third semiconductor according to (A2) and (A3) above. The amount of electrons injected into the layer 4 is not equal, and (A3) is larger.

  Here, in the first embodiment, the source electrode 6 and the drain electrode are in contact with the end face of the semiconductor layer 9, and the thickness of the third semiconductor layer 4 that is a well layer is the second semiconductor layer 5 that is a barrier layer. Greater than the film thickness. That is, the contact area between the third semiconductor layer 4 and the source electrode 6 and the drain electrode 7 is larger than the contact area between the second semiconductor layer 5 and the source electrode 6 and the drain electrode 7.

  Therefore, the electrons (hereinafter also referred to as carriers) injected into the third semiconductor layer 4 when a positive bias is applied to the gate electrode 1 are dominated by (A3) among the above (A1) to (A3). It becomes. In this way, by directly and most often injecting electrons into the third semiconductor layer 4 which is the main current between the source and drain electrodes 6, 7, the influence of the electrons from the second semiconductor layer 5 is reduced. Electrons can be efficiently injected into the well layer.

  The electrons injected into the third semiconductor layer 4 which is a well layer tend to move to the gate electrode 1 side by the positive bias of the gate electrode 1. However, since the band gap of the first semiconductor layer 3 is large and becomes a potential barrier, electrons are confined in the third semiconductor layer 4. The trapped electrons are two-dimensionally highly mobile. Therefore, high performance of the thin film transistor can be achieved by using the high mobility electrons. When the source electrode 6 is grounded while electrons are confined in the third semiconductor layer 4 and a positive bias is applied to the drain electrode 7, a current flows between the source and drain electrodes 6 and 7. Also in this case, electrons directly taken out from the third semiconductor layer 4 by the source electrode 6 and the drain electrode 7 become dominant. For this reason, electrons are not affected by film characteristics such as defect levels of the second semiconductor layer 5 as in the case of taking out via the second semiconductor layer 5, and further between the source and drain electrodes 6, 7. The resistance can be reduced.

  Next, the effect of electron injection into the semiconductor layer 9 in the first embodiment will be estimated. 2, it is assumed that the shape of the thin film transistor 100 in the depth direction of the paper surface is uniform, and the length of the contact portion between the semiconductor layer 9 and the source electrode 6 and drain electrode 7 in the depth direction of the paper surface is W (illustrated in FIG. 1). ). Further, the thickness of the first semiconductor layer 3 is 0.1 μm, the thickness of the third semiconductor layer 4 is 0.3 μm, and the second semiconductor layer 5 is 0.1 μm. At this time, the area S1 of the contact portion between the first semiconductor layer 3 which is the lower barrier layer and the source electrode 6 and the drain electrode 7, the second semiconductor layer 4 which is the upper barrier layer, the source electrode 6 and the drain electrode 7, The area S2 of the contact portion and the area S3 of the contact portion between the third semiconductor layer 5 which is a well layer and the source electrode 6 and the drain electrode 7 are expressed by the following Equation 1, respectively.

  The number of electrons injected from the source electrode 6 and the drain electrode 7 into the semiconductor layer 9 increases as the contact area between the source electrode 6 and the drain electrode 7 and the semiconductor layer 9 increases. Therefore, as in the first embodiment, by configuring the third semiconductor layer 4 so that the contact area between the source electrode 6 and the drain electrode 7 is maximized, the main current between the source, drain 6 and 7 can be increased. Thus, electrons can be efficiently injected into the well layer without passing through the barrier layer.

  In the first embodiment, a uniform electrode layout in the depth direction in FIG. 2 is assumed. However, in the first embodiment, it is essential that the contact area between the third semiconductor layer 4 which is a well layer and the source electrode 6 and the drain electrode 7 is maximized, and the electrode is not necessarily uniform in the depth direction. It doesn't have to be a layout.

  In the first embodiment, the source electrode 6 and the drain electrode 7 are assumed to have the same shape, and the first semiconductor layer 3, the second semiconductor layer 5, and the third semiconductor layer 4 are The configuration in which the contact area between the third semiconductor layer 4 and the source electrode 6 and the drain electrode 7 is maximized has been described. However, the source electrode 6 and the drain electrode 7 do not necessarily have the same shape, and even when the contact area of either the source electrode 6 or the drain electrode 7 is maximized, it is compared with the conventional case. Thus, electrons can be efficiently injected into the third semiconductor layer 4. That is, if the contact area of the source electrode 6 or the drain electrode 7 is maximized, electrons can be efficiently injected into the third semiconductor layer 4 as compared with the conventional case.

Further, in the first embodiment, a configuration has been described which is not in contact with the upper surface 5b of the second semiconductor layer 5 source electrode 6 and drain electrode 7 is the upper barrier layer. However, as in the thin film transistor 101 illustrated in FIG. 7, the source electrode 106 and the drain electrode 107 may be in contact with the upper surface 5 b as well as the end surface of the second semiconductor layer 5. In this case, the sum of the film thickness of the second semiconductor layer 5 and the contact width H in which the source electrode 106 or the drain electrode 107 is in contact with the upper surface 5b of the second semiconductor layer 5 is the third semiconductor. It is necessary to be less than the film thickness of the layer 4. That is, the contact area between the end face of the third semiconductor layer 4 and the source electrode 106 and the drain electrode 107 is larger than the contact area between the first and second semiconductor layers 3 and 5 and the source electrode 106 and the drain electrode 107. There is a need.

  Specifically, when the contact area between the end surface of the semiconductor layer 9 and the source electrode 106 and the drain electrode 107 is several 1, the width H of the source electrode 106 and the drain electrode 107 covering the upper surface 5b of the second semiconductor layer 5 is If it is less than 0.2 μm, the contact area between the source electrode 106 and the drain electrode 107 is maximized in the third semiconductor layer 4.

  In the first embodiment, a well-type potential having a three-layer structure has been described. However, four or more layers may be used.

  As described above, the first embodiment of the present invention includes the gate electrode 1 formed on the substrate 8, the gate insulating film 2 formed on the gate electrode 1, and the gate insulating film 2 on the gate electrode 1. A well type in which a first semiconductor layer 3 as a first barrier layer, a third semiconductor layer 4 as a well layer, and a second semiconductor layer 5 as a second barrier layer are stacked in this order. A thin film transistor including an oxide semiconductor layer 9 having a potential structure, and a source electrode 6 and a drain electrode 7 electrically connected to the oxide semiconductor layer 9, the first semiconductor layer 3 being a first barrier layer Of the third semiconductor layer 4 that is the well layer and the second semiconductor layer 5 that is the second barrier layer, the contact area with the source electrode 6 or the drain electrode 7 in the third semiconductor layer 4 that is the well layer Is maximized.

With this configuration, when a current between the source and the drain is taken out, the number of carriers (electrons) that move through the barrier layer decreases, and the number of carriers (electrons) that move without passing through the barrier layer increases. As a result, a thin film transistor having stable characteristics can be obtained in which the influence on carriers due to defects in the barrier layer, interface states, surface states, and the like is reduced.

  Further, in the thin film transistor of Embodiment 1 of the present invention, the semiconductor layer 9 is formed using an InGaZnO-based oxide semiconductor whose Ga composition can be controlled by the pressure at the time of film formation, discharge power, or the like. Therefore, by changing the film formation conditions, a potential well structure in which layers having different band gaps are stacked can be easily formed. In addition, since layers having different band gaps can be continuously formed while changing the Ga composition, the semiconductor layer 9 having good interface characteristics can be formed.

<Embodiment 2>
In Embodiment 1, a bottom-gate thin film transistor has been described. However, the present invention can also be applied to a top-gate thin film transistor. The thin film transistor of Embodiment 2 of the present invention has a top gate structure, and the arrangement position of the electrode with respect to the semiconductor layer is mainly different from the thin film transistor shown in Embodiment 1. Since the configuration other than this is the same as that of the first embodiment described above, the same reference numerals are assigned to the same elements, and the description thereof is not repeated. In addition, since the operation of the second embodiment is the same as that of the above-described first embodiment, the second embodiment described below also has the same effect as the first embodiment. Hereinafter, the structure of the thin film transistor according to the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 is a cross-sectional view of the thin film transistor 102 according to the second embodiment of the present invention. As shown in the figure, the thin film transistor 102 includes a substrate 8, a semiconductor layer 19, a source electrode 16, a drain electrode 17, an insulating layer 12, a gate electrode 11, a source extraction electrode 18a, and a drain extraction electrode 18b.

  A semiconductor layer 19, a source electrode 16, a drain electrode 17, an insulating layer 12, and a gate electrode 11 are formed on the insulating substrate 8.

  The semiconductor layer 19 includes a first semiconductor layer 13, a second semiconductor layer 15, and a third semiconductor layer 14. The semiconductor layer 19 is formed by laminating the first semiconductor layer 13, the third semiconductor layer 14, and the second semiconductor layer 15 in this order on the upper surface of the substrate 8. The third semiconductor layer 14 is sandwiched between the first semiconductor layer 13 and the second semiconductor layer 15 and has a narrower band gap than the first and second semiconductor layers 13 and 15. Therefore, the semiconductor layer 19 forms a well-type potential. That is, the first and second semiconductor layers 13 and 15 are barrier layers, and the third semiconductor layer 14 is a well layer.

  The semiconductor layer 19 is formed of an InGaZnO-based oxide semiconductor. In order to realize the potential well of the semiconductor layer 19 with an InGaZnO-based oxide semiconductor having a three-layer structure, the Ga composition of the first and second semiconductor layers 13 and 15 is compared with the Ga composition of the third semiconductor layer 14. You should try to increase as much as possible.

  In addition, the semiconductor layer 19 is configured such that the thickness of the third semiconductor layer 14 is larger than the thickness of the first and second semiconductor layers 13 and 15. That is, the third semiconductor layer 14 which is a well layer among the layers constituting the semiconductor layer 19 is the thickest.

  The source electrode 16 and the drain electrode 17 are formed of a conductive material and are formed on the upper surface of the substrate 8. The source electrode 16 and the drain electrode 17 are in contact with end faces (side surfaces) 13 a, 14 a, 15 a of the first semiconductor layer 13, the second semiconductor layer 15, and the third semiconductor layer 14 constituting the semiconductor layer 19. Are electrically connected. In FIG. 8, the source electrode 16 and the drain electrode 17 are not in contact with the upper surface 15 b of the second semiconductor layer 15.

  The semiconductor layer 19, the source electrode 16 and the drain electrode 17 are covered with the insulating layer 12. Further, the insulating layer 12 on the source electrode 16 and the drain electrode 17 is provided with a through hole, and in the through hole, a source lead electrode 18 a electrically connected to the source electrode 16 and a drain in contact with the drain electrode 17 are provided. A lead electrode 18b is formed. The source lead electrode 18a and the drain lead electrode 18b are formed of a conductive material. The source electrode 16 and the drain electrode 17 are led out to the upper surface of the insulating layer 12 by the source lead electrode 18a and the drain lead electrode 18b.

  A gate electrode 11 is formed above the semiconductor layer 19 via an insulating layer 12.

  As described above, the second embodiment of the present invention includes the first semiconductor layer 13 that is the first barrier layer, the third semiconductor layer 14 that is the well layer, and the second barrier layer on the substrate 8. An oxide semiconductor layer 19 having a well-type potential structure configured by stacking second semiconductor layers 15 in order, a source electrode 16 and a drain electrode 17 electrically connected to the oxide semiconductor layer 19, and an oxide semiconductor layer A thin film transistor including a gate insulating film 12 formed on 19 and a gate electrode 11 formed on the oxide semiconductor layer 19 with the gate insulating film 12 interposed therebetween, which is a first barrier layer. Source electrode 16 or drain electrode 17 in the third semiconductor layer 14 that is a well layer among the semiconductor layer 13, the third semiconductor layer 14 that is a well layer, and the second semiconductor layer 15 that is a second barrier layer. The maximum contact area with It is characterized in.

With this configuration, when a current between the source and the drain is taken out, the number of carriers (electrons) that move through the barrier layer decreases, and the number of carriers (electrons) that move without passing through the barrier layer increases. As a result, the influence on the carriers due to defects in the barrier layer, interface states, surface states, and the like is reduced, and a thin film transistor with stable characteristics can be obtained.

<Embodiment 3>
The structure of the thin film transistor according to the third embodiment of the present invention will be described. The thin film transistor of Embodiment 3 is mainly different from the thin film transistor described in Embodiment 1 in the structure of the contact portion between the semiconductor layer and the source and drain electrodes. Specifically, the main difference is that a region not covered with the barrier layer is provided on the upper surface of the well layer, and the source electrode and the drain electrode are brought into contact with this region. Since the configuration other than this is the same as that of the first embodiment described above, the same reference numerals are given to the same elements, and the description thereof will not be repeated. In addition, since the operation of the third embodiment is the same as that of the above-described first embodiment, in addition to the configuration peculiar to the third embodiment described below and the effects resulting therefrom, it is the same as that of the first embodiment. There is also an effect. Hereinafter, the structure of the thin film transistor according to the third embodiment of the present invention will be described with reference to the drawings.

  FIG. 9 is a cross-sectional view of a thin film transistor 200 according to Embodiment 3 of the present invention. As shown in the figure, the thin film transistor 200 includes a substrate 8, a gate electrode 1, an insulating layer 2, a semiconductor layer 29, a source electrode 26, and a drain electrode 27.

  The semiconductor layer 29 includes a first semiconductor layer 23, a second semiconductor layer 25, and a third semiconductor layer 24. The semiconductor layer 29 is formed by stacking the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25 in this order on the gate electrode 1 with the insulating layer 2 interposed therebetween. The third semiconductor layer 24 is sandwiched between the first semiconductor layer 23 and the second semiconductor layer 25 and has a narrower band gap than the first and second semiconductor layers 23 and 25. Therefore, the semiconductor layer 29 forms a well-type potential. That is, the first semiconductor layer 23 is a barrier layer (first barrier layer, lower barrier layer), the third semiconductor layer 24 is a well layer (potential well layer), and the second semiconductor layer 25 is a barrier layer (second barrier layer). Barrier layer, upper barrier layer).

  The semiconductor layer 29 is formed using an InGaZnO-based oxide semiconductor. In order to realize the potential well of the semiconductor layer 29 with an InGaZnO-based oxide semiconductor having a three-layer structure, the Ga composition of the first and second semiconductor layers 23 and 25 is compared with the Ga composition of the third semiconductor layer 24. You should try to increase as much as possible.

  The semiconductor layer 29 is configured such that the width of the second semiconductor layer 25 that is the upper barrier layer is narrower than the width of the third semiconductor layer 24 that is the well layer. Therefore, a part of the end portion of the upper surface 24b of the third semiconductor layer 24 is not covered with the second semiconductor layer 25 but is exposed. The width direction of the semiconductor layer 29 is a direction parallel to the direction connecting the source electrode 26 and the drain electrode 27 (the X direction shown in FIG. 9). Further, the film thicknesses of the three semiconductor layers 23, 24, and 25 are not particularly limited as long as a well-type potential is formed as described in the first embodiment. Here, the film thicknesses of the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 are the same.

  The source electrode 26 and the drain electrode 27 are formed of a conductive material, and end surfaces (side surfaces) 23 a and 24 a of the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 constituting the semiconductor layer 29. , 25a and is electrically connected. Further, the source electrode 26 and the drain electrode 27 are in contact with and electrically connected to a part of the upper surface 25 b of the second semiconductor layer 25 and the exposed region of the upper surface 24 b of the third semiconductor layer 24. ing. Therefore, the source electrode 26 and the drain electrode 27 are in continuous contact from the upper surface 25b of the second semiconductor layer 25 that is the upper barrier layer to the lower end portion of the end surface 23a of the first semiconductor layer 23 that is the lower barrier layer. It is formed to do.

  When viewed from above, the width of the region of the upper surface of the third barrier layer 24 that is not covered by the second barrier layer 25 and is in contact with the source electrode or the drain electrode is L3. Further, the width of the region of the upper surface 25b of the second semiconductor layer 25 that is in contact with the source electrode 26 or the drain electrode 27 is L2. In the thin film transistor 200, the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 have the same film thickness, and L3> L2. Therefore, the contact area between the third semiconductor layer 24 and the source electrode 26 and the drain electrode 27 is larger than the contact area between the second semiconductor layer 25 and the source electrode 26 and the drain electrode 27.

  Next, a method for manufacturing the thin film transistor 200 according to the third embodiment of the present invention will be described. FIGS. 10A to 10M are schematic views schematically showing a manufacturing flow of the thin film transistor 200 according to the third embodiment of the present invention.

  First, as shown in FIGS. 10A and 10B, the patterned gate electrode 1 and the insulating layer 2 covering the gate electrode 1 are formed on the glass substrate 8. Further, as shown in FIG. 10C, a first semiconductor layer 23, a third semiconductor layer 24, and a second semiconductor layer 25 are formed on the insulating layer 2 by sputtering. The semiconductor layer 29 including the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25 is formed by continuously forming an InGaZnO-based oxide semiconductor layer. In the formation of the three layers of the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25, the first and second semiconductor layers 23 and 25 that are barrier layers are well layers. The semiconductor layer 24 is made to have a Ga-rich composition as compared with the composition of the third semiconductor layer 24. By doing so, a well-type potential in which the band gap of the first and second semiconductor layers 23 and 25 is wider than the band gap of the third semiconductor layer 24 can be formed.

  As described in Embodiment 1, the Ga ratio of the InGaZnO-based oxide semiconductor layer can be changed depending on the pressure at the time of film formation, the discharge power, and the like. Specifically, the Ga ratio can be increased by increasing the pressure during film formation or increasing the discharge power. Thus, an oxide semiconductor layer that forms a well-type potential can be realized by a continuous film formation process.

  Next, as shown in FIGS. 10D and 10E, the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer are formed using the resist 83a formed above the gate electrode 1 as a mask. 25 three oxide semiconductor layers are patterned. Patterning is performed by dry etching. By patterning, the end surfaces 23a, 24a, and 25a of the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25 are formed.

  Next, as shown in FIGS. 10F to 10H, after removing the resist 83a, another resist 83b narrower than the resist 83a is formed, and the second semiconductor layer is formed using the resist 83b as a mask. 25 is patterned. Patterning is performed by dry etching. By patterning, the third semiconductor layer 24 is slightly removed, but it is sufficient if it is not completely eliminated. By this step, a part of the second semiconductor layer 25 covering the third semiconductor layer 24 is removed, and a part of the upper surface of the third semiconductor layer 24 is exposed.

  Thereafter, as shown in FIGS. 10I and 10J, the resist 83b is removed, and a metal film 84 to be an electrode is formed on the entire surface of the substrate by sputtering or the like. The metal film 84 is in contact with the exposed regions of the end surface of the semiconductor layer 29 and the upper surface of the third semiconductor layer 25. The metal film 84 serving as an electrode may be formed using Ti, Mo, ITO, or the like.

  Next, as shown in FIGS. 10K and 10L, the metal film 84 on the semiconductor layer 29 is etched by photolithography using a resist 85 to form the source electrode 26 and the gate electrode 27.

  Finally, as shown in FIG. 10 (m), the resist 85 is removed. Through the above steps, the source electrode 26 and the gate electrode 27 are exposed in the exposed regions of the end surfaces of the first semiconductor layer 23, the third semiconductor layer 24, the second semiconductor layer 25, and the upper surface of the third semiconductor layer 25. A thin film transistor in contact with can be manufactured.

Next, electrons injected into the third semiconductor layer 24 having a narrow band gap will be described. Also in the thin film transistor 200 of the third embodiment, when a positive bias is applied to the gate electrode 1, mainly three types of electrons shown in the following (B1) to (B3) are applied to the third semiconductor layer 24 which is a well layer. Injected.
(B1) Electrons existing in the valence band of the second semiconductor layer 25 from the beginning (B2) Electrons flowing into the valence band of the second semiconductor layer 25 via the source electrode 26 and the drain electrode 27 (B3) Electrons directly injected from the source electrode 26 and the drain electrode 27 into the valence band of the third semiconductor layer 24

  Also in the third embodiment, the contact area between the third semiconductor layer 24 and the source electrode 26 and the drain electrode 27 is larger than the contact area between the second semiconductor layer 25 and the source electrode 26 and the drain electrode 27. Therefore, when a positive bias is applied to the gate electrode 1, the electrons injected into the third semiconductor layer 24 are dominant in (B3) from (B1) to (B3). In this way, by directly and most often injecting electrons into the third semiconductor layer 24 which is the main current between the source and drain electrodes 26 and 27, the influence of the electrons from the second semiconductor layer 25 is reduced. Electrons can be efficiently injected into the well layer.

  Further, when the source electrode 26 is grounded in a state where electrons are confined in the third semiconductor layer 24 and a positive bias is applied to the drain electrode 27, a current flows between the source and drain electrodes 26 and 27. Also in this case, electrons directly extracted from the third semiconductor layer 24 by the source electrode 26 and the drain electrode 27 become dominant. Therefore, the electrons are not affected by the film characteristics such as the defect level of the second semiconductor layer 25 unlike the case where the electrons are taken out via the second semiconductor layer 25, and further between the source and drain electrodes 26 and 27. The resistance can be reduced.

  Next, the effect of injecting electrons into the semiconductor layer 29 in the third embodiment is estimated. In FIG. 9, the shape of the thin film transistor 200 in the depth direction of the paper surface is assumed to be uniform, and the length of the contact portion between the semiconductor layer 29 and the source electrode 26 and drain electrode 27 in the depth direction of the paper surface is W. The film thicknesses of the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 are all 0.1 um. Further, the width L2 in the X direction of the contact portion between the upper surface of the second semiconductor layer 25 as the upper barrier layer and the source electrode 26 and the drain electrode 27 is 5 μm, and the upper surface and source of the third semiconductor layer 24 as the well layer The width L3 in the X direction of the contact portion between the electrode 26 and the drain electrode 27 is set to 10 μm. At this time, the area S11 of the contact portion between the first semiconductor layer 23 which is the lower barrier layer and the source electrode 26 and the drain electrode 27, the second semiconductor layer 25 which is the upper barrier layer, the source electrode 26 and the drain electrode 27, The area S12 of the contact portion, and the area S13 of the contact portion between the third semiconductor layer 24, which is a well layer, and the source electrode 26 and the drain electrode 27 are expressed by the following formula 2, respectively.

  The number of electrons injected from the source electrode 26 and drain electrode 27 into the semiconductor layer 29 increases as the contact area between the source electrode 26 and drain electrode 27 and the semiconductor layer increases. Therefore, as in the third embodiment, the configuration in which the contact area between the third semiconductor layer 24 and the source electrode 26 and the drain electrode 27 is maximized allows the main current between the source and drain 26 and 27 to be main. Thus, electrons can be efficiently injected into the well layer without passing through the barrier layer.

  Here, the contact area between the semiconductor layer and the source and drain electrodes is examined. The size of the semiconductor layer 29 in a top view is generally about several um to several tens of um in order to ensure the likelihood of photolithography in the manufacturing process. Therefore, it is easy to set the contact widths L2 and L3 with the source electrode 26 and the drain electrode 27 to about several um. On the other hand, the film thickness of each layer constituting the semiconductor layer 29 is usually 50 nm or less, and there is a difference of about 1 to 2 digits compared to the size of the semiconductor layer 29 in a top view. From the above, the configuration of the third embodiment has a larger contact area between the semiconductor layer and the source and drain electrodes than the configuration in which the contact area is increased by the thickness of the semiconductor layer as in the first embodiment. A large thin film transistor can be easily formed in a short time.

  As described above, in the third embodiment of the present invention, the third semiconductor layer 24 that is a well layer has a region that is not covered with the second semiconductor layer 25 that is the second barrier layer in a top view. The source electrode 26 or the drain electrode 27 is formed in contact with a region of the upper surface of the third semiconductor layer 24 that is a well layer that is not covered with the second semiconductor layer 25 that is the second barrier layer. It is characterized by that.

  With this configuration, the third semiconductor layer 24, the source electrode 26, and the drain, which are the main currents between the source and drain electrodes 26, 27, are formed without increasing the thickness of the third semiconductor layer 24, which is a well layer. The contact area with the electrode 27 can be enlarged. As a result, the process time can be shortened, and steps in the wiring layers such as the source electrode 26 and the drain electrode 27 can be reduced.

  The source electrode 26 and the drain electrode 27 are not necessarily in contact with the upper surface of the second semiconductor layer 25 as shown in FIG. The contact area between the third semiconductor layer 24 and the source electrode 26 and drain electrode 27 may be larger than the contact area between the second semiconductor layer 25 and the source electrode 26 and drain electrode 27. For example, a structure in which the source electrode 126 and the drain electrode 127 are not in contact with the upper surface of the second semiconductor layer 25 as in the thin film transistor 201 illustrated in FIG.

  Further, in the thin film transistor according to the third embodiment of the present invention, it is not necessary to have the same structure in all the directions perpendicular to the paper surface, and the source electrode 26 and the drain electrode 27 are in contact with the surface of the third semiconductor layer 24. May be partially present.

  For example, like the thin film transistor 202 shown in FIG. 12, the contact portion between the surface of the third semiconductor layer 34 and the source electrode 36 and the drain electrode 37 is realized by through holes 40 a and 40 b provided in the second semiconductor layer 35. May be. The through holes 40a and 40b are indicated by broken-line circles in FIG. FIG. 13 shows a cross section of the thin film transistor 202 taken along line XIII-XIII in FIG. With this configuration, the contact area of the contact between the third semiconductor layer 34 and the source electrode 36 and the drain electrode 37 can be increased as compared with the conventional case.

  Further, as in the thin film transistor 203 illustrated in FIG. 14, gaps 30 a and 30 b are provided between the second semiconductor layer 25 and the source electrode 226 and the drain electrode 227, so that the second semiconductor layer 25, the source electrode 226, and the drain electrode are provided. You may employ | adopt the structure where 227 does not contact directly. The gaps 30a and 30b may be about 0.2 to 0.3 μm, respectively. With this configuration, the injection of electrons into the third semiconductor layer 24 is limited to the source electrode 226 and the drain electrode 227, and the film quality of the second semiconductor layer 25 is further less affected.

  Further, as in the thin film transistor 204 illustrated in FIG. 15, the source electrode 46 and the drain electrode 47 are in contact with only the upper surface of the third semiconductor layer 44 and are in direct contact with the first semiconductor layer 43 and the second semiconductor layer 45. The structure which is not carried out may be sufficient. Specifically, the insulating layer 50 is formed on the semiconductor layer 49, and the third semiconductor layer 44 in which the source electrode 46 and the drain electrode 47 are well layers through the through holes 50a and 50b provided in the insulating layer 50. You may comprise so that it may contact the upper surface of. The through holes 50 a and 50 b are formed in the insulating layer 50 above the region of the third semiconductor layer 44 that is not covered with the second semiconductor layer 45.

  By adopting such a structure, the injection of carriers into the third semiconductor layer 44 is limited to the source electrode 46 and the drain electrode 47, and is less susceptible to the film quality of the second semiconductor layer 45. Electrons injected from the first semiconductor layer 43 into the third semiconductor layer 44 by diffusion can be suppressed.

<Embodiment 4>
In Embodiment 3, the structure in which the source electrode and the drain are directly arranged on the upper surface of the well layer in the bottom-gate thin film transistor has been described. However, the present invention can also be applied to a top-gate thin film transistor. The thin film transistor of Embodiment 4 of the present invention has a top gate structure, and the arrangement position of the electrode with respect to the semiconductor layer is mainly different from the thin film transistor shown in Embodiment 3. Since the configuration other than this is the same as that of the above-described third embodiment, the same elements are denoted by the same reference numerals, and the description thereof is not repeated. Further, since the operation of the fourth embodiment is the same as that of the above-described third embodiment, the same effects as those of the third embodiment are also obtained in the fourth embodiment described below. Hereinafter, the structure of the thin film transistor according to Embodiment 4 of the present invention will be described with reference to the drawings.

  FIG. 16 is a cross-sectional view of the thin film transistor 205 according to the fourth embodiment of the present invention. As shown in the figure, the thin film transistor 205 includes a substrate 8, a semiconductor layer 59, a source electrode 56, a drain electrode 57, an insulating layer 52, a gate electrode 51, a source extraction electrode 18a, and a drain extraction electrode 18b.

  A semiconductor layer 59, a source electrode 56, a drain electrode 57, an insulating layer 52, and a gate electrode 51 are formed on the insulating substrate 8.

  The semiconductor layer 59 includes a first semiconductor layer 53, a second semiconductor layer 55, and a third semiconductor layer 54. The semiconductor layer 59 is formed by stacking a first semiconductor layer 53, a third semiconductor layer 54, and a second semiconductor layer 55 in this order on the upper surface of the substrate 8. The third semiconductor layer 54 is sandwiched between the first semiconductor layer 53 and the second semiconductor layer 55 and has a narrower band gap than the first and second semiconductor layers 53 and 55. Therefore, the semiconductor layer 59 forms a well-type potential. That is, the first and second semiconductor layers 53 and 55 are barrier layers, and the third semiconductor layer 54 is a well layer.

  The semiconductor layer 59 is formed using an InGaZnO-based oxide semiconductor. In order to realize the potential well of the semiconductor layer 59 with an InGaZnO-based oxide semiconductor having a three-layer structure, the Ga compositions of the first and second semiconductor layers 53 and 55 are compared with the Ga composition of the third semiconductor layer 54. It is enough to increase as much as possible.

  The semiconductor layer 59 is configured such that the width of the second semiconductor layer 55 that is the upper barrier layer is narrower than the width of the third semiconductor layer 54 that is the well layer. Therefore, a part of the upper surface 54b of the third semiconductor layer 54 is not covered with the second semiconductor layer 55 but exposed. Note that the width direction of the semiconductor layer 59 is a direction parallel to the direction connecting the source electrode 56 and the drain electrode 57 (the X direction shown in FIG. 16). Further, the film thicknesses of the three semiconductor layers 53, 54, and 55 are not particularly limited as long as a well-type potential is formed as described in the first embodiment.

  The source electrode 56 and the drain electrode 57 are formed of a conductive material and are formed on the upper surface of the substrate 8. The source electrode 56 and the drain electrode 57 are in contact with end faces (side surfaces) 53 a, 54 a, 55 a of the first semiconductor layer 53, the second semiconductor layer 55, and the third semiconductor layer 54 that constitute the semiconductor layer 59. Are electrically connected. Further, the source electrode 56 and the drain electrode 57 are in contact with and electrically connected to the exposed region of the upper surface 54 b of the third semiconductor layer 54. Therefore, the source electrode 56 and the drain electrode 57 are continuous from the upper end of the end surface 55a of the second semiconductor layer 55 that is the upper barrier layer to the lower end portion of the end surface 53a of the first semiconductor layer 53 that is the lower barrier layer. Are formed so as to contact each other. In FIG. 16, the source electrode 56 and the drain electrode 57 are not in contact with the upper surface 55 b of the second semiconductor layer 55.

  The semiconductor layer 59, the source electrode 56 and the drain electrode 57 are covered with an insulating layer 52. The insulating layer 52 on the source electrode 56 and the drain electrode 57 is provided with a through hole, and the source lead electrode 18 a and the drain electrode 57 electrically connected to the source electrode 56 are electrically connected to the through hole. A drain lead electrode 18b connected to is formed. The source lead electrode 18a and the drain lead electrode 18b are formed of a conductive material. The source electrode 56 and the drain electrode 57 are drawn to the upper surface of the insulating layer 52 by the source lead electrode 18a and the drain lead electrode 18b.

  A gate electrode 51 is formed above the semiconductor layer 59 through an insulating layer 52.

  As described above, the fourth embodiment of the present invention includes the first semiconductor layer 53 that is the first barrier layer, the third semiconductor layer 54 that is the well layer, and the second barrier layer on the substrate 8. An oxide semiconductor layer 59 having a well-type potential structure formed by stacking the second semiconductor layers 55 in this order, a source electrode 56 and a drain electrode 57 electrically connected to the oxide semiconductor layer 59, and an oxide semiconductor layer A third semiconductor layer which is a thin film transistor including a gate insulating film 52 formed on 59 and a gate electrode 51 formed on the oxide semiconductor layer 59 with the gate insulating film 52 interposed therebetween, which is a well layer 54 has a region not covered with the second semiconductor layer 55 which is the second barrier layer in a top view, and the source electrode 56 or the drain electrode 57 is the upper surface of the third semiconductor layer 54 which is a well layer. Is the second barrier layer Characterized in that it is formed in contact with the areas not covered by the second semiconductor layer 55.

  With this configuration, even in a thin film transistor having a top-gate structure, the third semiconductor that is the main current between the source and drain electrodes 56 and 57 without increasing the thickness of the third semiconductor layer 54 that is a well layer. The contact area between the layer 54 and the source electrode 56 and drain electrode 57 can be increased. As a result, the process time can be shortened, and steps in the wiring layers such as the source electrode 56 and the drain electrode 57 can be reduced.

<Embodiment 5>
The present invention can also be applied to an etch stopper type thin film transistor. The thin film transistor of the fifth embodiment of the present invention is mainly different from the thin film transistor shown in the third embodiment in that an etch stopper layer is provided on the semiconductor layer. Since the configuration other than this is the same as that of the above-described third embodiment, the same elements are denoted by the same reference numerals, and the description thereof is not repeated. Further, since the operation of the thin film transistor of the fifth embodiment is the same as that of the above-described third embodiment, the same effects as those of the third embodiment are also obtained in the fifth embodiment described below. Hereinafter, the structure of the thin film transistor according to the fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 17 is a cross-sectional view of a thin film transistor 300 according to the fifth embodiment of the present invention. The cross-sectional structure shown in FIG. 17 is called an etch stopper type. As shown in the figure, the thin film transistor 300 includes a substrate 8, a gate electrode 1, an insulating layer 2, a semiconductor layer 29, an insulating layer 60 serving as an etch stopper layer, a source electrode 66, and a drain electrode 67. Note that the insulating layer 60 serving as an etch stopper layer is also simply referred to as an etch stopper layer.

  An etch stopper layer 60 is provided on the semiconductor layer 29. The width of the etch stopper layer 60 is substantially the same as that of the second semiconductor layer 25 that is the upper barrier layer, and is narrower than that of the third semiconductor layer 24 that is the well layer. Therefore, a part of the upper surface of the third semiconductor layer 24 is not covered with the second semiconductor layer 25 and the etch stopper layer 60 and is exposed.

  The source electrode 66 and the drain electrode 67 are in contact with and electrically connected to end faces (side surfaces) of the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 constituting the semiconductor layer 29. Yes. Further, the source electrode 66 and the drain electrode 67 are in contact with and electrically connected to the exposed region of the upper surface of the third semiconductor layer 24. Furthermore, the source electrode 66 and the drain electrode 67 are also in contact with part of the end surface and the upper surface of the etch stopper layer 60. Therefore, the source electrode 66 and the drain electrode 67 are formed so as to continuously contact from the upper surface of the etch stopper layer 60 to the lower end portion of the end surface of the first semiconductor layer 23 that is the lower barrier layer.

  In FIG. 17, the source electrode 66 and the drain electrode 67 do not have to have the same structure in the entire direction perpendicular to the paper surface, and the portion in contact with the upper surface of the etch stopper layer 60 partially exists in the paper surface vertical direction. Good.

  Further, the source electrode 66 and the drain electrode 67 are not necessarily in contact with the upper surface of the etch stopper layer 60, and the source electrode 166 and the drain electrode 167 are not necessarily in the etch stopper layer 60 as in the thin film transistor 301 shown in FIG. A structure that does not contact the upper surface may be used.

  Next, a method for manufacturing the thin film transistor 300 according to the fifth embodiment of the present invention will be described. FIGS. 19A to 19J are schematic diagrams schematically showing extracted steps different from the manufacturing flow of the thin film transistor of the third embodiment in the manufacturing flow of the thin film transistor 300 according to the fifth embodiment of the present invention. It is. FIG. 19A shows the same process as FIG.

  First, as shown in FIG. 19A, three layers of a first semiconductor layer 23, a third semiconductor layer 24, and a second semiconductor layer 25 are formed using a resist 83a formed above the gate electrode 1 as a mask. The semiconductor layer 29 composed of an oxide semiconductor layer is patterned. Here, the patterning may be performed using a PAN-based wet etchant or may be performed by dry etching.

  Next, as shown in FIGS. 19B and 19C, after the resist 83 a is peeled off, an etching stopper layer 60 is formed so as to cover the semiconductor layer 29. The etching stopper layer 60 is usually formed of a silicon oxide film.

  Next, as shown in FIGS. 19D and 19E, another resist 83c having a width smaller than the removed resist 83a is formed above the semiconductor layer 29. Next, as shown in FIG. Using this resist 83c as a mask, the silicon oxide film as the etching stopper layer 60 and the second semiconductor layer 25 are patterned. Patterning is performed by dry etching. At this time, the third semiconductor layer 24 is slightly removed, but it is sufficient that it is not completely eliminated. By this step, a part of the second semiconductor layer 25 and the etching stopper layer 60 covering the third semiconductor layer 24 is removed, and a part of the upper surface of the third semiconductor layer 24 is exposed.

  Thereafter, as shown in FIGS. 19F and 19G, the resist 83c is removed, and a metal film 86 to be an electrode is formed on the entire surface of the substrate 1 by sputtering or the like. The metal film 86 is in contact with the exposed regions of the etching stopper layer 60 and the end face and upper surface of the semiconductor layer 29. The metal film 86 serving as an electrode may be formed using Ti, Mo, ITO, or the like.

  Next, as shown in FIGS. 19H and 19I, the metal film 86 on the upper surface of the semiconductor layer 29 is etched by photolithography using a resist 87 to form the source electrode 66 and the gate electrode 67. Finally, as shown in FIG. 19J, the resist 87 is removed.

  Through the above steps, the thin film transistor 300 including the etching stopper layer and having the source electrode 66 and the gate electrode 67 in contact with the end surfaces of the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25 is manufactured. be able to.

  The thin film transistor according to the fifth embodiment of the present invention includes an etching stopper layer 60 on the second semiconductor layer 25 which is an upper barrier layer, and the third semiconductor layer 24 which is a well layer has a second barrier in a top view. The source electrode 66 or the drain electrode 67 has a region that is not covered with the second semiconductor layer 25 that is a layer, and the source electrode 66 or the drain electrode 67 is a second barrier layer of the upper surface of the third semiconductor layer 24 that is a well layer. It is characterized in that it is in contact with a region that is not covered with the semiconductor layer 25.

  As described above, the structure including the etching stopper layer 60 suppresses generation of defects on the upper surface of the second semiconductor layer 25 when the source electrode 66 and the drain electrode 67 are patterned, thereby reducing the leakage current of the transistor. be able to.

  In the fifth embodiment, as in the thin film transistor 302 shown in FIG. 20, the gaps 30c and 30d are provided between the etching stopper layer 60 and the second semiconductor layer 25, the source electrode 266, and the drain electrode 267, and etching is performed. A structure in which the stopper layer 60 and the second semiconductor layer 25 are not in direct contact with the source electrode 266 and the drain electrode 267 may be employed. With such a configuration, the injection of electrons into the third semiconductor layer 24 is limited to the source electrode 266 and the drain electrode 267 and is less affected by the film quality of the second semiconductor layer 25.

  Furthermore, in the method of manufacturing the thin film transistor of the fifth embodiment, the second semiconductor layer 25 that is the upper barrier layer can be etched using the patterning process of the silicon oxide film that becomes the etching stopper layer. Therefore, it is possible to expose the upper surface of the third semiconductor layer 24 without adding a new process.

<Embodiment 6>
The thin film transistor according to the sixth embodiment of the present invention is mainly different from the third embodiment in the manufacturing method. Since the configuration of the sixth embodiment is the same as that of the above-described third embodiment, the same elements are denoted by the same reference numerals and description thereof is not repeated. Since the operation of the sixth embodiment is the same as that of the third embodiment described above, the same effects as those of the third embodiment can be obtained in addition to the effects peculiar to the sixth embodiment described below. Hereinafter, the manufacturing method of the thin film transistor according to the sixth embodiment of the present invention will be described with reference to the drawings.

  FIGS. 21A to 21D schematically show the steps different from the manufacturing flow of the thin film transistor 200 according to the third embodiment out of the manufacturing flow of the thin film transistor according to the sixth embodiment of the present invention. It is a schematic diagram. FIG. 21A shows the same process as FIG.

  First, as shown in FIGS. 21A and 21B, using the resist 83a formed above the gate electrode 1 as a mask, the first semiconductor layer 23, the third semiconductor layer 24, and the second semiconductor layer 25 are used. These three oxide semiconductor layers are patterned. Specifically, patterning is performed by performing wet etching with a PAN-based etchant using the resist 83a as a mask. At this time, since the etching rate of the Ga-rich composition InGaZnO-based oxide semiconductor layer is high, the etching of the second semiconductor layer 25 proceeds faster than the etching of the third semiconductor layer 24, as shown in FIG. In addition, the second semiconductor layer 25 below the resist 83a is over-etched. As a result, a part of the upper surface of the third semiconductor layer 24 can be exposed.

  Thereafter, as shown in FIG. 21D, when the resist 83a is removed, the state is the same as that in FIG. 10I, which is the manufacturing flow of the third embodiment. The subsequent steps are the same as those in the third embodiment. Note that in the top gate thin film transistor 205 of Embodiment 4, part of the upper surface of the third semiconductor layer 54 can be exposed by overetching the second semiconductor layer 25 in the same manner.

  As described above, in the method of manufacturing the thin film transistor according to the sixth embodiment, a barrier layer having a higher etching rate than that of the well layer, that is, a composition that is easily etched, is formed on the upper layer of the well layer. A method for manufacturing a thin film transistor is characterized in that a region for disposing a source electrode and a drain electrode is formed on an upper surface of a well layer by exposing a surface. In this way, by utilizing the over-etching at the time of wet etching, the upper surface of the exposed third semiconductor layer 24 is added without adding a photoengraving process as shown in FIGS. A thin film transistor in which the source electrode 26 and the gate electrode 27 are in contact with each other can be manufactured.

  Further, the Ga composition of the first semiconductor layer 23, the second semiconductor layer 25, and the third semiconductor layer 24 is such that the third semiconductor layer 24 <the first semiconductor layer 23 <the second semiconductor layer 25. You may comprise. For example, the Ga ratio of the third semiconductor layer 24 that is the well layer is 5%, the Ga ratio of the first semiconductor layer 23 that is the lower barrier layer is 6%, and the Ga ratio of the second semiconductor layer 25 that is the upper barrier layer. The ratio is 7%. By setting the Ga composition to such a magnitude relationship, overetching of the first semiconductor layer 23 can be suppressed.

<Embodiment 7>
In Embodiment 7 of the present invention, a liquid crystal display device to which the thin film transistor according to Embodiments 1 to 6 of the present invention is applied as a switch for supplying charges to a pixel will be described. In this embodiment mode, a liquid crystal display device including the thin film transistor 101 of Embodiment Mode 1 is shown, but each of the thin film transistors 100, 102, 200, 201, 202, 203, 204, 205, described in Embodiment Modes 1 to 6 is described. Even the configuration including 300, 301, 302 has the same effect.

  FIG. 22 is a plan view schematically showing the configuration of the pixel portion of the liquid crystal display device. FIG. 23 is a cross-sectional view taken along section XXIII-XXIII in FIG. 24 is a diagram showing an equivalent circuit of the pixel shown in FIG. In FIG. 22, a region constituting the pixel P is indicated by a bold dashed rectangle, and a region constituting the thin film transistor (also referred to as a pixel transistor) T is indicated by a thin dashed rectangle.

  As shown in the figure, the liquid crystal display device according to the seventh embodiment includes a plurality of pixel electrodes 94, a plurality of pixel transistors T, a plurality of source lines 90, a plurality of gate lines 91, a plurality of auxiliary capacitance lines 92, and the like. A liquid crystal is sandwiched between the array substrate and a color filter substrate (not shown) provided with a color filter or the like. In FIG. 22, the gate insulating film 2 covering the gate wiring 91, the gate electrode 1 included in the pixel transistor T, the auxiliary capacitance wiring 92, and the like is seen through.

  The gate lines 91 extend in a straight line in parallel with each other. The gate wiring 91 has a portion protruding in a direction orthogonal to its extending direction, and the protruding portion constitutes the gate electrode 1. The source wiring 90 extends in a straight line parallel to each other in a direction orthogonal to the gate wiring 91. In other words, the plurality of source lines 90 are arranged in the extending direction of the gate line 91. The auxiliary capacitance line 92 is disposed adjacent to the gate line 91 and extends linearly in parallel with the gate line 91. The auxiliary capacitance line 92 has a portion protruding in a direction perpendicular to the extending direction of the auxiliary capacitance wiring 92, and the protruding portion constitutes the auxiliary capacitance electrode 93.

  One pixel P is defined in a region surrounded by two adjacent source lines 90 and two adjacent gate lines 91. A pixel transistor T is provided in the vicinity of the intersection between the source wiring 90 and the gate wiring 91. Each pixel P includes an auxiliary capacitance electrode 93, a pixel electrode 94, and a pixel transistor T. The pixel transistor T is a bottom-gate transistor, as shown in a cross section in FIG. 23, and plays a role of a charge supply switch to the pixel electrode 94. The drain electrode 107 of the pixel transistor T is connected to the pixel electrode 94 through the contact hole 95.

  Here, the pixel P will be described with reference to FIG. Each pixel P is provided with at least one pixel transistor T. The pixel transistor T is disposed in the vicinity of the intersection between the gate line 91 and the source line 90. The gate electrode 1 of the pixel transistor T is connected to the gate wiring 91, and the source electrode 106 of the pixel transistor T is connected to the source wiring 90. The drain electrode 107 of the pixel transistor T is connected to the pixel electrode 94.

  The pixel electrode 94 constitutes an auxiliary capacitor 96 in combination with the auxiliary capacitor electrode 93 provided on the auxiliary capacitor line 92. Further, the pixel electrode 94 forms a pixel capacitor 97 in combination with the common electrode. Although not shown, the common electrode is provided on the color filter substrate in the TN method or the like, and is provided on the array substrate in the FFS method or the IPS method.

  As described above, in the seventh embodiment, the liquid crystal display device is configured using the thin film transistors described in the first to sixth embodiments. As described above, by applying the thin film transistor according to any of the first to sixth embodiments, the same effect as in the first to sixth embodiments can be obtained, so that a liquid crystal display device with stable operation can be realized.

  It should be understood that the above-described embodiment is illustrative in all respects and not restrictive. The scope of the present invention is shown not by the scope of the embodiment described above but by the scope of claims, and includes all modifications within the meaning and scope equivalent to the scope of claims.

  DESCRIPTION OF SYMBOLS 1 Gate electrode, 2 Insulation layer, 3 1st semiconductor layer, 4 3rd semiconductor layer, 5 2nd semiconductor layer, 6 Source electrode, 7 Drain electrode, 8 Substrate, 9 Semiconductor layer, 11 Gate electrode, 12 Insulation Layer, 13 first semiconductor layer, 14 third semiconductor layer, 15 second semiconductor layer, 16 source electrode, 17 drain electrode, 19 semiconductor layer, 30a void, 30b void, 30c void, 30d void, 40a through hole 40b through hole, 52 insulating layer, 52a through hole, 52b through hole, 60 etching stopper layer, 83a resist, 80b resist, 80c resist.

Claims (6)

A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
An oxide semiconductor layer having a well-type potential structure in which a first barrier layer, a well layer, and a second barrier layer are sequentially stacked on the gate electrode via the gate insulating film;
A thin film transistor including a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
Of the first barrier layer, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer ,
The well layer has a region not covered with the second barrier layer in a top view;
The source electrode or the drain electrode is formed in contact with a region of the upper surface of the well layer that is not covered with the second barrier layer, and has a gap with the second barrier layer.
A thin film transistor. A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
An oxide semiconductor layer having a well-type potential structure in which a first barrier layer, a well layer, and a second barrier layer are sequentially stacked on the gate electrode via the gate insulating film;
A thin film transistor including a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
Of the first barrier layer, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer ,
The well layer has a region not covered with the second barrier layer in a top view;
The source electrode or the drain electrode is formed in contact with a region of the upper surface of the well layer that is not covered with the second barrier layer,
An etching stopper layer on the second barrier layer;
A thin film transistor. A gate electrode formed on the substrate;
A gate insulating film formed on the gate electrode;
An oxide semiconductor layer having a well-type potential structure in which a first barrier layer, a well layer, and a second barrier layer are sequentially stacked on the gate electrode via the gate insulating film;
A thin film transistor including a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
Of the first barrier layer, the well layer, and the second barrier layer, the contact area with the source electrode or the drain electrode is maximized in the well layer ,
The well layer has a region not covered with the second barrier layer in a top view;
The source electrode or the drain electrode is formed in contact with a region of the upper surface of the well layer that is not covered with the second barrier layer, and has a gap between the second barrier layer and the second barrier layer. ,
An etching stopper layer on the second barrier layer;
A thin film transistor. The liquid crystal display device provided with the thin-film transistor of any one of Claims 1-3 . Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a well-type potential structure oxide semiconductor layer by sequentially stacking a first barrier layer, a well layer, and a second barrier layer via the gate insulating film on the gate electrode;
Forming a first mask on the gate electrode;
Etching the oxide semiconductor layer using the first mask;
Removing the first mask;
Forming an etching stopper layer on the substrate;
Forming a second mask on the etching stopper layer;
Etching the etching stopper layer and the second barrier layer using the second mask to expose an upper surface of the well layer and forming a region connecting the source electrode or the drain electrode;
And a step of forming the source electrode or the drain electrode in contact with the region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
An oxide having a well-type potential structure in which a first barrier layer, a well layer, and a second barrier layer having a composition that is more easily etched than the well layer are sequentially stacked on the gate electrode through the gate insulating film. Forming a semiconductor layer;
Forming a mask on the gate electrode;
Etching the oxide semiconductor layer using the mask, overetching to remove a portion of the second barrier layer under the mask to expose an upper surface of the well layer; Forming a region connecting the source electrode or the drain electrode;
Removing the mask;
And a step of forming the source electrode or the drain electrode in contact with the region.

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