JP6116413B2 - Method for manufacturing power semiconductor device - Google Patents
Method for manufacturing power semiconductor device Download PDFInfo
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- JP6116413B2 JP6116413B2 JP2013143186A JP2013143186A JP6116413B2 JP 6116413 B2 JP6116413 B2 JP 6116413B2 JP 2013143186 A JP2013143186 A JP 2013143186A JP 2013143186 A JP2013143186 A JP 2013143186A JP 6116413 B2 JP6116413 B2 JP 6116413B2
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- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 238000000034 method Methods 0.000 title claims description 36
- 239000000463 material Substances 0.000 claims description 32
- 238000009434 installation Methods 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000005304 joining Methods 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 12
- 239000002923 metal particle Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- 239000012459 cleaning agent Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910000510 noble metal Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 23
- 229910052709 silver Inorganic materials 0.000 description 21
- 239000004332 silver Substances 0.000 description 21
- 238000004140 cleaning Methods 0.000 description 14
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000002829 reductive effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000005751 Copper oxide Substances 0.000 description 6
- 229910000431 copper oxide Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000004506 ultrasonic cleaning Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003638 chemical reducing agent Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- -1 diamond Chemical compound 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
本発明は、焼結性金属接合材を用いて電力用半導体素子を実装した電力用半導体装置の製造方法に関するものである。 The present invention relates to a method for manufacturing a power semiconductor device in which a power semiconductor element is mounted using a sinterable metal bonding material.
半導体装置の中でも電力用半導体装置は、産業用機器から家電・情報端末まで幅広い機器の主電力（パワー）の制御に用いられ、とくに高い信頼性と小型化が求められている。近年、とくに大電流を流すことができ、高温動作も可能なワイドバンドギャップ半導体材料である炭化珪素（ＳｉＣ）がシリコン（Ｓｉ）に代わる半導体材料として開発が進められている。 Among semiconductor devices, power semiconductor devices are used to control main power of a wide range of devices from industrial equipment to home appliances and information terminals, and particularly high reliability and miniaturization are required. In recent years, silicon carbide (SiC), which is a wide band gap semiconductor material capable of flowing a particularly large current and capable of high-temperature operation, has been developed as a semiconductor material replacing silicon (Si).
一方、これまで用いられてきたはんだでは、高温動作への対応は困難であり、焼結接合材と呼ばれるナノあるいは、マイクロレベルの金属微粒子を含むペーストによる接合が高温対応の接合技術として提案されている（例えば、特許文献１〜４参照。）。 On the other hand, it has been difficult to cope with high-temperature operation with the solders used so far, and joining with paste containing nano- or micro-level metal fine particles called sintered joining materials has been proposed as a joining technique for high temperatures. (For example, refer to Patent Documents 1 to 4.)
このような焼結接合材による接合は、接合時の温度よりも接合後の融点の方が高くなるため、高温運転が想定される電力用半導体装置の信頼性を向上させることが期待できる。しかしながら、焼結接合材は、所定の接合力を得るためには、原理的に接合時に加圧力を必要とする。そのため、焼結接合材を塗布した際の余り部あるいはニジミ部は接合時に圧力の掛からない無加圧状態となり、以降の工程で脱離の可能性がある。この脱離物が製品内に残留すると、様々な不具合を引き起こす可能性があり、信頼性を阻害する要因となっていた。 In such a joining with a sintered joining material, since the melting point after joining becomes higher than the temperature at the time of joining, it can be expected to improve the reliability of the power semiconductor device assumed to be operated at a high temperature. However, in order to obtain a predetermined bonding force, the sintered bonding material in principle requires a pressing force during bonding. For this reason, the surplus part or the blurring part when the sintered joining material is applied is in a non-pressurized state where no pressure is applied during joining, and there is a possibility of detachment in the subsequent steps. If this desorbed substance remains in the product, it may cause various problems, which has been a factor that hinders reliability.
本発明は、上記のような課題を解決するためになされたもので、高温に対応し、かつ信頼性の高い電力用半導体装置を得ることを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a power semiconductor device that can cope with high temperatures and has high reliability.
本発明の電力用半導体装置の製造方法は、焼結性金属粒子を含有する接合材を用いて、電力用半導体素子と回路基板との接合を行う電力用半導体装置の製造方法であって、前記回路基板の電極の表面のうち、前記電力用半導体素子の設置領域の外周に所定の領域を残して前記設置領域を囲む第一領域から、前記設置領域に内包される第二領域を除いた領域に、加熱によって酸化膜を形成する工程と、前記設置領域を網羅するように、前記第一領域内に前記接合材を塗布する工程と、前記設置領域に前記電力用半導体素子を設置する工程と、前記回路基板と前記電力用半導体素子との間に圧力をかけながら加熱して、前記焼結性金属粒子の焼結体を形成し、前記電力用半導体素子と前記電極とを接合する工程と、前記酸化膜を溶解する洗浄剤を用い、前記焼結体のうち、前記電力用半導体素子からはみ出た部分を前記酸化膜とともに除去する工程と、を順次実行することを特徴とする。 A method for manufacturing a power semiconductor device according to the present invention is a method for manufacturing a power semiconductor device in which a power semiconductor element and a circuit board are bonded using a bonding material containing sinterable metal particles, Of the surface of the electrode of the circuit board, a region excluding a second region included in the installation region from a first region surrounding the installation region leaving a predetermined region on the outer periphery of the installation region of the power semiconductor element A step of forming an oxide film by heating, a step of applying the bonding material in the first region so as to cover the installation region, and a step of installing the power semiconductor element in the installation region. Heating while applying pressure between the circuit board and the power semiconductor element to form a sintered body of the sinterable metal particles, and joining the power semiconductor element and the electrode; , A cleaning agent that dissolves the oxide film There, among the sintered body, and executes a step of removing the protruding portion from the power semiconductor element together with the oxide film, sequentially.
本発明の電力用半導体装置の製造方法によれば、接合時に加圧されなかった焼結体の残留を抑制できるので、高温に対応し、かつ信頼性が高い電力用半導体装置を得ることができる。 According to the method for manufacturing a power semiconductor device of the present invention, it is possible to suppress the remaining of the sintered body that has not been pressurized at the time of joining, and thus it is possible to obtain a power semiconductor device that can handle high temperatures and has high reliability. .
実施の形態１．
図１および図２は、本発明の実施の形態１にかかる電力用半導体装置の製造方法について説明するためのものであって、図１は本製造方法で製造した電力用半導体装置の構成を示すもので、図１（ａ）は平面図、図１（ｂ）は図１（ａ）におけるＢ−Ｂ線による断面図である。図２（ａ）〜（ｆ）は、本製造方法を説明するためのもので、図１（ａ）のＢ−Ｂ線による断面図のうち、絶縁基材より上側の部分に相当する部分の製造工程ごとの状態を示す図である。
Embodiment 1 FIG.
1 and 2 are for explaining a method for manufacturing a power semiconductor device according to a first embodiment of the present invention. FIG. 1 shows a configuration of a power semiconductor device manufactured by the present manufacturing method. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line BB in FIG. 2 (a) to 2 (f) are for explaining the manufacturing method, and in the cross-sectional view taken along the line BB in FIG. 1 (a), the portion corresponding to the portion above the insulating substrate. It is a figure which shows the state for every manufacturing process.
本実施の形態１にかかる電力用半導体装置の製造方法の説明の前に、本製造方法により得られた電力用半導体装置の基本構成について、図１を用いて説明する。電力用半導体装置１０は窒化ケイ素（Ｓｉ３Ｎ４）等のセラミックス板を絶縁基材４ｉとし、両面に銅（Ｃｕ）の電極４ｆ、４ｒをろう付け処理した３０ｍｍ×４０ｍｍ×１ｍｍｔの回路基板４と、回路基板４の回路面側の電極４ｆの所定領域に焼結接合材による接合層２を介して裏面が接合された９ｍｍ×９ｍｍ大の電力用半導体素子１とを備えている。そして、電極４ｆの電力用半導体素子１が接合された領域は、他の領域よりも厚みが厚く、接合層２との境界部分に２μｍ以上の部分金（Ａｕ）メッキ層（被覆膜３）が形成されている。 Prior to the description of the manufacturing method of the power semiconductor device according to the first embodiment, the basic configuration of the power semiconductor device obtained by the manufacturing method will be described with reference to FIG. The power semiconductor device 10 is a circuit board 4 of 30 mm × 40 mm × 1 mmt in which a ceramic plate such as silicon nitride (Si 3 N 4 ) is used as an insulating base 4i and copper (Cu) electrodes 4f and 4r are brazed on both sides. And a 9 mm × 9 mm large power semiconductor element 1 having a back surface bonded to a predetermined region of the electrode 4 f on the circuit surface side of the circuit board 4 via a bonding layer 2 made of a sintered bonding material. And the area | region where the power semiconductor element 1 of the electrode 4f was joined is thicker than another area | region, and a partial gold (Au) plating layer (covering film 3) of 2 micrometers or more in the boundary part with the joining layer 2 Is formed.
電力用半導体素子１は、例えば、スイッチング素子としてＩＧＢＴ（Insulated Gate Bipolar Transistor）を用いた場合、裏面にはコレクタ電極が形成され、主面（表面）には主電力電極であるエミッタ電極と、制御電極であるゲート電極が形成されている。さらに、電力用半導体素子１としては、ＭＯＳＦＥＴ(Metal Oxide Semiconductor Field-Effect Transistor)の他、整流素子であるＳＢＤ（Schottky Barrier diode）、ＦＷＤ(Free Wheeling Diode)などを用いることができる。 For example, when an IGBT (Insulated Gate Bipolar Transistor) is used as a switching element, the power semiconductor element 1 has a collector electrode formed on the back surface and an emitter electrode that is a main power electrode on the main surface (front surface). A gate electrode, which is an electrode, is formed. Furthermore, as the power semiconductor element 1, in addition to a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), an SBD (Schottky Barrier Diode), an FWD (Free Wheeling Diode), or the like, which is a rectifier element, can be used.
なお、回路基板４の電極４ｒおよび、電力用半導体素子１の表面側には、外部回路との電気接続を行うための図示しない電極端子等が接合され、回路面の反対側である電極４ｒには、電力用半導体素子１で発生した熱を除去するために、図示しない冷却部材が設けられている。そして、電力用半導体素子１を含む回路面は図示しない封止樹脂で覆われていることが一般的に行われている。しかし、この段落で説明した部分は、本発明には、直接関係しない部分であるので、これらの説明を省略して製造方法の説明に移る。なお、以下、サイズや工程に関する記載の際は、電力用半導体素子１を「チップ」と称する。 An electrode terminal (not shown) for electrical connection with an external circuit is joined to the electrode 4r of the circuit board 4 and the surface side of the power semiconductor element 1, and the electrode 4r on the opposite side of the circuit surface is joined to the electrode 4r. In order to remove the heat generated in the power semiconductor element 1, a cooling member (not shown) is provided. The circuit surface including the power semiconductor element 1 is generally covered with a sealing resin (not shown). However, since the part described in this paragraph is a part not directly related to the present invention, the description is omitted and the description shifts to the manufacturing method. Hereinafter, the power semiconductor element 1 will be referred to as a “chip” when describing the size and process.
図２（ａ）に示すように、電極４ｆのうち、電力用半導体素子１を接合する領域（設置領域：９ｍｍ×９ｍｍ）に、部分金メッキにより厚さ２μｍ以上の被覆膜３を形成する。この被覆膜３は、次の熱処理工程にて、下地の銅が酸化するのを防ぐ役割があり、ピンホール等の欠陥が形成されないよう注意する必要がある。なお、上記の条件（所定領域で下地の銅が酸化するのを防ぐ）を満たすならば被覆方法は問わない。また、被覆金属も金に限らず、後述する酸化膜を形成する工程で酸化を防ぐものであれば、例えば、白金（Ｐｔ）、パラジウム（Ｐｄ）等の貴金属を用いることができる。 As shown in FIG. 2A, a coating film 3 having a thickness of 2 μm or more is formed by partial gold plating in a region (installation region: 9 mm × 9 mm) of the electrode 4f where the power semiconductor element 1 is bonded. This coating film 3 has a role of preventing the underlying copper from being oxidized in the next heat treatment step, and care must be taken so that no defects such as pinholes are formed. Note that the coating method is not limited as long as the above conditions (preventing oxidation of the underlying copper in a predetermined region) are satisfied. Further, the coating metal is not limited to gold, and a noble metal such as platinum (Pt) or palladium (Pd) can be used as long as it prevents oxidation in the step of forming an oxide film described later.
また、被覆膜３のサイズ（被覆領域）に関して、チップサイズよりも少し小さなサイズとしても良い。この場合、被覆膜３が電力用半導体素子１の設置領域からはみ出るというチップマウント時の位置ズレリスクを軽減することができる。なお、この場合、次の工程中の構造として、チップ直下に酸化膜が食い込む形となるが、その食い込み程度を制限することで、接合に関する問題も回避することができる。少し小さなサイズの領域としては、例えば、その外周が、チップの中心よりも側部に近い位置になる領域などがある。 Further, the size of the coating film 3 (covering region) may be a little smaller than the chip size. In this case, the positional deviation risk at the time of chip mounting that the coating film 3 protrudes from the installation region of the power semiconductor element 1 can be reduced. In this case, as a structure in the next process, an oxide film bites in immediately below the chip. However, by limiting the biting level, a problem related to bonding can be avoided. As an area of a slightly smaller size, for example, there is an area where the outer periphery is located closer to the side than the center of the chip.
このように一部に被覆膜３を形成した回路基板４（上述したように、図では電極４ｆより上側部分のみ表示）に大気中で２００〜４００℃の温度で熱処理を行い、図２（ｂ）に示すように、電極４ｆの表面に、銅の酸化膜５を形成した。酸化膜５の組成（例えば、ＣｕＯあるいはＣｕ２Ｏのどちらであるか等）は問わないが、厚みは所定（２３０ｎｍ）以上に形成した。このとき、電極４ｆの表面のうち、チップ接合部となる領域は、被覆膜３が形成されているため、酸化を防ぐことができる。 The circuit board 4 having the coating film 3 partially formed in this way (as described above, only the upper part of the electrode 4f is shown in the figure) is heat-treated in the atmosphere at a temperature of 200 to 400 ° C. As shown in b), a copper oxide film 5 was formed on the surface of the electrode 4f. The composition of the oxide film 5 (for example, whether it is CuO or Cu 2 O, etc.) does not matter, but the thickness is formed to be a predetermined (230 nm) or more. At this time, since the coating film 3 is formed in the region of the surface of the electrode 4f that serves as the chip bonding portion, oxidation can be prevented.
次に、図２（ｃ）に示すように、回路基板４のチップ接合領域に、ナノ銀（Ａｇ）粒子による焼結接合材のペースト２Ｐを印刷する。印刷サイズは、１０ｍｍ×１０ｍｍと、チップ設置領域を内包するように、チップサイズよりも意図的に大きくし、印刷位置ズレがあっても、マウント時にチップが印刷エリア外に出ないようにした。印刷厚みは、接合後の段階で、接合層厚みが１０〜１００μｍとなる厚みとした。なお、焼結接合材も銀に限ることなく、電力用半導体素子１と電極４ｆ（あるいは被覆膜３）とを接合できるのであれば、他の材料であってもよい。 Next, as shown in FIG. 2 (c), a paste 2 </ b> P of a sintered bonding material made of nano silver (Ag) particles is printed on the chip bonding region of the circuit board 4. The print size is 10 mm × 10 mm, which is intentionally larger than the chip size so as to include the chip installation area, so that the chip does not come out of the print area when mounted even if there is a print position shift. The printing thickness was set to a thickness at which the bonding layer thickness was 10 to 100 μm at the stage after bonding. The sintered bonding material is not limited to silver, and may be other materials as long as the power semiconductor element 1 and the electrode 4f (or the coating film 3) can be bonded.
印刷後、図２（ｄ）に示すように、電極４ｆの被覆膜３で被覆された領域を内包するように電力用半導体素子１をマウントする。そして、１０〜５０ＭＰａの圧力を掛けながら、２００〜４００℃に加熱することで、焼結銀による電力用半導体素子１と電極４ｆとの接合層２が形成される。 After printing, as shown in FIG. 2D, the power semiconductor element 1 is mounted so as to enclose the region covered with the coating film 3 of the electrode 4f. And the joining layer 2 of the semiconductor element 1 for electric power and the electrode 4f by sintered silver is formed by heating at 200-400 degreeC, applying a pressure of 10-50 Mpa.
上記のように電力用半導体素子１が接合された回路基板４に、（銅酸化膜）除去剤を用いて湿式超音波洗浄を実施し、回路基板４上の酸化膜５を除去する。この際、図２（ｅ）に示すように、酸化膜５上の各種異物、汚れも除去剤によって除去された除去酸化膜５Ｒと一緒に除去される。なお、ペースト２Ｐには、銅酸化膜還元剤が添加されているため、自然酸化膜程度の被膜であれば印刷後に還元される。そのため、大気中での熱処理工程を経ずに接合を行うと、チップ接合エリアからはずれた電極表面のうち、ペースト２Ｐが塗布された部分の酸化被膜が除去されてしまい、焼結銀との部分接合が進行するので、洗浄後にも無加圧の焼結銀が電極４ｆ上に残留してしまう。 The circuit board 4 to which the power semiconductor element 1 is bonded as described above is subjected to wet ultrasonic cleaning using a (copper oxide film) remover, and the oxide film 5 on the circuit board 4 is removed. At this time, as shown in FIG. 2E, various foreign matters and dirt on the oxide film 5 are also removed together with the removed oxide film 5R removed by the remover. In addition, since the copper oxide film reducing agent is added to the paste 2P, if it is a film about a natural oxide film, it is reduced after printing. Therefore, when bonding is performed without passing through a heat treatment step in the atmosphere, the oxide film on the portion of the electrode surface that is off the chip bonding area where the paste 2P is applied is removed, and the portion with the sintered silver is removed. Since joining proceeds, unpressurized sintered silver remains on the electrode 4f even after cleaning.
しかし、本実施の形態１にかかる電力用半導体装置の製造方法では、接合工程の前に、大気中（酸化雰囲気）での熱処理により、被覆膜３が形成された部分を取り巻く領域には、所定厚み以上の（銅）酸化膜５が形成されている。そのため、洗浄による酸化膜を除去する段階でも、被覆膜３が形成された領域の外側の部分では、ペースト２Ｐと電極４ｆとの間には、酸化膜５が介在する。つまり、焼結銀のうち、接合層２として寄与しない無加圧の部分（無加圧部２Ｒ）と電極４ｆの金属銅との間には酸化膜５が存在する。その結果、チップ直下から外れた印刷余り部、ニジミ部（無加圧部２Ｒ）は、湿式超音波洗浄により、図２（ｆ）のように除去酸化膜５Ｒと一緒に除去される。 However, in the method for manufacturing the power semiconductor device according to the first embodiment, the region surrounding the portion where the coating film 3 is formed by heat treatment in the atmosphere (oxidizing atmosphere) before the bonding step is A (copper) oxide film 5 having a predetermined thickness or more is formed. Therefore, even in the stage of removing the oxide film by cleaning, the oxide film 5 is interposed between the paste 2P and the electrode 4f in the portion outside the region where the coating film 3 is formed. That is, the oxide film 5 exists between the non-pressurized part (non-pressurized part 2R) which does not contribute as the joining layer 2 among sintered silver, and the metal copper of the electrode 4f. As a result, the excess printing portion and the blurring portion (non-pressurized portion 2R) deviated from immediately below the chip are removed together with the removed oxide film 5R as shown in FIG. 2F by wet ultrasonic cleaning.
洗浄後、回路基板４と図示しないベース板を還元性雰囲気リフローによりはんだ接合し、図示しないモジュール用ケースに取り付け、ワイヤーボンド結線し、樹脂による封止を行うことで、電力用半導体装置１０を作製した。この洗浄後の工程には、例えばワイヤーボンド結線の際の振動など、接合層２およびその周辺部分に衝撃が加わる工程があるが、酸化膜５と一緒に無加圧部２Ｒを除去しているため、脱離物は形成されなかった。 After cleaning, the circuit board 4 and a base plate (not shown) are solder-bonded by reductive atmosphere reflow, attached to a module case (not shown), wire-bonded, and sealed with resin to produce the power semiconductor device 10. did. In this post-cleaning process, for example, there is a process in which impact is applied to the bonding layer 2 and its peripheral part such as vibration during wire bond connection, but the non-pressurized part 2R is removed together with the oxide film 5. Therefore, no desorbed material was formed.
なお、例えば、酸化膜５の代わりに、有機物によるマスキングを施した場合、洗浄工程後にマスキングの一部が残留して、回路部材を汚染し、動作信頼性が損なわれることが懸念される。しかし、本実施の形態１にかかる電力用半導体装置の製造方法のように、無加圧部２Ｒを除去するための膜として、もともと電極４ｆを構成した金属（銅）の酸化膜５を用いているので、除去後に不純物が残ることなく、信頼性を損ねる心配もない。 For example, when masking with an organic substance is performed instead of the oxide film 5, there is a concern that a part of the masking remains after the cleaning process, contaminates the circuit member and impairs the operation reliability. However, as in the method for manufacturing the power semiconductor device according to the first embodiment, the metal (copper) oxide film 5 originally constituting the electrode 4f is used as the film for removing the non-pressurized portion 2R. As a result, no impurities remain after removal, and there is no fear of impairing reliability.
比較例として、チップ接合部である９ｍｍ×９ｍｍの領域に被覆膜３を形成せず、熱処理工程を経ずに接合を行い、電力用半導体装置を作製した結果、ワイヤーボンド結線工程における振動にて、焼結銀の脱離物が検出された。 As a comparative example, the coating film 3 was not formed in the 9 mm × 9 mm region that is the chip bonding portion, and bonding was performed without going through the heat treatment process, and as a result, a power semiconductor device was manufactured. As a result, detachment of sintered silver was detected.
以上のように、本発明の実施の形態１にかかる電力用半導体装置の製造方法によれば、焼結性金属粒子を含有する接合材（ペースト２Ｐ）を用いて、電力用半導体素子１と回路基板４との接合を行う電力用半導体装置１０の製造方法であって、回路基板４の電極４ｆの表面のうち、電力用半導体素子１の設置領域に内包される領域（接合領域）に貴金属の被覆膜３を形成する工程と、加熱によって酸化膜５を形成する工程と、設置領域を網羅するように、設置領域の外周に所定の領域を残して設置領域を囲む領域に接合材（ペースト２Ｐ）を塗布する工程と、設置領域に、電力用半導体素子１を設置する工程と、回路基板４と電力用半導体素子１との間に圧力をかけながら加熱して、焼結性金属粒子の焼結体（接合層２）を形成し、電力用半導体素子１と電極４ｆとを接合する工程と、酸化膜５を溶解する洗浄剤（酸化膜除去剤）を用い、焼結体のうち、電力用半導体素子１からはみ出た部分（無加圧部２Ｒ）を酸化膜５とともに除去する工程と、を順次実行するように構成したので、接合時に加圧されなかった焼結体（無加圧部２Ｒ）の残留を抑制できるので、高温に対応し、かつ信頼性が高い電力用半導体装置１０を得ることができる。 As described above, according to the method for manufacturing the power semiconductor device according to the first embodiment of the present invention, the power semiconductor element 1 and the circuit are formed using the bonding material (paste 2P) containing the sinterable metal particles. In the method for manufacturing the power semiconductor device 10 for bonding to the substrate 4, a region (bonding region) of the surface of the electrode 4 f of the circuit substrate 4 that is included in the installation region of the power semiconductor element 1 (bonding region) is made of noble metal. A step of forming the coating film 3, a step of forming the oxide film 5 by heating, and a bonding material (paste) in a region surrounding the installation region leaving a predetermined region on the outer periphery of the installation region so as to cover the installation region 2P), a step of installing the power semiconductor element 1 in the installation region, and heating while applying pressure between the circuit board 4 and the power semiconductor element 1, Form a sintered body (bonding layer 2) The portion of the sintered body that protrudes from the power semiconductor element 1 (non-pressurized portion) using a step of bonding the body element 1 and the electrode 4f and a cleaning agent (oxide film removing agent) that dissolves the oxide film 5 2R) together with the oxide film 5 are sequentially executed, so that it is possible to suppress the remaining of the sintered body (non-pressurized portion 2R) that has not been pressurized at the time of joining. In addition, a highly reliable power semiconductor device 10 can be obtained.
実施の形態２．
上記実施の形態１にかかる電力用半導体装置の製造方法では、チップ接合領域を確保するために被覆膜を形成する例について説明した。本実施の形態２にかかる電力用半導体装置の製造方法では、酸化膜を部分的に除去することにより、チップ接合領域を形成する例について説明する。
Embodiment 2. FIG.
In the method for manufacturing the power semiconductor device according to the first embodiment, the example in which the coating film is formed in order to secure the chip bonding region has been described. In the method for manufacturing the power semiconductor device according to the second embodiment, an example in which the chip bonding region is formed by partially removing the oxide film will be described.
図３および図４は、本発明の実施の形態２にかかる電力用半導体装置の製造方法について説明するためのものであって、図３は本製造方法で製造した電力用半導体装置の構成を示すもので、図３（ａ）は平面図、図３（ｂ）は図３（ａ）におけるＢ−Ｂ線による断面図である。図４（ａ）〜（ｇ）は、本製造方法を説明するためのもので、図３（ａ）のＢ−Ｂ線による断面図のうち、絶縁基材より上側の部分に相当する部分の製造工程ごとの状態を示す図である。なお、実施の形態１と同様の部分については同じ符号を付し、詳細な説明は省略する。 3 and 4 are for explaining a method for manufacturing a power semiconductor device according to the second embodiment of the present invention, and FIG. 3 shows a configuration of the power semiconductor device manufactured by the present manufacturing method. FIG. 3 (a) is a plan view, and FIG. 3 (b) is a cross-sectional view taken along line BB in FIG. 3 (a). 4 (a) to 4 (g) are for explaining the manufacturing method, and in the cross-sectional view taken along the line BB in FIG. 3 (a), the portion corresponding to the portion above the insulating substrate. It is a figure which shows the state for every manufacturing process. In addition, the same code | symbol is attached | subjected about the part similar to Embodiment 1, and detailed description is abbreviate | omitted.
本実施の形態２にかかる電力用半導体装置の製造方法の説明の前に、本製造方法により得られた電力用半導体装置の基本構成について、図３を用いて説明する。電力用半導体装置１０は窒化ケイ素（Ｓｉ３Ｎ４）等のセラミックス板を絶縁基材４ｉとし、両面に銅（Ｃｕ）の電極４ｆ、４ｒをろう付け処理した３０ｍｍ×４０ｍｍ×１ｍｍｔの回路基板４と、回路基板４の回路面側の電極４ｆの所定領域に焼結接合材による接合層２を介して裏面が接合された９ｍｍ×９ｍｍ大の電力用半導体素子１とを備えている。 Prior to the description of the method for manufacturing the power semiconductor device according to the second embodiment, the basic configuration of the power semiconductor device obtained by this manufacturing method will be described with reference to FIG. The power semiconductor device 10 is a circuit board 4 of 30 mm × 40 mm × 1 mmt in which a ceramic plate such as silicon nitride (Si 3 N 4 ) is used as an insulating base 4i and copper (Cu) electrodes 4f and 4r are brazed on both sides. And a 9 mm × 9 mm large power semiconductor element 1 having a back surface bonded to a predetermined region of the electrode 4 f on the circuit surface side of the circuit board 4 via a bonding layer 2 made of a sintered bonding material.
つぎに、製造方法について図４を用いて説明する。
はじめに、回路基板４（上述したように、図では電極４ｆより上側部分のみ表示）を大気中で２００〜４００℃の温度で熱処理を行い、図４（ｂ）に示すように、電極４ｆの表面に、銅の酸化膜５を形成した。酸化膜５の組成（例えば、ＣｕＯあるいはＣｕ２Ｏのどちらであるか等）は問わないが、厚みは所定（２３０ｎｍ）以上に形成した。
Next, the manufacturing method will be described with reference to FIG.
First, the circuit board 4 (as shown above, only the portion above the electrode 4f is shown) is heat-treated in the atmosphere at a temperature of 200 to 400 ° C., and as shown in FIG. 4B, the surface of the electrode 4f Then, a copper oxide film 5 was formed. The composition of the oxide film 5 (for example, whether it is CuO or Cu 2 O, etc.) does not matter, but the thickness is formed to be a predetermined (230 nm) or more.
つぎに、図４（ｃ）に示すように、酸化膜５のうち、電力用半導体素子１を接合する領域（９ｍｍ×９ｍｍ）部分５Ｅのみ、部分的にエッチングして除去した。酸化膜５の除去方法は、化学処理、物理処理を問わない。また、部分エッチングのサイズ（除去領域）に関して、チップサイズよりも少し小さなサイズとしても良い。この場合、除去領域が電力用半導体素子１の設置領域からはみ出るというチップマウント時の位置ズレリスクを軽減することができる。なお、この場合、次の工程中の構造として、チップ直下に酸化膜が食い込む形となるが、その食い込み程度を制限することで、接合に関する問題も回避することができる。 Next, as shown in FIG. 4C, only the region (9 mm × 9 mm) portion 5E to which the power semiconductor element 1 is bonded is partially removed by etching. The removal method of the oxide film 5 may be any chemical treatment or physical treatment. Further, the size of the partial etching (removal region) may be a little smaller than the chip size. In this case, the positional deviation risk at the time of chip mounting that the removal region protrudes from the installation region of the power semiconductor element 1 can be reduced. In this case, as a structure in the next process, an oxide film bites in immediately below the chip. However, by limiting the biting level, a problem related to bonding can be avoided.
次に、図４（ｄ）に示すように、回路基板４のチップ接合領域に、ナノ銀（Ａｇ）粒子による焼結接合材のペースト２Ｐを印刷する。印刷サイズは、１０ｍｍ×１０ｍｍと、チップ設置領域を内包するように、チップサイズよりも意図的に大きくし、印刷位置ズレがあっても、マウント時にチップが印刷エリア外に出ないようにした。印刷厚みは、接合後の段階で、接合層厚みが１０〜１００μｍとなる厚みとした。 Next, as shown in FIG. 4 (d), a paste 2 </ b> P of a sintered bonding material made of nano silver (Ag) particles is printed on the chip bonding region of the circuit board 4. The print size is 10 mm × 10 mm, which is intentionally larger than the chip size so as to include the chip installation area, so that the chip does not come out of the print area when mounted even if there is a print position shift. The printing thickness was set to a thickness at which the bonding layer thickness was 10 to 100 μm at the stage after bonding.
印刷後、図４（ｅ）に示すように、電極４ｆの酸化膜５が部分エッチングされた領域を内包するように電力用半導体素子１をマウントする。そして、１０〜５０ＭＰａの圧力を掛けながら、２００〜４００℃に加熱することで、焼結銀による電力用半導体素子１と電極４ｆとの接合層２が形成される。 After printing, as shown in FIG. 4E, the power semiconductor element 1 is mounted so as to include a region where the oxide film 5 of the electrode 4f is partially etched. And the joining layer 2 of the semiconductor element 1 for electric power and the electrode 4f by sintered silver is formed by heating at 200-400 degreeC, applying a pressure of 10-50 Mpa.
上記のように電力用半導体素子１が接合された回路基板４に、（銅酸化膜）除去剤を用いて湿式超音波洗浄を実施し、回路基板４上の酸化膜５を除去する。この際、図４（ｆ）に示すように、酸化膜５上の各種異物、汚れも除去剤によって除去された除去酸化膜５Ｒと一緒に除去される。なお、ペースト２Ｐには、銅酸化膜還元剤が添加されているため、自然酸化膜程度の被膜であれば印刷後に還元される。そのため、大気中での熱処理工程を経ずに接合を行うと、チップ接合エリアからはずれた電極表面のうち、ペースト２Ｐが塗布された部分の酸化被膜が除去されてしまい、焼結銀との部分接合が進行するので、洗浄後にも無加圧の焼結銀が電極４ｆ上に残留してしまう。 The circuit board 4 to which the power semiconductor element 1 is bonded as described above is subjected to wet ultrasonic cleaning using a (copper oxide film) remover, and the oxide film 5 on the circuit board 4 is removed. At this time, as shown in FIG. 4F, various foreign matters and dirt on the oxide film 5 are also removed together with the removed oxide film 5R removed by the remover. In addition, since the copper oxide film reducing agent is added to the paste 2P, if it is a film about a natural oxide film, it is reduced after printing. Therefore, when bonding is performed without passing through a heat treatment step in the atmosphere, the oxide film on the portion of the electrode surface that is off the chip bonding area where the paste 2P is applied is removed, and the portion with the sintered silver is removed. Since joining proceeds, unpressurized sintered silver remains on the electrode 4f even after cleaning.
しかし、本実施の形態２にかかる電力用半導体装置の製造方法では、接合工程の前に、大気中（酸化雰囲気）での熱処理により、部分エッチングで除去された部分を取り巻く領域には、所定厚み以上の（銅）酸化膜５が形成されている。そのため、洗浄による酸化膜を除去する段階でも、接合領域の外側の部分では、ペースト２Ｐと電極４ｆとの間には、酸化膜５が介在する。つまり、焼結銀のうち、接合層２として寄与しない無加圧の部分（無加圧部２Ｒ）と電極４ｆの金属銅との間には酸化膜５が存在する。その結果、チップ直下から外れた印刷余り部、ニジミ部（無加圧部２Ｒ）は、湿式超音波洗浄により、図４（ｇ）のように除去酸化膜５Ｒと一緒に除去される。 However, in the method of manufacturing the power semiconductor device according to the second embodiment, the region surrounding the portion removed by the partial etching by the heat treatment in the atmosphere (oxidizing atmosphere) before the bonding step has a predetermined thickness. The above (copper) oxide film 5 is formed. Therefore, even in the stage of removing the oxide film by cleaning, the oxide film 5 is interposed between the paste 2P and the electrode 4f in the portion outside the bonding region. That is, the oxide film 5 exists between the non-pressurized part (non-pressurized part 2R) which does not contribute as the joining layer 2 among sintered silver, and the metal copper of the electrode 4f. As a result, the excess printing part and the blurring part (non-pressurized part 2R) deviated from immediately below the chip are removed together with the removed oxide film 5R as shown in FIG. 4G by wet ultrasonic cleaning.
洗浄後、回路基板４と図示しないベース板を還元性雰囲気リフローによりはんだ接合し、図示しないモジュール用ケースに取り付け、ワイヤーボンド結線し、樹脂による封止を行うことで、電力用半導体装置１０を作製した。この洗浄後の工程には、例えばワイヤーボンド結線の際の振動など、接合層２およびその周辺部分に衝撃が加わる工程があるが、酸化膜５と一緒に無加圧部２Ｒを除去しているため、脱離物は形成されなかった。 After cleaning, the circuit board 4 and a base plate (not shown) are solder-bonded by reductive atmosphere reflow, attached to a module case (not shown), wire-bonded, and sealed with resin to produce the power semiconductor device 10. did. In this post-cleaning process, for example, there is a process in which impact is applied to the bonding layer 2 and its peripheral part such as vibration during wire bond connection, but the non-pressurized part 2R is removed together with the oxide film 5. Therefore, no desorbed material was formed.
比較例として、熱処理による酸化膜形成工程を経ずに接合を行い、電力用半導体装置を作製した結果、ワイヤーボンド結線工程における振動にて、焼結銀の脱離物が検出された。 As a comparative example, joining was carried out without an oxide film forming step by heat treatment, and a power semiconductor device was produced. As a result, a detachment of sintered silver was detected by vibration in the wire bond connecting step.
以上のように、本実施の形態２にかかる電力用半導体装置の製造方法によれば、焼結性金属粒子を含有する接合材（ペースト２Ｐ）を用いて、電力用半導体素子１と回路基板４との接合を行う電力用半導体装置１０の製造方法であって、回路基板４の電極４ｆの表面に加熱によって酸化膜５を形成する工程と、前記酸化膜５のうち、電力用半導体素子１の設置領域に内包される領域（接合領域）の部分をエッチングによって除去する工程と、設置領域を網羅するように、設置領域の外周に所定の領域を残して設置領域を囲む領域に接合材（ペースト２Ｐ）を塗布する工程と、設置領域に電力用半導体素子１を設置する工程と、回路基板４と電力用半導体素子１との間に圧力をかけながら加熱して、焼結性金属粒子の焼結体（接合層２）を形成し、電力用半導体素子１と電極４ｆとを接合する工程と、酸化膜５を溶解する洗浄剤（酸化膜除去剤）を用い、焼結体のうち、電力用半導体素子１からはみ出た部分（無加圧部２Ｒ）を酸化膜５とともに除去する工程と、を順次実行するように構成したので、接合時に加圧されなかった焼結体（無加圧部２Ｒ）の残留を抑制できるので、高温に対応し、かつ信頼性が高い電力用半導体装置１０を得ることができる。 As described above, according to the manufacturing method of the power semiconductor device according to the second embodiment, the power semiconductor element 1 and the circuit board 4 are used using the bonding material (paste 2P) containing the sinterable metal particles. A method of manufacturing the power semiconductor device 10 for bonding to the surface of the electrode 4f of the circuit board 4 by heating, and the step of forming the power semiconductor element 1 of the oxide film 5 The step of removing the region (bonding region) included in the installation region by etching, and the bonding material (paste) in the region surrounding the installation region leaving the predetermined region on the outer periphery of the installation region so as to cover the installation region 2P), the step of installing the power semiconductor element 1 in the installation region, and heating while applying pressure between the circuit board 4 and the power semiconductor element 1 to sinter the sintered metal particles. Forming a bonded body (bonding layer 2) The step of joining the power semiconductor element 1 and the electrode 4f and a cleaning agent (oxide film removing agent) that dissolves the oxide film 5 are used. Since the step of removing the pressurizing portion 2R) together with the oxide film 5 is sequentially performed, the residual of the sintered body (no pressurizing portion 2R) that has not been pressurized at the time of bonding can be suppressed. And the power semiconductor device 10 with high reliability can be obtained.
＜接合材除去効果評価試験＞
つぎに、上述した各製造方法における不要な焼結銀を除去する効果を検証するため、酸化膜５の厚みをパラメータとする焼結銀（接合材）除去効果評価試験を行った。
<Bonding material removal effect evaluation test>
Next, in order to verify the effect of removing unnecessary sintered silver in each of the manufacturing methods described above, a sintered silver (bonding material) removal effect evaluation test using the thickness of the oxide film 5 as a parameter was performed.
試験は、以下のようにして行った。
回路基板４単位をサンプルとし、サンプルごとに、大気中での温度と保持時間を変えて電極４ｆ上に厚みの異なる酸化膜５を形成する。そして、各サンプルの電極４ｆ上に同じ条件（ペースト２Ｐ塗布、乾燥（１３０℃、３０分）、接合（１０ＭＰａ、２５０℃、５分））で焼結銀を形成する。電極４ｆ上に焼結銀が形成されたサンプルに対して酸化膜除去洗浄液を用いた超音波洗浄により、焼結銀を除去し、最終的に焼結銀が残留したか否かを評価する。
The test was conducted as follows.
The circuit board 4 unit is used as a sample, and the oxide film 5 having a different thickness is formed on the electrode 4f by changing the temperature and holding time in the atmosphere for each sample. Then, sintered silver is formed on the electrode 4f of each sample under the same conditions (application of paste 2P, drying (130 ° C., 30 minutes), bonding (10 MPa, 250 ° C., 5 minutes)). The sample in which the sintered silver is formed on the electrode 4f is subjected to ultrasonic cleaning using an oxide film removing cleaning solution to remove the sintered silver and finally evaluate whether or not the sintered silver remains.
図４と図５は、それぞれ本評価結果を表形式で示すものであり、１段目はサンプル番号、２段目の上段は酸化膜を形成する際の処理条件、下段は形成された酸化膜の厚みを示す。そして、３段目はサンプルの工程ごとの状態を示す写真（平面）で、上段がペースト印刷前の状態、中断がペースト印刷後の状態、下段が酸化膜除去（洗浄）後の状態を示す。そして４段目が結果である。なお、酸化膜５の厚みは、ＳＥＲＡ法（Sequential Electrochemical Reduction Analysis：連続電気化学還元法）により算出した。 FIG. 4 and FIG. 5 show the results of the evaluation in a tabular format. The first stage is the sample number, the upper stage is the processing conditions for forming the oxide film, and the lower stage is the formed oxide film. The thickness of is shown. The third row is a photograph (plane) showing the state of each process of the sample, the upper row shows the state before paste printing, the interruption is the state after paste printing, and the lower row shows the state after oxide film removal (cleaning). The fourth row is the result. The thickness of the oxide film 5 was calculated by the SERA method (Sequential Electrochemical Reduction Analysis).
図４と図５に示すように、酸化膜５の厚みが１２０ｎｍ以下の場合（サンプルＳＰ−１〜ＳＰ−２）は、洗浄後に接合材が残留し、酸化膜の厚みが２３０ｎｍ以上の場合は（サンプルＳＰ−３〜ＳＰ−７）接合材が除去できていることがわかった。つまり、酸化膜５の厚みを２３０ｎｍ以上にしておけば、還元剤が添加されたペースト２Ｐが塗布されても金属部分と焼結銀との間に介在（残留）し、洗浄工程で焼結銀を除去できることが分かった。 As shown in FIGS. 4 and 5, when the thickness of the oxide film 5 is 120 nm or less (samples SP-1 to SP-2), the bonding material remains after cleaning, and the thickness of the oxide film is 230 nm or more. (Samples SP-3 to SP-7) It was found that the bonding material was removed. That is, if the thickness of the oxide film 5 is set to 230 nm or more, even if the paste 2P to which the reducing agent is added is applied, it is interposed (residual) between the metal part and the sintered silver, and the sintered silver is removed in the cleaning process. It was found that can be removed.
なお、上記各実施の形態１あるいは２では、電極４ｆの接合領域を除く全体に、酸化膜５を形成した例について説明した。しかし、上述したように、無加圧部２Ｒ部分を除去できればいいのであって、ペースト２Ｐの塗布領域あるいは塗布される可能性のある領域以外まで、酸化膜５が形成されている必要はない。したがって、酸化膜５を形成する領域としては、接合領域を縁取り、ペースト２Ｐの塗布範囲である枠状の領域であれば事足りる。 In each of the first and second embodiments, the example in which the oxide film 5 is formed on the entire surface excluding the bonding region of the electrode 4f has been described. However, as described above, it suffices if the non-pressurized portion 2R portion can be removed, and the oxide film 5 does not have to be formed except for the application region of the paste 2P or the region where the paste 2P may be applied. Therefore, the region for forming the oxide film 5 is sufficient if it is a frame-like region that borders the bonding region and is the application range of the paste 2P.
以上のように、本実施の形態１あるいは２にかかる電力用半導体装置の製造方法によれば、焼結性金属粒子を含有する接合材（ペースト２Ｐ）を用いて、電力用半導体素子１と回路基板４との接合を行う電力用半導体装置１０の製造方法であって、回路基板４の電極４ｆの表面のうち、電力用半導体素子１の設置領域の外周に所定の領域を残して前記設置領域を囲む第一領域から、設置領域に内包される（設置領域と同等以下の）第二領域を除いた領域に、加熱によって酸化膜５を形成する工程と、設置領域を網羅するように、第一領域内に接合材（ペースト２Ｐ）を塗布する工程と、設置領域に、電力用半導体素子１を設置する工程と、回路基板４と電力用半導体素子１との間に圧力をかけながら加熱して、焼結性金属粒子の焼結体（接合層２）を形成し、電力用半導体素子１と電極４ｆとを接合する工程と、酸化膜５を溶解する洗浄剤（酸化膜除去剤）を用い、焼結体のうち、電力用半導体素子１からはみ出た部分（無加圧部２Ｒ）を酸化膜５とともに除去する工程と、を順次実行するように構成したので、接合時に加圧されなかった焼結体（無加圧部２Ｒ）の残留を抑制できるので、高温に対応し、かつ信頼性が高い電力用半導体装置１０を得ることができる。 As described above, according to the method for manufacturing the power semiconductor device according to the first or second embodiment, the power semiconductor element 1 and the circuit are formed using the bonding material (paste 2P) containing the sinterable metal particles. A method of manufacturing a power semiconductor device 10 for bonding to a substrate 4, wherein the installation region is left on the surface of the electrode 4 f of the circuit substrate 4, leaving a predetermined region on the outer periphery of the installation region of the power semiconductor element 1. A step of forming the oxide film 5 by heating in a region excluding a second region (equal to or less than the installation region) included in the installation region from the first region surrounding the A process of applying a bonding material (paste 2P) in one area, a process of installing the power semiconductor element 1 in the installation area, and heating while applying pressure between the circuit board 4 and the power semiconductor element 1 Sintered body of sinterable metal particles (joining 2), a step of bonding the power semiconductor element 1 and the electrode 4f, and a cleaning agent (oxide film removing agent) for dissolving the oxide film 5, and from the power semiconductor element 1 in the sintered body. The step of removing the protruding portion (non-pressurized portion 2R) together with the oxide film 5 is sequentially executed, so that the remaining sintered body (non-pressurized portion 2R) that has not been pressurized during bonding is removed. Since it can suppress, the semiconductor device 10 for electric power corresponding to high temperature and having high reliability can be obtained.
とくに、電極４ｆが銅であり、その酸化膜５の厚みが２３０ｎｍ以上になるように構成したので、還元剤が添加されたペースト２Ｐが塗布されても、金属部分と焼結銀との間に酸化膜５が介在（残留）し、洗浄工程で焼結銀を容易に除去できる。 In particular, since the electrode 4f is made of copper and the thickness of the oxide film 5 is 230 nm or more, even if the paste 2P to which a reducing agent is added is applied, it is between the metal portion and the sintered silver. The oxide film 5 is interposed (residual), and the sintered silver can be easily removed in the cleaning process.
なお、上記各実施の形態においては、電力用半導体素子１には、シリコンウエハを基材とした一般的な素子でも良いが、本発明においては炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）系材料、またはダイヤモンドといったシリコンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料を用い、高耐圧および高温動作が可能な半導体素子を用いた場合に、特に顕著な効果が現れる。特に炭化ケイ素を用いた電力用半導体素子に好適に用いることができる。 In each of the above embodiments, the power semiconductor element 1 may be a general element based on a silicon wafer, but in the present invention, silicon carbide (SiC) or gallium nitride (GaN) -based material. In particular, when a so-called wide band gap semiconductor material having a wider band gap than silicon, such as diamond, is used, and a semiconductor element capable of high breakdown voltage and high temperature operation is used, a particularly remarkable effect appears. In particular, it can be suitably used for a power semiconductor element using silicon carbide.
ワイドバンドギャップ半導体によって形成されたスイッチング素子や整流素子は、ケイ素で形成された素子よりも電力損失が低いため、スイッチング素子や整流素子における高効率化が可能であり、ひいては、電力用半導体装置の高効率化が可能となる。さらに、耐電圧性が高く、許容電流密度も高いため、スイッチング素子や整流素子の小型化が可能であり、これら小型化されたスイッチング素子や整流素子を用いることにより、電力用半導体装置も小型化が可能となる。また耐熱性が高いので、高温動作が可能であり、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化も可能となるので、電力用半導体装置の一層の小型化が可能になる。 Since switching elements and rectifying elements formed of wide band gap semiconductors have lower power loss than elements formed of silicon, it is possible to increase the efficiency of switching elements and rectifying elements. High efficiency can be achieved. In addition, because it has high voltage resistance and high allowable current density, it is possible to reduce the size of switching elements and rectifier elements. By using these reduced switching elements and rectifier elements, power semiconductor devices can also be reduced in size. Is possible. In addition, since the heat resistance is high, it is possible to operate at a high temperature, and it is possible to reduce the size of the heat dissipating fins of the heat sink and the air cooling of the water-cooled portion, thereby further reducing the size of the power semiconductor device.
その際、本発明による効果を発揮することで、ワイドバンドギャップ半導体の特性を活かすことができるようになる。なお、複数の半導体素子全てが、ワイドバンドギャップ半導体によって形成されていても、一部の半導体素子がワイドバンドギャップ半導体によって形成されていてもよい。 At that time, the characteristics of the wide band gap semiconductor can be utilized by exhibiting the effects of the present invention. Note that all of the plurality of semiconductor elements may be formed of a wide band gap semiconductor, or some of the semiconductor elements may be formed of a wide band gap semiconductor.
１：電力用半導体素子、 ２：接合層、 ２Ｐ：ペースト、 ２Ｒ：無加圧部、
３：被覆膜、 ４：回路基板、 ４ｆ：電極（回路面側）、 ４ｉ：絶縁基材、
４ｒ：電極（放熱面側）、 ５：酸化膜、 ５Ｅ：（電力用半導体素子を接合する領域部分の）酸化膜、 ５Ｒ：除去酸化膜、 １０：電力用半導体装置。
1: power semiconductor element, 2: bonding layer, 2P: paste, 2R: no pressure part,
3: coating film, 4: circuit board, 4f: electrode (circuit surface side), 4i: insulating base material,
4r: Electrode (heat radiation surface side), 5: Oxide film, 5E: Oxide film (in the region where the power semiconductor element is joined), 5R: Removal oxide film, 10: Power semiconductor device.
Claims (4)
前記回路基板の電極の表面のうち、前記電力用半導体素子の設置領域の外周に所定の領域を残して前記設置領域を囲む第一領域から、前記設置領域に内包される第二領域を除いた領域に、加熱によって酸化膜を形成する工程と、
前記設置領域を網羅するように、前記第一領域内に前記接合材を塗布する工程と、
前記設置領域に前記電力用半導体素子を設置する工程と、
前記回路基板と前記電力用半導体素子との間に圧力をかけながら加熱して、前記焼結性金属粒子の焼結体を形成し、前記電力用半導体素子と前記電極とを接合する工程と、
前記酸化膜を溶解する洗浄剤を用い、前記焼結体のうち、前記電力用半導体素子からはみ出た部分を前記酸化膜とともに除去する工程と、
を順次実行することを特徴とする電力用半導体装置の製造方法。 Using a bonding material containing sinterable metal particles, a method for manufacturing a power semiconductor device for bonding a power semiconductor element and a circuit board,
Of the surface of the electrode of the circuit board, the second region included in the installation region is excluded from the first region surrounding the installation region leaving a predetermined region on the outer periphery of the installation region of the power semiconductor element. Forming an oxide film by heating in the region;
Applying the bonding material in the first region so as to cover the installation region;
Installing the power semiconductor element in the installation area;
Heating while applying pressure between the circuit board and the power semiconductor element to form a sintered body of the sinterable metal particles, and joining the power semiconductor element and the electrode;
Using a cleaning agent that dissolves the oxide film, and removing the portion of the sintered body that protrudes from the power semiconductor element together with the oxide film;
Are sequentially executed. A method for manufacturing a power semiconductor device.
前記酸化膜の厚みが２３０μｍ以上であることを特徴とする請求項１に記載の電力用半導体装置の製造方法。 The electrode is made of copper;
The method for manufacturing a power semiconductor device according to claim 1, wherein the oxide film has a thickness of 230 μm or more.
前記第二領域に貴金属の被覆膜を形成してから前記加熱を行うことを特徴とする請求項１または２に記載の電力用半導体装置の製造方法。 In the step of forming the oxide film,
The method for manufacturing a power semiconductor device according to claim 1, wherein the heating is performed after a noble metal coating film is formed in the second region.
前記第一領域の全域に前記酸化膜を形成したのち、形成した酸化膜のうち、前記第二領域の部分をエッチングにより除去することを特徴とする請求項１または２に記載の電力用半導体装置の製造方法。 In the step of forming the oxide film,
3. The power semiconductor device according to claim 1, wherein after the oxide film is formed over the entire area of the first region, a portion of the second region of the formed oxide film is removed by etching. 4. Manufacturing method.
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