JP2011086821A - Semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor device, and method of manufacturing the same Download PDF

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JP2011086821A
JP2011086821A JP2009239497A JP2009239497A JP2011086821A JP 2011086821 A JP2011086821 A JP 2011086821A JP 2009239497 A JP2009239497 A JP 2009239497A JP 2009239497 A JP2009239497 A JP 2009239497A JP 2011086821 A JP2011086821 A JP 2011086821A
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thermistor
electrode
circuit pattern
semiconductor chip
semiconductor device
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Takatoshi Kobayashi
孝敏 小林
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/191—Disposition
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    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability and inexpensive semiconductor device having a thermistor, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device is high in reliability and low in cost, as compared with the case of soldering in a nitrogen atmosphere requiring flux treatment, by fixing an electrode 14 constituting a thermistor 13 to a circuit pattern 5 with silver paste 12. The method of manufacturing the same is also provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、半導体チップの温度を検出するサーミスタを有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device having a thermistor for detecting the temperature of a semiconductor chip and a method for manufacturing the same.

半導体モジュール（例えば、ＩＧＢＴモジュール）に搭載される半導体チップの温度をサーミスタで検出し半導体チップが過熱したとき、半導体モジュールの動作を停止させたり半導体モジュールに流れる電流を絞ったりして、半導体チップの破壊を防止している。   When the temperature of a semiconductor chip mounted on a semiconductor module (for example, an IGBT module) is detected by a thermistor and the semiconductor chip is overheated, the operation of the semiconductor module is stopped or the current flowing through the semiconductor module is reduced. Prevents destruction.

図７は、従来のサーミスタを有する半導体モジュールの要部断面図である。この半導体モジュールは、銅ベース１と絶縁基板７の裏面が水素（Ｈ2）の還元雰囲気ではんだ付けされ、この絶縁基板７を構成する回路パターン５と半導体チップ９が水素の還元雰囲気ではんだ付けされ、半導体チップ９の近くにサーミスタ２３と回路パターン５が大気中または窒素（Ｎ2）雰囲気ではんだ付けされている。 FIG. 7 is a cross-sectional view of a main part of a semiconductor module having a conventional thermistor. In this semiconductor module, the copper base 1 and the back surface of the insulating substrate 7 are soldered in a hydrogen (H 2 ) reducing atmosphere, and the circuit pattern 5 and the semiconductor chip 9 constituting the insulating substrate 7 are soldered in a hydrogen reducing atmosphere. The thermistor 23 and the circuit pattern 5 are soldered in the air or in a nitrogen (N 2 ) atmosphere near the semiconductor chip 9.

このサーミスタ２３は酸化物で形成されているため、水素の還元雰囲気ではんだ付けするとサーミスタ２３の機能が消失する。そのため、サーミスタ２３の電極２４と回路パターン５の電極１１とのはんだ付けは大気中または窒素雰囲気で行なわれる。しかし、大気中または窒素雰囲気でのはんだ付けではフラックス処理やはんだ付けした後のフラックスを除去するための洗浄工程が必要となる。   Since the thermistor 23 is formed of an oxide, the function of the thermistor 23 disappears when soldering is performed in a hydrogen reducing atmosphere. Therefore, soldering of the electrode 24 of the thermistor 23 and the electrode 11 of the circuit pattern 5 is performed in the air or in a nitrogen atmosphere. However, soldering in the air or in a nitrogen atmosphere requires a flux process and a cleaning process for removing the flux after soldering.

一方、銅ベース１と絶縁基板７、絶縁基板７と半導体チップ９は、フラックス処理が不要な水素の還元雰囲気でのはんだ付けとしている。
尚、図中の符号の２は銅ベース１と導電膜３（例えば、銅箔など）を固着するはんだ、３は絶縁基板７の裏面側の導電膜、４はセラミック板、６は回路パターン５の一つである電極、７は回路パターン５とセラミック板４と導電膜３で構成される絶縁基板、８は半導体チップ９の裏面と回路パターン５を固着するはんだ、１０は半導体チップ９の表面電極と電極６を接続するボンディングワイヤ、１１はサーミスタ２３を固着する回路パターン５の一つである電極、１５は電極６と端子ケース１７の端子１８を接続するボンディングワイヤ、１６は電極１１と端子ケース１７の端子１８を接続するボンディングワイヤ、１７は端子ケース、１８は端子ケース１７の端子、１９は端子ケース１７の絶縁性の外枠であるケース、２０はゲル（例えば、シリコーンゲルなど）、２１は端子ケース１７を覆うフタ、２２はサーミスタ２３と回路パターン５を接続するはんだ、２４はサーミスタ２３の電極である。 On the other hand, the copper base 1 and the insulating substrate 7, and the insulating substrate 7 and the semiconductor chip 9 are soldered in a hydrogen reducing atmosphere that does not require flux treatment.
In the figure, reference numeral 2 denotes solder for fixing the copper base 1 and the conductive film 3 (for example, copper foil), 3 denotes a conductive film on the back side of the insulating substrate 7, 4 denotes a ceramic plate, and 6 denotes a circuit pattern 5. , 7 is an insulating substrate composed of the circuit pattern 5, the ceramic plate 4 and the conductive film 3, 8 is a solder for fixing the back surface of the semiconductor chip 9 and the circuit pattern 5, and 10 is a surface of the semiconductor chip 9. Bonding wire for connecting the electrode 6 and the electrode 6, 11 is an electrode which is one of the circuit patterns 5 for fixing the thermistor 23, 15 is a bonding wire for connecting the electrode 6 and the terminal 18 of the terminal case 17, and 16 is the electrode 11 and the terminal Bonding wires for connecting the terminals 18 of the case 17, 17 is a terminal case, 18 is a terminal of the terminal case 17, 19 is an insulating outer frame of the terminal case 17, and 20 is a gel (for example, , Silicone gel), 21 the lid that covers the terminal case 17, 22 a solder which connects the thermistor 23 and the circuit pattern 5, 24 is an electrode of the thermistor 23.

特許文献１において、半導体チップの温度を検出するためにサーミスタを回路パターンにはんだ付けした半導体装置が記載されている。
特許文献２において、半導体チップの上面に熱伝導の良い絶縁層を介してサーミスタを固定し、このサーミスタの対向する側面に銀ペーストなどの導電性の接着剤を介してリード線であるワイヤの一端を取り付けた半導体装置が記載されている。 Patent Document 1 describes a semiconductor device in which a thermistor is soldered to a circuit pattern in order to detect the temperature of a semiconductor chip.
In Patent Document 2, a thermistor is fixed to the upper surface of a semiconductor chip via an insulating layer having good thermal conductivity, and one end of a wire that is a lead wire is attached to the opposite side surface of the thermistor via a conductive adhesive such as silver paste. Is described.

特許文献３において、半導体チップと絶縁基板を水素の還元雰囲気ではんだ付けすることが記載されている。   Patent Document 3 describes soldering a semiconductor chip and an insulating substrate in a hydrogen reducing atmosphere.

特開２００２−７６２３６号公報（図３、段落０００３〜段落０００９参照）JP 2002-76236 A (see FIG. 3, paragraphs 0003 to 0009) 実開平２−８１０５５号公報（３頁、第５図参照）Japanese Utility Model Publication No. 2-81055 (see page 3, Fig. 5) 特許第３８０９８０６号公報（段落００２５、段落００２７参照）Japanese Patent No. 3809806 (see paragraphs 0025 and 0027)

図７で説明したように、サーミスタ２３を大気中または窒素雰囲気ではんだ付けするときにフラックス処理が必要となり、はんだ付けした後で、フラックスを洗浄する工程が必要となる。そのため製造コストが増大し、また洗浄工程が不十分な場合には製品の信頼性が低下する。   As described with reference to FIG. 7, a flux process is required when soldering the thermistor 23 in the air or in a nitrogen atmosphere, and a process of cleaning the flux after soldering is required. As a result, the manufacturing cost increases, and the reliability of the product decreases when the cleaning process is insufficient.

さらに、サーミスタ２３のはんだ付け工程で、すでにはんだ付けされた銅ベース１と絶縁基板７、絶縁基板７と半導体チップ９のそれぞれの固化したはんだ２、８が再溶融してはんだのはみ出しが生じて製品不良を発生させ、製造コストを増大させる。   Further, in the soldering process of the thermistor 23, the already soldered copper base 1 and the insulating substrate 7, and the solidified solders 2 and 8 of the insulating substrate 7 and the semiconductor chip 9 are remelted, and the solder protrudes. Generate product defects and increase manufacturing costs.

特許文献１、３に記載の半導体装置の場合もサーミスタをはんだで固着するので、図７で説明した課題が生じる。
また、特許文献１、３では、銀ペーストでサーミスタを固着することは記載されていない。 In the case of the semiconductor devices described in Patent Documents 1 and 3, since the thermistor is fixed with solder, the problem described with reference to FIG. 7 occurs.
Patent Documents 1 and 3 do not describe fixing the thermistor with a silver paste.

特許文献２に記載の半導体装置では、サーミスタを半導体チップに絶縁層を介して固着する工程と、図８に示すように、リード線になるワイヤをサーミスタの両端に銀ペーストで固着する工程が必要になる。このワイヤのサーミスタへの結線作業では、銀ペーストの硬化に１５０℃前後で１時間〜２時間程度の時間が必要となり、またワイヤの端部がサーミスタの側面に位置するように長時間保持しておかなければならない。そのため、この結線作業は非常に厄介であるとともに、作業性が悪い。そのために、製造コストが増大する。   The semiconductor device described in Patent Document 2 requires a step of fixing the thermistor to the semiconductor chip via an insulating layer and a step of fixing a wire to be a lead wire to both ends of the thermistor with silver paste as shown in FIG. become. This wire connection to the thermistor requires about 1 to 2 hours at around 150 ° C to cure the silver paste, and hold the wire for a long time so that the end of the wire is located on the side of the thermistor. I have to leave. Therefore, this connection work is very troublesome and the workability is poor. Therefore, the manufacturing cost increases.

また、特許文献２では、サーミスタの両側面に形成された電極を銀ペーストで回路パターンに固定するとことでサーミスタと回路パターンを固着することについては記載されていない。   Patent Document 2 does not describe fixing the thermistor and the circuit pattern by fixing the electrodes formed on both sides of the thermistor to the circuit pattern with silver paste.

この発明の目的は、前記の課題を解決して、サーミスタを有し低コストで信頼性が高い半導体装置およびその製造方法を提供することにある。   An object of the present invention is to solve the above-described problems and provide a semiconductor device having a thermistor and high reliability at a low cost and a manufacturing method thereof.

前記の目的を達成するために、特許請求の範囲の請求項１記載の発明によれば、絶縁基板を介して半導体チップの温度を検出するサーミスタを有する半導体装置において、回路パターンを構成する前記絶縁基板と、前記回路パターンにはんだで固着される前記半導体チップと、前記回路パターンに銀ペーストで電極が固着されるサーミスタとを具備する構成とするとよい。   In order to achieve the above object, according to the first aspect of the present invention, in the semiconductor device having the thermistor for detecting the temperature of the semiconductor chip through the insulating substrate, the insulation constituting the circuit pattern is provided. The semiconductor chip may be fixed to the circuit pattern with solder, and the thermistor with the electrode fixed to the circuit pattern with silver paste.

特許請求の範囲の請求項２記載の発明によれば、絶縁基板を介して半導体チップの温度を検出するサーミスタを有する半導体装置の製造方法において、前記絶縁基板を構成する回路パターンに前記半導体チップを水素の還元雰囲気ではんだ付けする工程と、前記回路パターンに前記サーミスタの対向する側面に形成された電極を銀ペーストで固着する工程と、を含む製造方法とするとよい。   According to a second aspect of the present invention, in a method of manufacturing a semiconductor device having a thermistor that detects the temperature of a semiconductor chip through an insulating substrate, the semiconductor chip is formed in a circuit pattern that constitutes the insulating substrate. It is preferable that the manufacturing method includes a step of soldering in a hydrogen reducing atmosphere and a step of fixing an electrode formed on a side surface of the thermistor facing the circuit pattern with a silver paste.

この発明によれば、サーミスタを回路パターンに固着する場合に、銀ペーストを用いるために、はんだの場合に必要となるフラックス処理や洗浄工程が不要となり、製造コストを低減することができる。   According to the present invention, since the silver paste is used when the thermistor is fixed to the circuit pattern, the flux processing and the cleaning process required in the case of solder are not required, and the manufacturing cost can be reduced.

また、銀ペーストでの固着では、はんだが溶ける温度まで銀ペーストの温度が上昇しないので、はんだ付けの場合に生じたはんだの再溶融によるはんだのはみ出しという現象がなくなり、良品率が向上して、製造コストを低減することができる。   In addition, in fixing with silver paste, the temperature of the silver paste does not rise to the temperature at which the solder melts, so there is no phenomenon of solder overflow due to remelting of the solder that occurred during soldering, and the yield rate is improved. Manufacturing cost can be reduced.

また、銀ペーストでの固着のため、フラックス処理が不要となり、大気中または窒素雰囲気でのはんだ付けに比べて製品の信頼性を向上させることができる。
また、特許文献２に記載されている半導体装置では、サーミスタの半導体チップへの固定とリード線となるワイヤのサーミスタ端部への固定というの２工程が必要になるが、本発明の半導体装置ではサーミスタの電極の回路パターンへの固着という１工程で済み、製造コストを低減することができる。 In addition, since it is fixed with silver paste, flux treatment is unnecessary, and the reliability of the product can be improved as compared with soldering in the air or in a nitrogen atmosphere.
In addition, in the semiconductor device described in Patent Document 2, two steps of fixing the thermistor to the semiconductor chip and fixing the wire serving as the lead wire to the end of the thermistor are necessary. One step of fixing the thermistor electrode to the circuit pattern is sufficient, and the manufacturing cost can be reduced.

つまり、本発明では、サーミスタの端子を銀ペーストで回路パターンに固着すると共に、製造の全工程でフラックス処理を不要とすることができるため、製造コストの低減と製品の信頼性の向上を図ることができる。   In other words, in the present invention, the terminal of the thermistor is fixed to the circuit pattern with silver paste, and flux processing is not necessary in the entire manufacturing process, thereby reducing the manufacturing cost and improving the reliability of the product. Can do.

この発明の第１実施例の半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device of 1st Example of this invention. この発明の半導体装置内部の配置図であり、（ａ）は拡大平面図、（ｂ）はサーミスタの固着状態を示す拡大断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout view inside a semiconductor device according to the present invention, where FIG. この発明の第２実施例の半導体装置の要部製造工程断面図である。It is principal part manufacturing process sectional drawing of the semiconductor device of 2nd Example of this invention. 図３に続く、この発明の第２実施例の半導体装置の要部製造工程断面図である。FIG. 4 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 3; 図４に続く、この発明の第２実施例の半導体装置の要部製造工程断面図である。FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 4. 図５に続く、この発明の第２実施例の半導体装置の要部製造工程断面図である。FIG. 6 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 5. 従来のサーミスタを有する半導体モジュールの要部断面図である。It is principal part sectional drawing of the semiconductor module which has the conventional thermistor. 特許文献２に示されるサーミスタの構成図である。10 is a configuration diagram of a thermistor disclosed in Patent Document 2. FIG.

実施の形態を以下の実施例で説明する。尚、図７の従来構造と同一の部位には同一の符号を付した。   Embodiments will be described in the following examples. In addition, the same code | symbol was attached | subjected to the site | part same as the conventional structure of FIG.

図１は、この発明の第１実施例の半導体装置の要部断面図である。ここでは半導体装置として半導体モジュールを例として挙げた。
この発明の半導体装置は、銅ベース１と、この銅ベース１上にはんだ２で固着する絶縁基板７と、この絶縁基板７上に形成された回路パターン５にはんだ８で固着する半導体チップ９と、回路パターン１１に銀ペースト１２で電極１４が固着するサーミスタ１３と、これらを収納する端子ケースと、半導体チップ９の図示しない表面電極（エミッタ電極パッド、ゲートパッド）と回路パターン５の一つである電極６を接続するボンディングワイヤ１０（図の右側のボンディングワイヤ１０は図示しない別の電極６と接続する）と、電極６と端子ケース１７の端子１８と接続するボンディングワイヤ１５と、サーミスタ１３の電極１４が固着する電極１１と端子ケース１７の端子１８とを接続するボンディングワイヤ１６と、端子ケース１７内を充填するゲル２０と、端子ケース１７を塞ぐフタ２１とで構成される。 FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. Here, a semiconductor module is taken as an example of the semiconductor device.
The semiconductor device of the present invention includes a copper base 1, an insulating substrate 7 fixed on the copper base 1 with solder 2, and a semiconductor chip 9 fixed on a circuit pattern 5 formed on the insulating substrate 7 with solder 8. One of the thermistor 13 in which the electrode 14 is fixed to the circuit pattern 11 with the silver paste 12, the terminal case for storing these, the surface electrode (emitter electrode pad, gate pad) (not shown) of the semiconductor chip 9, and the circuit pattern 5. A bonding wire 10 for connecting a certain electrode 6 (the bonding wire 10 on the right side of the figure is connected to another electrode 6 not shown), a bonding wire 15 for connecting the electrode 6 and the terminal 18 of the terminal case 17, and a thermistor 13 A bonding wire 16 for connecting the electrode 11 to which the electrode 14 is fixed and the terminal 18 of the terminal case 17; Composed of a gel 20 that fills a lid 21 for closing the terminal case 17.

尚、前記の端子ケース１７とは、ここでは端子１８と絶縁性の枠体であるケース１９が一体化しているものをいう。また、本サーミスタ１３は、サーミスタ１３の両端の対向する側面に形成された電極１４を回路パターン５（１１）に導電性接着剤（はんだや銀ペースト）で直接固着できる構造であり、面実装型のサーミスタであると言える。この構造はサーミスタの電極１４と回路パターン５の間を結ぶリード線（ピンやワイヤなど）が不要な構造である。   Here, the terminal case 17 means that the terminal 18 and the case 19 which is an insulating frame are integrated. The thermistor 13 has a structure in which the electrodes 14 formed on the opposite side surfaces of both ends of the thermistor 13 can be directly fixed to the circuit pattern 5 (11) with a conductive adhesive (solder or silver paste). It can be said that this is a thermistor. This structure is a structure that does not require a lead wire (pin, wire or the like) connecting the electrode 14 of the thermistor and the circuit pattern 5.

一方、特許文献２に記載のサーミスタは、図８に示すように、サーミスタの両端にワイヤを銀ペーストで接続したリード線付きサーミスタであり、半導体チップとの固着はサーミスタ本体で行う。従って、この構造は本発明で用いたサーミスタ１３とは異なる構造である。   On the other hand, the thermistor described in Patent Document 2, as shown in FIG. 8, is a thermistor with lead wires in which wires are connected to both ends of the thermistor with silver paste, and is fixed to the semiconductor chip by the thermistor body. Therefore, this structure is different from the thermistor 13 used in the present invention.

図１において、回路パターン５の一つである電極１１とサーミスタ１３の電極１４を銀ペースト１２で固着するとき、はんだ付けで必要となるフラックス処理とその後の洗浄工程は不要となる。その結果、はんだ付けの場合に比べて、工程数が減少し製造コストを低減することができ、さらにフラックス処理が不要なことから製品の信頼性を向上させることができる。   In FIG. 1, when the electrode 11 which is one of the circuit patterns 5 and the electrode 14 of the thermistor 13 are fixed with the silver paste 12, the flux treatment required for soldering and the subsequent cleaning process are not required. As a result, compared with the case of soldering, the number of processes can be reduced, the manufacturing cost can be reduced, and the reliability of the product can be improved because the flux treatment is unnecessary.

また、サーミスタの電極１４と回路パターン５（電極１１）を導電性接着剤である銀ペースト１２で固着することで、サーミスタの固定とサーミスタと回路パターンの間の導通を同時にできるので、特許文献２に記載のサーミスタの場合に比べて組み立て工数を減らすことができる。その結果、製造コストを低減することができる。
図２は、この発明の半導体装置内部の配置図であり、同図（ａ）は拡大平面図、同図（ｂ）はサーミスタの固着状態を示す拡大断面図である。図２に示すように、半導体チップ９と半導体チップ９の近くにサーミスタ１３が配置されている。半導体チップ９ははんだ８で回路パターン５に固着し、サーミスタ１３の電極１４は回路パターン５の一つである電極１１に銀ペースト１２で固着されている。 Further, by fixing the thermistor electrode 14 and the circuit pattern 5 (electrode 11) with the silver paste 12 as a conductive adhesive, the thermistor can be fixed and the conduction between the thermistor and the circuit pattern can be performed simultaneously. The number of assembly steps can be reduced compared to the case of the thermistor described in. As a result, the manufacturing cost can be reduced.
2A and 2B are layout views inside the semiconductor device of the present invention, where FIG. 2A is an enlarged plan view and FIG. 2B is an enlarged cross-sectional view showing a fixed state of the thermistor. As shown in FIG. 2, the thermistor 13 is disposed near the semiconductor chip 9 and the semiconductor chip 9. The semiconductor chip 9 is fixed to the circuit pattern 5 with the solder 8, and the electrode 14 of the thermistor 13 is fixed to the electrode 11 that is one of the circuit patterns 5 with the silver paste 12.

本発明の半導体装置の一例である半導体モジュールでは、多数の半導体チップ９がそれぞれ違ったタイミングで動作する。サーミスタ１３を１個の半導体チップ９に固定した場合には、サーミスタ１３を付けない半導体チップ９が動作しているときの温度は、熱の伝導通路である絶縁基板７とサーミスタ１３を固定した半導体チップ９（つまり、シリコン板）を通して検出されることになる。熱伝導率の低いシリコン板を通して、温度を検出されることになるので、検出される温度はかなり低くなる。   In a semiconductor module which is an example of the semiconductor device of the present invention, a large number of semiconductor chips 9 operate at different timings. When the thermistor 13 is fixed to one semiconductor chip 9, the temperature when the semiconductor chip 9 without the thermistor 13 is operating is a semiconductor in which the insulating substrate 7 that is a heat conduction path and the thermistor 13 are fixed. It is detected through the chip 9 (that is, a silicon plate). Since the temperature is detected through the silicon plate having a low thermal conductivity, the detected temperature becomes considerably low.

これを改善するために、半導体モジュールのような多数の半導体チップ９が搭載された場合は、半導体チップ９が固着する熱伝導率の高い絶縁基板７（回路パターン５）の温度を検出することで、半導体チップ９の温度を検出している。但し、絶縁基板７の温度と半導体チップ９の温度の相関を予め把握しておく必要がある。   In order to improve this, when a large number of semiconductor chips 9 such as semiconductor modules are mounted, the temperature of the insulating substrate 7 (circuit pattern 5) with high thermal conductivity to which the semiconductor chips 9 are fixed is detected. The temperature of the semiconductor chip 9 is detected. However, it is necessary to grasp in advance the correlation between the temperature of the insulating substrate 7 and the temperature of the semiconductor chip 9.

また、半導体チップ９に図示しないヒートスプレッダが固着した半導体装置の場合は、特許文献２に記載されているように半導体チップ９上にサーミスタを配置することが困難になるので、本発明が有効となり、前記と同様の効果が得られる。   Further, in the case of a semiconductor device in which a heat spreader (not shown) is fixed to the semiconductor chip 9, it is difficult to dispose a thermistor on the semiconductor chip 9 as described in Patent Document 2, so that the present invention is effective. The same effect as described above can be obtained.

図３〜図６は、この発明の第２実施例の半導体装置の製造方法を工程順に示した要部製造工程断面図である。この要部製造工程断面図は図１に相当する断面図である。
図３（ａ）に示すように、絶縁基板７を構成する回路パターン５にはんだ板を介して半導体チップ９を配置し、水素（Ｈ2）の還元雰囲気３２で２００℃以上の温度のはんだ付け炉３１に入れて半導体チップ９の図示しない裏面電極と回路パターン５のはんだ付けを行う。 3 to 6 are cross-sectional views showing a main part manufacturing process showing the semiconductor device manufacturing method according to the second embodiment of the present invention in the order of processes. This principal part manufacturing process sectional view is a sectional view corresponding to FIG.
As shown in FIG. 3A, a semiconductor chip 9 is disposed on a circuit pattern 5 constituting an insulating substrate 7 via a solder plate, and soldering is performed at a temperature of 200 ° C. or higher in a hydrogen (H 2 ) reducing atmosphere 32. It puts in the furnace 31 and solders the back surface electrode (not shown) of the semiconductor chip 9 and the circuit pattern 5.

つぎに、図３（ｂ）に示すように、全体をはんだ付け炉３１から取り出し、半導体チップ９の図示しない表面電極（エミッタ電極やゲート電極）と回路パターン５の一部である電極６とをボンディングワイヤ１０で接続する。図面右側のボンディングワイヤ１０は回路パターン５の図示しない別の電極６に接続する。   Next, as shown in FIG. 3B, the whole is taken out from the soldering furnace 31, and the surface electrode (emitter electrode and gate electrode) (not shown) of the semiconductor chip 9 and the electrode 6 which is a part of the circuit pattern 5 are attached. Connect with bonding wire 10. The bonding wire 10 on the right side of the drawing is connected to another electrode 6 (not shown) of the circuit pattern 5.

つぎに、図４（ａ）に示すように、銅ベース１上にはんだ介して絶縁基板７を載せ、水素の還元雰囲気２５で２００℃以上の温度のはんだ付け炉３３に入れて絶縁基板７を構成する裏側の導電膜３と銅ベース１のはんだ付けを行う。   Next, as shown in FIG. 4A, the insulating substrate 7 is placed on the copper base 1 via solder, and the insulating substrate 7 is placed in a soldering furnace 33 at a temperature of 200 ° C. or higher in a hydrogen reducing atmosphere 25. The back side conductive film 3 and the copper base 1 are soldered.

つぎに、図４（ｄ）に示すように、端子ケース１７を絶縁基板７を囲むように上から被せて銅ベース１上に載せ、位置合わせして図示しない接着剤で端子ケース１７を銅ベース１に固着する。   Next, as shown in FIG. 4 (d), the terminal case 17 is placed on the copper base 1 so as to surround the insulating substrate 7, placed on the copper base 1, and aligned, and the terminal case 17 is attached to the copper base with an adhesive (not shown). 1 is fixed.

つぎに、図５（ｅ）に示すように、半導体チップ９に接続する電極６と端子ケース１７の端子１８をボンディングワイヤ１５で接続し、回路パターン５の一つである電極１１と端子ケース１７の端子１８をボンディングワイヤ１６で接続する。   Next, as shown in FIG. 5E, the electrode 6 connected to the semiconductor chip 9 and the terminal 18 of the terminal case 17 are connected by a bonding wire 15, and the electrode 11 and the terminal case 17 which are one of the circuit patterns 5 are connected. These terminals 18 are connected by bonding wires 16.

つぎに、図５（ｆ）に示すように、絶縁基板７を構成する回路パターン５の一つである電極１１に銀ペースト１２を塗布する。続いて、この電極上１１に銀ペースト１２を介してサーミスタ１３を載置し、サーミスタ１３の電極１４と回路パターン５の電極１１を銀ペーストを挟んで対峙させる。続いて、全体を大気中で１５０℃程度（はんだ付け温度より低い）の恒温槽３４に入れて、銀ペースト１２の硬化を行う。銀ペースト１２の硬化に当たっては、恒温槽３４の代わりに熱板を使用してもよい。また窒素雰囲気で銀ペースト１２を硬化する場合には窒素雰囲気の炉に入れて行う。   Next, as shown in FIG. 5 (f), a silver paste 12 is applied to the electrode 11 which is one of the circuit patterns 5 constituting the insulating substrate 7. Subsequently, the thermistor 13 is placed on the electrode 11 via the silver paste 12, and the electrode 14 of the thermistor 13 and the electrode 11 of the circuit pattern 5 are opposed to each other with the silver paste interposed therebetween. Subsequently, the whole is placed in a constant temperature bath 34 at about 150 ° C. (lower than the soldering temperature) in the atmosphere, and the silver paste 12 is cured. When the silver paste 12 is cured, a hot plate may be used instead of the thermostatic chamber 34. Further, when the silver paste 12 is cured in a nitrogen atmosphere, it is performed in a furnace having a nitrogen atmosphere.

尚、作業内容は異なるが、この銀ペースト１２による回路パターン５の一つである電極１１とサーミスタ１３の電極１４との固着は、特許文献２に記載のサーミスタの側面にワイヤを銀ペーストで固着する場合に比べて作業性はよい。   Although the work contents are different, the electrode 11 which is one of the circuit patterns 5 by the silver paste 12 and the electrode 14 of the thermistor 13 are fixed to the side surface of the thermistor described in Patent Document 2 with the silver paste. Workability is better than when doing this.

つぎに、図６（ｇ）に示すように、端子ケース１７内にゲル２０を注入し、全体を１００℃〜１５０℃の硬化炉２６に入れ、ゲル２０を硬化させる。
つぎに、図６（ｈ）に示すように、全体を硬化炉２６から取り出して端子ケース１７上に図示しない接着剤を塗布し、その上にフタ２１を載置する。続いて、全体を１００℃程度の硬化炉２７に入れて接着剤を硬化させ、フタ２１を端子ケース１７上に固着する。 Next, as shown in FIG. 6G, the gel 20 is poured into the terminal case 17, and the whole is put into a curing furnace 26 at 100 ° C. to 150 ° C. to cure the gel 20.
Next, as shown in FIG. 6 (h), the whole is taken out from the curing furnace 26, an adhesive (not shown) is applied on the terminal case 17, and the lid 21 is placed thereon. Subsequently, the whole is placed in a curing furnace 27 at about 100 ° C. to cure the adhesive, and the lid 21 is fixed onto the terminal case 17.

つぎに、全体を硬化炉２７から取り出して図１に示す半導体装置が完成する。
前記の銀ペースト１２を硬化させる工程で、硬化させるときの温度は例えば１５０℃なので、すでにはんだ付けした箇所のはんだ２，８は再溶融することはない。また、銀ペースト１２なのでフラックス処理は不要であり、従って洗浄も不要である。 Next, the whole is taken out from the curing furnace 27 to complete the semiconductor device shown in FIG.
In the step of curing the silver paste 12, the temperature at the time of curing is, for example, 150 ° C., so that the solders 2 and 8 at the already soldered portions are not remelted. Moreover, since it is the silver paste 12, a flux process is unnecessary and therefore washing | cleaning is also unnecessary.

前記の銀ペースト１２を硬化させる工程で、はんだ２、８の再溶融がないので、はんだ２、８のはみ出しがなく、製品の良品率が向上する。また、フラックス処理がなく、洗浄工程も不要なため、製造工数が減少する。   In the step of curing the silver paste 12, the solders 2 and 8 are not remelted, so that the solders 2 and 8 do not protrude and the yield rate of the product is improved. Further, since there is no flux treatment and no cleaning process is required, the number of manufacturing steps is reduced.

このように、良品率が向上し、製造工数が減少するので製造コストを低減することができる。それと同時にフラックス処理と洗浄工程がないために製品の信頼性が向上する。
また、サーミスタの電極１４を直接、銀ペースト１２で回路パターン５（電極１１）に固着している。その結果、特許文献２に記載した半導体装置の場合に比べて、製造コストを低減できる。つまり、サーミスタ１３の電極１４を回路パターン５（電極１１）に直接固着することで、特許文献２に記載されているサーミスタの半導体チップへの固着とワイヤのサーミスタへの固着に相当する工程が１回の工程でできるようになり、製造コストを低減することができる。 In this way, the yield rate is improved and the number of manufacturing steps is reduced, so that the manufacturing cost can be reduced. At the same time, the reliability of the product is improved because there is no flux treatment and cleaning process.
Further, the thermistor electrode 14 is directly fixed to the circuit pattern 5 (electrode 11) with silver paste 12. As a result, the manufacturing cost can be reduced as compared with the semiconductor device described in Patent Document 2. That is, by directly fixing the electrode 14 of the thermistor 13 to the circuit pattern 5 (electrode 11), there is one process corresponding to fixing the thermistor to the semiconductor chip and fixing the wire to the thermistor described in Patent Document 2. This can be done in a single process, and the manufacturing cost can be reduced.

尚、前記したように、本発明では、サーミスタ１３の電極１４を銀ペースト１２で回路パターン５（電極１１）に固着すると共に、製造の全工程でフラックス処理を不要とすることで、製造コストの低減と製品の信頼性の向上を図ることができる。   As described above, in the present invention, the electrode 14 of the thermistor 13 is fixed to the circuit pattern 5 (electrode 11) with the silver paste 12, and the flux process is unnecessary in all the manufacturing steps, thereby reducing the manufacturing cost. Reduction and improvement of product reliability can be achieved.

１ 銅ベース
２、８、２２ はんだ
３ 導電膜
４ セラミック板
５ 回路パターン
６、１１、１４、２４ 電極
７ 絶縁基板
９ 半導体チップ
１０、１５、１６ ボンディングワイヤ
１２ 銀ペースト
１３、２３ サーミスタ
１７ 端子ケース
１８ 端子
１９ ケース
２０ ゲル
２１ フタ
DESCRIPTION OF SYMBOLS 1 Copper base 2, 8, 22 Solder 3 Conductive film 4 Ceramic board 5 Circuit pattern 6, 11, 14, 24 Electrode 7 Insulating substrate 9 Semiconductor chip 10, 15, 16 Bonding wire 12 Silver paste 13, 23 Thermistor 17 Terminal case 18 Terminal 19 Case 20 Gel 21 Lid

Claims (2)

絶縁基板を介して半導体チップの温度を検出するサーミスタを有する半導体装置において、回路パターンを構成する前記絶縁基板と、前記回路パターンにはんだで固着される前記半導体チップと、前記回路パターンに銀ペーストで電極が固着されるサーミスタとを具備することを特徴とする半導体装置。 In a semiconductor device having a thermistor for detecting the temperature of a semiconductor chip through an insulating substrate, the insulating substrate constituting a circuit pattern, the semiconductor chip fixed to the circuit pattern with solder, and a silver paste on the circuit pattern A semiconductor device comprising: a thermistor to which an electrode is fixed. 絶縁基板を介して半導体チップの温度を検出するサーミスタを有する半導体装置の製造方法において、
前記絶縁基板を構成する回路パターンに前記半導体チップを水素の還元雰囲気ではんだ付けする工程と、
前記回路パターンに前記サーミスタの対向する側面に形成された電極を銀ペーストで固着する工程と、
を含むことを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device having a thermistor that detects the temperature of a semiconductor chip through an insulating substrate,
Soldering the semiconductor chip to a circuit pattern constituting the insulating substrate in a hydrogen reducing atmosphere;
Fixing the electrodes formed on the opposite side surfaces of the thermistor to the circuit pattern with silver paste;
A method for manufacturing a semiconductor device, comprising:
JP2009239497A 2009-10-16 2009-10-16 Semiconductor device, and method of manufacturing the same Withdrawn JP2011086821A (en)

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EP2509121A1 (en) 2011-04-08 2012-10-10 Nichia Corporation Semiconductor Light Emitting Device
JP2013254873A (en) * 2012-06-07 2013-12-19 Hitachi Ltd Power module and manufacturing method of the same
US9530707B2 (en) 2013-10-03 2016-12-27 Fuji Electric Co., Ltd. Semiconductor module
US10056175B2 (en) 2015-06-04 2018-08-21 Fuji Electric Co., Ltd. Thermistor mounting apparatus and thermistor component
DE102018220949A1 (en) 2018-02-20 2019-08-22 Mitsubishi Electric Corporation Semiconductor device

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2509121A1 (en) 2011-04-08 2012-10-10 Nichia Corporation Semiconductor Light Emitting Device
JP2013254873A (en) * 2012-06-07 2013-12-19 Hitachi Ltd Power module and manufacturing method of the same
US9530707B2 (en) 2013-10-03 2016-12-27 Fuji Electric Co., Ltd. Semiconductor module
US10056175B2 (en) 2015-06-04 2018-08-21 Fuji Electric Co., Ltd. Thermistor mounting apparatus and thermistor component
DE102018220949A1 (en) 2018-02-20 2019-08-22 Mitsubishi Electric Corporation Semiconductor device
CN110176446A (en) * 2018-02-20 2019-08-27 三菱电机株式会社 Semiconductor device
JP2019145641A (en) * 2018-02-20 2019-08-29 三菱電機株式会社 Semiconductor device
DE102018220949B4 (en) * 2018-02-20 2020-11-05 Mitsubishi Electric Corporation Semiconductor device
US10930736B2 (en) 2018-02-20 2021-02-23 Mitsubishi Electric Corporation Semiconductor apparatus
JP7098953B2 (en) 2018-02-20 2022-07-12 三菱電機株式会社 Semiconductor device
CN110176446B (en) * 2018-02-20 2023-10-03 三菱电机株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips
DE102018220949C5 (en) 2018-02-20 2024-08-01 Mitsubishi Electric Corporation semiconductor device

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