JP6101585B2 - Inverter device - Google Patents

Description

The present invention relates to an inverter device.

  In recent years, power semiconductors using wide band gap semiconductors such as SiC (silicon carbide) and GaN (gallium nitride), which have a dielectric breakdown electric field strength 10 times or more higher than that of Si (silicon), have been applied to inverter devices. In particular, with respect to diodes, Si-PiND (P-intrinsic-N) has been used in conventional inverter devices, but since reverse recovery current is large during reverse recovery operation, turn-on loss of switching elements and recovery loss of diodes increase. There was a problem. In addition, if an SBD (Schottky barrier diode) without reverse recovery current is made of Si, the conduction loss greatly increases, and the withstand voltage of about 200 V is the limit. It is effective to produce an SiC-SBD at a high withstand voltage. is there.

  As for the high voltage diode, SiC-SBD has a feature that the junction capacitance is increased because the semiconductor chip can be made thinner than Si-PiND. As a result of this, when the switching element performs a turn-on operation and the SiC-SBD performs a reverse recovery operation, an oscillating current due to the main circuit inductance and the junction capacitance flows, which causes an increase in noise and surge voltage.

  As background art of this technical field, there is JP 2011-78296 A (Patent Document 1). In this document, among the plurality of diodes, only the diode that performs the recovery operation is a wide bandgap semiconductor, and at least one of the diodes that does not perform the recovery operation is a diode other than the wide bandgap semiconductor, resulting in low loss and low cost. It is described that an inverter device is provided. In patent document 1, it is specialized in the structure of an inverter apparatus, The noise increase when a wide band gap semiconductor is applied becomes a subject.

  In JP 2013-90350 A (Patent Document 2), when the supply current is in the vicinity of 0 amperes, the switching speed when turning on is reduced by reducing the switching speed in the case where the supply current is not in the vicinity of 0 amperes. It is described that an inverter device to be suppressed is provided. Patent Document 2 describes a method for suppressing noise, but the problem is that loss increases when a large current flows, and there is no description regarding a three-level inverter device.

JP2011-78296 JP2013-90350A

As described above, in the inverter device to which the SiC-SBD is applied, the oscillating current due to the main circuit inductance and the junction capacitance of the SiC-SBD increases. As a method for suppressing the oscillating current, it is effective to reduce the turn-on speed of the switching element and to add a filter device. The objective of this invention is providing the inverter apparatus which suppresses an oscillating current, without increasing the loss of an inverter apparatus at the time of applying SBD.

In order to solve the above problems, for example, the configuration of the claims is adopted. For example, a direct current three terminal having a high potential terminal that provides a high direct current potential, a negative potential terminal that imparts a negative negative potential, and an intermediate potential terminal that provides an intermediate potential between the high potential and the negative potential. A first switching element having a positive electrode connected to the high potential terminal, a second switching element having a positive electrode connected to a negative electrode of the first switching element, and a positive electrode being a negative electrode of the second switching element A third switching element connected to the fourth switching element, a fourth switching element having a positive electrode connected to the negative electrode of the third switching element and a negative electrode connected to the negative potential terminal, an intermediate potential terminal, and the first switching element A first diode element connected between the negative electrodes of the first switching element, a second diode element connected between the intermediate potential terminal and the negative electrode of the third switching element, and a second switching element. Output terminal connected between the negative electrode of the third switching element and the positive electrode of the third switching element, and the three potentials of the high potential, the intermediate potential, and the negative potential that are given from the three DC terminals are sequentially made to appear at the output terminal. The inverter device has means for applying different voltages to the gate terminals of the second switching element and the third switching element in an operation mode in which the second switching element and the third switching element are simultaneously turned on. Features.

The effect of the present invention is that the oscillating current can be suppressed without even increasing the loss of the inverter device.

It is an example of the circuit diagram which shows the inverter apparatus by Example 1 of this invention. It is an example of the circuit diagram which shows the inverter apparatus by Example 1 of this invention. It is an example of the schematic of the voltage of the inverter apparatus by Example 1 of this invention, and a current waveform. It is an example of the equivalent circuit diagram in operation | movement of the inverter apparatus by Example 1 of this invention. It is an example of the characteristic view of the switching element by Example 1 of this invention. It is an example of the circuit diagram which shows the inverter apparatus by Example 1 of this invention. It is an example of the circuit diagram which shows the inverter apparatus by Example 2 of this invention. It is an example which shows the structure of the inverter apparatus by Example 3 of this invention. It is an example of the circuit diagram which shows the inverter apparatus by Example 3 of this invention. It is an example of the circuit diagram which shows the inverter apparatus by Example 4 of this invention.

  Embodiments will be described below with reference to the drawings.

(Configuration of inverter device)
FIG. 1 is an example of a configuration diagram of an inverter device 100 according to a first embodiment of the present invention. In the circuit diagram of FIG. 1, the inverter device 100 includes DC power supplies 101a and 101b as main power supplies, four switching elements Q1 to Q4, and six diodes D1 to D6. Here, the switching elements Q1 to Q4 are connected in parallel so-called reverse parallel so that the conduction polarities of the diodes D1 to D4 are reversed.

  The switching elements Q1 to Q4 are three-terminal semiconductor elements including a gate terminal, a collector terminal, and an emitter terminal, and the collector current can be controlled by the gate voltage. For example, it is composed of a voltage control element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In addition, the switching elements Q1 to Q4 may have a plurality of switching elements connected in series or connected in parallel.

  The diodes D1 to D6 are two-terminal semiconductor elements having an anode end and a cathode end, and current flows only from the anode end to the cathode end. In order not to increase the loss of the inverter device 100, the diodes D1 to D4 are preferably SBDs (Schottky barrier diodes) having no reverse recovery current, but may be PiNDs (P-intrinsic-N). In addition, the diodes D1 to D6 may have a plurality of diodes connected in series or in parallel.

  As the DC power supplies 101a and 101b, a switching power supply using a commercial power supply may be used, and a primary battery or a secondary battery may be used.

(Operation method of inverter device)
The on and off states of switching elements Q1-Q4 are controlled by gate drive devices 104a-104d, respectively. Hereinafter, the switching element Q3 will be described as an example with reference to FIG.

  The gate driving device 104c of the switching element Q3 includes transistors 108a and 108b and a PWM (Pulse Width Modulation) signal generator 114. The gate driving device 104c is connected to DC power supplies 102c and 103c.

  For example, when the PWM signal generation device 114 of the switching element Q3 outputs an ON signal, the transistor 108a is turned ON, and the potential between the gate and the emitter of the switching element Q3 becomes equal to the DC power source 102c. When the PWM signal generation device 114 of the switching element Q3 outputs an off signal, the transistor 108b is turned on, and the gate-emitter of the switching element Q3 is equipotential with the DC power supply 103c. Here, DC power supply 102c is equal to or higher than threshold voltage 201 of switching element Q3, and DC power supply 103c is lower than threshold voltage 201. For example, if the threshold voltage 201 of the switching element Q3 is 6V, the DC power supply 102c is 18V and the DC power supply 103c is -12V.

  When the gate driving devices 104a, 104b, and 104d of the switching elements Q1, Q2, and Q4 perform the same operation as the gate driving device 104c of the switching element Q3, and the gate driving devices 104a, 104b, and 104d output ON signals, respectively. , Q1, Q2, and Q4 are equipotential to the DC power supplies 102a, 102b, and 102d, respectively, and when the gate drive devices 104a, 104b, and 104d output an off signal, the gate emitters of Q1, Q2, and Q4 are The DC power supplies 103a, 103b, and 103d are used, respectively. Here, the DC power supplies 102a, 102b, and 102c are equal to or higher than the threshold voltages of the switching elements Q1, Q2, and Q4, respectively, and the DC power supplies 102a, 102b, and 102d are based on the threshold voltages of the switching elements Q1, Q2, and Q4, respectively. Is also low.

(Configuration and operation of gate voltage switching device)
Next, the operation of the gate voltage switching device 105b of the switching element Q3 will be described. An MPU (Micro Processing Unit) 107b includes a positive / negative determining device 116 that determines whether the output current value detected by the output current sensor 117 is positive and negative, and a PWM signal generating device 115 for the switching element Q2. Here, the MPU 107b only needs to have a means for calculating a plurality of signals and outputting the signals from the results.

  The signal generated by the MPU 107b is sent to the determination circuit 110 via the insulating device 106b, and the determination circuit 110 turns on one of the semiconductor switches 109a and 109b. Specifically, when the output current sensor 117 is a positive current and the PWM signal generation device 115 of the switching element Q2 outputs an on signal, the MPU 107b of the switching element Q3 outputs a signal for turning on the semiconductor switch 109b, In other cases, the MPU 107b of Q3 outputs a signal for turning on the semiconductor switch 109a.

  Here, when the semiconductor switch 109b is turned on while the gate driving device 104c of the switching element Q3 is outputting the on signal, the gate-emitter voltage of Q3 is applied from the DC power supply 102c via the Zener diode 111. For example, if the DC power supply 102c is 18V and the Zener voltage of the Zener diode 111 is 12V, the gate-emitter voltage of Q3 is 6V. Here, the current flowing through the Zener diode is suppressed by the resistor 112 so as not to exceed the element rating of the Zener diode 111.

  The capacitor 113 is added to remove noise from the Zener diode 111 and stabilize the voltage of the resistor 112. The gate voltage switching device 105b is implemented by using the Zener diode 111 and the semiconductor switches 109a and 109b. However, any device that can switch the output voltage based on a specific signal may be used.

  On the other hand, when the semiconductor switch 109a is turned on while the gate drive device 104c of the switching element Q3 is outputting the on signal, the DC power supply 102c is applied between the gate emitters of Q3.

  Next, the operation of the gate voltage switching device 105b of the switching element Q3 will be described using the timing chart of FIG. Here, it is assumed that the output current sensor 117 detects a positive current. In mode 1 from time t1 to time t2, ON signals are output from the gate drive devices 104c and 104d of the switching elements Q3 and Q4, and the DC power supplies 102c and 102d are applied between the gate emitters of the switching elements Q3 and Q4.

  At time t2, an off signal is output from the gate drive device 104d of the switching element Q4, and the DC power supply 103d is applied to the gate-emitter voltage of the switching element Q4.

  Thereafter, a dead time period 202 is provided at times t2 to t3 so that the switching elements Q2 to Q4 do not turn on simultaneously.

  When the dead time period 202 ends, the mode shifts to mode 2 from time t3 to t5, an ON signal is output from the gate drive device 104b of the switching element Q2, and the DC power supply 102b is applied between the gate emitter of the switching element Q2. At this time, since the output current sensor 117 detects a positive signal, a signal for turning on the semiconductor switch 109b is output from the MPU 117 of the switching element Q3. As described above, a voltage obtained by subtracting the Zener voltage of the Zener diode 111 from the DC power supply 102c is applied between the gate and emitter of the switching element Q3. This voltage is lower than DC power supply 102c and is equal to or higher than threshold voltage 201 of switching element Q3.

(Effect of gate voltage switching device)
Next, the effect of the gate voltage switching device 105b will be described with reference to FIG. 3, FIG. 4, and FIG. Here, it is assumed that the output current sensor 117 detects a positive current.

  In mode 1 in which the switching elements Q3 and Q4 are turned on, a main current of several hundred A is output from the DC power supply 101b via the diodes D3 and D4. When an inductive device such as a motor is connected to the output terminal, since the direction of the output current does not change instantaneously, in mode 2 in which the switching elements Q2 and Q3 are on, the output current is the same as that of the diode D5. It flows through the switching element Q2.

  FIG. 4 shows an equivalent circuit when shifting from mode 1 to mode 2. In the diode D4, the main current flows in the mode 1, and in the mode 2, the DC power source 101b is applied between the anode and the cathode of the diode D4, so that the reverse recovery operation is performed and the junction capacitance 305 is equivalently obtained.

  Here, the inverter device 100 has electrical wiring for connecting the switching elements Q1 to Q4 and the diodes D1 to D6, and the parasitic inductance 301 exists everywhere. That is, when the mode 1 is shifted to the mode 2, the oscillating current passes through the path of the DC power source 101b, the parasitic inductance 301, the on-resistance 302 of the diode D5, the on-resistances 303 and 304 of the switching elements Q2 and Q3, and the junction capacitance 305 of the diode D4. Flows.

  As shown in FIG. 3, since the oscillating current 203 flows through the collector terminal of the switching element Q4, an oscillating voltage 204 is generated between the collector and emitter of the switching element Q4, which causes noise. This oscillating current becomes more prominent as a high-speed operation is realized, for example, by reducing the gate resistance of the switching element Q2.

  Although it is effective to slow down the turn-on speed of the switching element Q2 as a method for suppressing the oscillating current, an increase in switching loss is a problem. As another means, in order to suppress the oscillating current, it is effective to increase the resistance of the path. Therefore, the on-resistances 303 and 304 of the switching elements Q2 and Q3 may be increased.

  FIG. 5 shows the gate-emitter voltage dependency of the relationship between the collector-emitter voltage and the collector current of the switching element. When the collector-emitter voltage is kept constant, the collector current is reduced by reducing the gate-emitter voltage, so that the on-resistance of the switching element increases. By utilizing this characteristic, the oscillation current can be suppressed by reducing the gate-emitter voltage of the switching elements Q2, Q3. On the other hand, since a main current of several hundred A flows through the switching element Q2, increasing the on-resistance 303 of the switching element Q2 significantly increases the loss.

  The gate voltage switching device according to the present invention is characterized in that only the gate-emitter of the switching element Q3 is made smaller than the DC power supply 102c and larger than the threshold voltage 201 of the switching element Q3. Only can be increased. Here, when SiC-SBD is applied to the diode D4, there is no reverse recovery current and the oscillating current is several tens of A. Therefore, an increase in loss due to the increase in the ON resistance 304 of the switching element Q3 hardly occurs.

  As shown in FIG. 3, when the gate voltage switching device is applied, the collector current of the switching element Q4 can be reduced as the oscillating current 205, and accordingly, the collector-emitter voltage of the switching element Q4 is also suppressed as the oscillating voltage 206. it can.

  Further, the time for applying the gate voltage switching device may be until the switching element Q2 is completely turned on and the oscillation current 203 or 205 of the collector current of the switching element Q4 is suppressed. That is, based on the signal that the switching element Q2 is completely turned on, the DC power source 102c is applied between the gate and emitter of the switching element Q3 at time t4.

  In the above embodiment, the case where the output current sensor 117 detects a positive signal has been described. Hereinafter, the operation of the gate voltage switching device 105a of the switching element Q2 when the output current sensor 117 detects a negative current will be described. Since the configuration of the inverter device is the same as described above, the description thereof is omitted.

The difference between the gate voltage switching device 105a of the switching element Q3 and the gate voltage switching device 105b of the switching element Q2 is a determination signal of the MPU 107a. The MPU 107a includes a positive / negative determining device 116 that determines whether the value detected by the output current sensor 117 is positive and negative, and a PWM signal generating device 114 for the switching element Q3. The signal generated by the MPU 107a is sent to the determination circuit 110 via the insulating device 106a, and the determination circuit 110 turns on one of the semiconductor switches 109a and 109b. Specifically, when the output current sensor 117 is a negative signal and the PWM signal generation device 115 of the switching element Q3 outputs an on signal, the MPU 107a of the switching element Q2 outputs a signal for turning on the semiconductor switch 109b, For other signals, the MPU 107b outputs a signal for turning on the semiconductor switch 109a. Hereinafter, the operation of changing the gate-emitter voltage of the switching element Q2 is the same as that of the gate voltage switching device 104c of the switching element Q3.

  FIG. 7 is a circuit diagram of the inverter device 100 used in Embodiment 2 of the present invention. Since the operation mode of the inverter device 100 and the operation of the gate voltage switching devices 106a and 106b are the same as those in the first embodiment, the description thereof is omitted.

  Generally, there is a problem that the oscillating current generated during the reverse recovery operation of the SiC-SBD increases as the output current increases. In order to solve this problem, the oscillation current is efficiently suppressed by using the output current sensor 117 and the output current value determination devices 402a and 402b.

  The determination devices 402 a and 402 b are devices that determine the current value detected by the output current sensor 117. This value is input to the gate voltage switching devices 105a and 105b via the insulating devices 401a and 401b, respectively. Gate voltage switching devices 105a and 105b control the gate-emitter voltage output to switching elements Q2 and Q3 based on the values input from insulating devices 401a and 401b.

For example, when the output current sensor 117 detects a large positive current of several hundred A, the gate-emitter voltage of the switching element Q3 is lower than the gate-emitter voltage of the switching element Q2, and the threshold voltage of the switching element Q3 In the above, when the gate voltage switching device 105b is controlled so as to be as close as possible to the threshold voltage, and when the output current sensor 117 detects a large negative current of several hundreds of A, it is between the gate and emitter of the switching element Q2. It is effective to control the gate voltage switching device 105a so that the voltage is lower than the gate-emitter voltage of the switching element Q3 and equal to or higher than the threshold voltage of the switching element Q2 as much as possible. By doing so, the on-resistances 303 and 304 of the switching elements Q2 and Q3 increase when the output current is large, and the oscillating current can be suppressed.

  FIG. 8 shows a configuration of an inverter device 100 for realizing the third embodiment.

  FIG. 9 is a circuit diagram of an inverter device 100 used in Embodiment 3 of the present invention. Since the operation mode of the inverter device 100 and the operation of the gate voltage switching devices 106a and 106b are the same as those in the first embodiment, the description thereof is omitted.

  In general, there is a problem that the oscillating current generated in the reverse recovery operation of the SiC-SBD increases as the temperature of the inverter device 100 decreases. In order to solve this problem, the signals output from the temperature sensor 502 of the cooler 501 connected to the inverter device 100 are processed by the temperature determination devices 503a and 503b, and the voltages output from the gate voltage switching devices 105a and 105b are processed. Control.

For example, when the temperature sensor 502 detects a temperature below freezing point and the output current sensor 117 detects a positive current, the gate-emitter voltage of the switching element Q3 is lower than the gate-emitter voltage of the switching element Q2, and the switching element When the gate voltage switching device 105b is controlled to be as close as possible to the threshold voltage within the threshold voltage of Q3, and the negative current is detected by the output current sensor 117, the gate of the switching element Q2 It is effective to control the gate voltage switching device 105a so that the emitter-to-emitter voltage is lower than the gate-emitter voltage of the switching element Q3 and equal to or higher than the threshold voltage of the switching element Q2. is there.

  FIG. 10 is a circuit diagram of an inverter device 100 used in Embodiment 4 of the present invention. Since the operation mode of the inverter device 100 and the operation of the gate voltage switching devices 106a and 106b are the same as those in the first embodiment, the description thereof is omitted.

  In general, the oscillating current generated in the reverse recovery operation of the SiC-SBD increases as the DC power sources 101a and 101b of the inverter device 100 are higher. In order to solve this problem, the voltage output from the gate voltage switching devices 105 a and 105 b is controlled based on the voltage sensor 601 connected to the inverter device 100.

  For example, when the voltage sensor 601 detects a higher voltage than the DC power supplies 101a and 101b when the inverter device 100 is normally operating and the output current sensor 117 detects a positive current, the switching element Q3 The gate voltage switching device 105b is controlled such that the gate-emitter voltage is lower than the gate-emitter voltage of the switching element Q2 and equal to or higher than the threshold voltage of the switching element Q3, and the output voltage When the sensor 117 detects a negative current, the threshold voltage between the gate-emitter voltage of the switching element Q2 is lower than the gate-emitter voltage of the switching element Q3 and is equal to or higher than the threshold voltage of the switching element Q2. It is effective to control the gate voltage switching device 105a so as to be as close as possible.

For example, in a railway inverter device, the voltage sensor 601 detects a voltage higher than that in the normal operation during the regenerative operation, and thus the fourth embodiment is effective.

Q1 to Q4 Switching elements D1 to D6 Diode 100 Inverter devices 101a and 101b DC power supply (main power supply)
102a to 102d DC power supply (first DC power supply)
103a to 103d DC power supply (second DC power supply)
104a to 104d Gate driving devices 105a and 105b Gate voltage switching devices 106a, 106b, 401a and 401b Insulating devices 107a and 107b MPU (Micro Processing Unit)
108a, 108b Transistors 109a, 109b Semiconductor switch 110 Determination circuit 111 Zener diode 112 Resistor 113 Capacitor 114 Q3 PWM signal generation device 115 Q2 PWM signal generation device 116 Positive / negative determination device 117 Output current sensor 201 Threshold voltage of switching element Q3 202 Dead time period 203 Conventional collector current waveform 204 Conventional collector-emitter voltage waveform 205 Collector current waveform 206 of the present invention Collector-emitter voltage waveform of the present invention 301 Parasitic inductance 302 On-resistance 303, 304 of the diode D5 Switching element Q2, Q3 ON-resistance 305 Junction capacitance 402a, 402b of diode D4 Current value determination device 501 Cooler 502 Temperature sensor 503a, 503b Temperature determination device 60 Voltage sensor 602a, 602b voltage value determining device

Claims (8)

A direct current three terminal including a high potential terminal for applying a high direct current potential, a negative potential terminal for providing a negative direct current potential, and an intermediate potential terminal for providing an intermediate potential between the high potential and the negative potential;
A first switching element having a positive electrode connected to the high potential terminal;
A second switching element having a positive electrode connected to the negative electrode of the first switching element;
A third switching element having a positive electrode connected to the negative electrode of the second switching element;
A fourth switching element having a positive electrode connected to the negative electrode of the third switching element and a negative electrode connected to the negative potential terminal;
A first diode element connected between the intermediate potential terminal and the negative electrode of the first switching element;
A second diode element connected between the intermediate potential terminal and the negative electrode of the third switching element;
An output terminal connected between the negative electrode of the second switching element and the positive electrode of the third switching element;
In the inverter device that causes the three potentials of the high potential, the intermediate potential, and the negative potential that are given from the three DC terminals to appear at the output terminal sequentially,
Means for applying different voltages to gate terminals of the second switching element and the third switching element in an operation mode in which the second switching element and the third switching element are simultaneously turned on; A featured inverter device. The inverter device according to claim 1,
In the operation mode in which the second switching element and the third switching element are simultaneously turned on, the control signal of the second switching element, the control signal of the third switching element, and the current flowing through the output terminal An inverter device comprising a device for controlling a timing at which a voltage at a gate terminal of the second switching element and the third switching element changes according to positive and negative. In the inverter device according to claim 1 or 2,
The voltage applied to the gate terminal of the second switching element when current flows from the output terminal to the three DC terminals in an operation mode in which the second switching element and the third switching element are simultaneously turned on. Is lower than the threshold voltage of the second switching element and lower than the voltage of the gate terminal of the third switching element, and when a current flows from the three DC terminals to the output terminal, the gate of the third switching element The voltage applied to the terminal is equal to or higher than the threshold voltage of the third switching element and lower than the voltage of the gate terminal of the second switching element. In the inverter apparatus as described in any one of Claims 1 thru | or 3,
In the operation mode in which the second switching element and the third switching element are simultaneously turned on, a voltage applied to the gate terminals of the second switching element and the third switching element flows to the output terminal. An inverter device controlled by a current value. In the inverter apparatus as described in any one of Claim 1 thru | or 4,
In the operation mode in which the second switching element and the third switching element are simultaneously turned on, the voltage applied to the gate terminals of the second switching element and the third switching element is the temperature of the inverter device. It is controlled by the inverter apparatus characterized by the above-mentioned. In the inverter apparatus as described in any one of Claims 1 thru | or 5,
In an operation mode in which the second switching element and the third switching element are simultaneously turned on, the voltage applied to the gate terminals of the second switching element and the third switching element is the high potential terminal and An inverter device controlled by a voltage between the negative potential terminals. The inverter device according to any one of claims 1 to 6,
In an operation mode in which the second switching element and the third switching element are turned on simultaneously, after applying different voltages to the gate terminal of the second switching element or the third switching element, When the turn-on operation of the second switching element or the third switching element is completed, the same voltage is applied to the second switching element and the third switching element. In the inverter apparatus as described in any one of Claim 1 thru | or 7,
The inverter device characterized in that the first to fourth switching elements are based on a semiconductor material having a larger band gap than silicon.