JP2010251517A - Power semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device that has improved conversion efficiency of electric power as compared with conventional examples at current values of a load current ranging widely from a small-current region to a large-current region. <P>SOLUTION: A power semiconductor element is switched under the control of a first gate electrode, and has a second gate for switching between an IGBT (Insulated Gate Bipolar Transistor) operation and a MOS transistor operation. When a switching operation is performed by the first gate electrode, a control signal is applied to the second gate electrode in accordance with a current value of a load current flowing to a load to make a choice of whether the power semiconductor element operates in a MOS transistor or operates as a bipolar transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power semiconductor device used for a power converter or the like that handles a large amount of power.

Conventionally, power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), diodes, GTO (Gate Turn Off) thyristors, and power transistors have been applied to various inverter devices depending on the withstand voltage and current capacity.
In particular, the IGBT can be easily switched by applying a voltage, is easy to control, has a large current capacity, and is capable of high-frequency operation with a large current. It has an advantage in comparison.

In this IGBT, as shown in FIGS. 16 and 17, the drain current of the MOS transistor becomes the base current of the pnp bipolar transistor (hereinafter referred to as pnp transistor), and the npn bipolar transistor (hereinafter referred to as npn transistor) is turned on. To turn on (see, for example, Patent Document 1). In FIG. 16, the pnp transistor is configured such that a collector layer in the IGBT is a collector, a drift layer is a base, and a base region is an emitter.
Even if the collector current of the pnp transistor increases, carriers are injected into the drift layer, conductivity modulation occurs, and the resistance of the element decreases, so that the increase in voltage between the collector and the emitter accompanying the increase in current is suppressed. Therefore, it is frequently used as a large current switching element.

JP 2000-350475 A

However, in the current region where the collector current is small, the lower limit value of the collector-emitter voltage is limited by the junction potential, and energy loss occurs.
For this reason, in power generation systems that use renewable energy such as mega solar, output fluctuations are severe, so when using IGBT for power conversion, there is a problem of reduced power conversion efficiency in a small current region such as during partial load. Become.

In recent years, matrix converters have been put into practical use. This matrix converter includes an AC input and an AC output, and outputs an AC output of an arbitrary voltage by directly PWM controlling the power supply voltage of the AC input. Since there is no storage element such as a capacitor in the conversion circuit, there is no problem of a reduction in life due to deterioration of the capacitor, and the circuit scale of the converter is reduced and the converter becomes compact.
However, when constructing this matrix converter, it is necessary to use a bidirectional device in order to perform a process of flowing current bidirectionally from input to output and from output to input. In order to configure this bidirectional device, two general-purpose IGBTs and two diodes are combined so as to operate bidirectionally, or two reverse blocking IGBTs are connected in parallel so that their polarities are opposite to each other. Will be used. For this reason, the conventional matrix converter cannot realize circuit miniaturization as expected.

The present invention has been made in view of such circumstances, and is capable of improving power conversion efficiency over a wide range of current values from a small current region to a large current region as compared with the conventional example. An object is to provide a semiconductor device.
In addition, the present invention can improve the power conversion efficiency and perform the operation of flowing a current bidirectionally over a wide range of current values from a small current region to a large current region. An object is to provide a power semiconductor device.

The invention according to claim 1 is a first MOS transistor (for example, the first MOSFET 104 in the embodiment) that causes the base current of the bipolar transistors (for example, the pnp transistor 101 and the npn transistor 102 in the embodiment) in the IGBT to flow and causes the IGBT to perform a switching operation. ) And an on / off operation to control the potential of the base of the bipolar transistor. When performing a switching operation, the base current is supplied to the base of the bipolar transistor to operate as an IGBT, or the first MOS transistor. A power semiconductor element having a second MOS transistor (for example, the second MOSFET 50 in the embodiment) that controls whether to operate as a MOS transistor only, Conductivity type drift layer (drift layer 10 in FIGS. 1, 10, and 13) and a second conductivity type base region formed on the main surface side of the drift layer (FIGS. 1, 10, and 13). Base region 11), a first conductivity type emitter region (emitter region 12 in FIGS. 1, 10, and 13) formed on the surface of the base region so as to terminate in the base region, and A back diffusion layer of the second conductivity type formed on the back surface side of the drift layer (the back surface diffusion layer 15 in FIGS. 1 and 10 and the back surface diffusion region 51 in FIG. 13), and the back surface diffusion in the back surface diffusion layer The first conductivity type MOS diffusion layer (the MOS diffusion layer 150 in FIGS. 1 and 10 and the MOS diffusion layer 52 in FIG. 13) formed on the surface of the layer and the base region between the emitter region and the drift layer are 1st transistor of 1MOS transistor A first gate insulating film (gate insulating film 13 in FIGS. 1, 10, and 13) formed on the surface of the second channel region, and connected to the emitter region and the base region. An emitter electrode (emitter electrode E in FIGS. 1, 10 and 13) and a first gate electrode (gate electrode 14 in FIGS. 1, 10 and 13) formed on the first gate insulating film; The collector electrode formed on the back diffusion layer and the MOS diffusion layer (the collector electrode 16 in FIGS. 1 and 10 and the collector electrode 56 in FIG. 13), and the surface of the back diffusion layer between the drift layer and the MOS diffusion layer A second gate insulating film (the gate insulating film 17 in FIGS. 1 and 10 and the gate insulating film 53 in FIG. 13) formed as a second channel region of the second MOS transistor and formed on the surface of the second channel region. )When, And a second gate electrode (the gate electrode 18 in FIGS. 1 and 10 and the gate electrode 54 in FIG. 13) formed on the second gate insulating film.
Each component of this claim is described corresponding to the configuration of FIGS. 1, 2, 10 and 13 as described above.

The invention according to claim 2 is the power semiconductor element according to claim 2, wherein the drift layer (for example, the drift layer 10 in FIGS. 1 and 2 in the embodiment) is used as a drain, and the emitter region (for example, implementation). The first gate electrode (for example, the emitter region 12 of FIGS. 1 and 2 in the embodiment) is used as the source, and the surface of the base region (for example, the base region 11 of FIGS. 1 and 2 in the embodiment) is the channel formation region. , The first MOS transistor (for example, the first MOSFET 104 of FIG. 2 in the embodiment) is formed, the MOS diffusion layer is used as a drain, the drift layer is used as a source, and the back surface diffusion layer is used as a channel. A second M comprising a second gate electrode (for example, the gate electrode 18 of FIG. 1 in the embodiment) serving as a region. When an S transistor (for example, the second MOSFET 50 in the embodiment) is formed and the MOS transistor operation is performed, when the first MOS transistor is turned on, the second MOS transistor is turned on, while the bipolar transistor is turned on. When the operation is performed, the second MOS transistor is turned off when the first MOS transistor is turned on.
Each component of this claim is described corresponding to the configuration of FIGS. 1, 2, 10 and 13, respectively, as described above.

A third aspect of the present invention is the power semiconductor element according to the first or second aspect, wherein a groove is formed from the back surface of the back surface diffusion layer, penetrating the MOS diffusion layer and reaching the drift layer. The second gate insulating film is formed on the inner surface of the groove, the second gate electrode is provided on the second gate insulating film, and the inner peripheral surface inside the groove in the collector layer is formed on the second gate electrode. A channel region is used.
Each component of this claim is described corresponding to the configuration of FIG. 10 as described above.

The invention according to claim 4 is the power semiconductor element according to claim 1 or 2, wherein a diffusion layer of a first conductivity type formed on the surface of the collector region so as to terminate in the collector region ( 13 in the embodiment, the second MOS transistor is formed with the drift layer and the surface of the drift layer between the diffusion layers as the second channel region, and the first MOS transistor On the other hand, it is characterized by having a plane-symmetric structure with a plane perpendicular to the direction of current flow as a plane of symmetry.
Each component of this claim is described corresponding to the configuration of FIG. 13 as described above.

  According to a fifth aspect of the present invention, there is provided the power semiconductor device according to the fourth aspect, wherein in the first MOS transistor, a first groove that penetrates the emitter region and reaches the drift layer from the surface of the base region. And forming the first gate oxide film in the first groove, providing the first gate electrode in the shape of the first gate oxide film, and forming the inside of the first groove in the emitter region In the second MOS transistor, a groove reaching the drift layer from the back surface of the collector layer is formed, and the second gate insulating film is formed on the inner surface of the groove. The second gate electrode is provided on the second gate insulating film, and the inner peripheral surface of the collector layer in the trench is used as the second channel region. Each component of this claim is described corresponding to the configuration of FIG. 13 as described above.

The invention according to claim 6 is the power semiconductor element according to claim 4 or claim 5, wherein in a forward operation in which a current flows from the collector electrode to the emitter electrode, in a bipolar transistor operation, The first MOS transistor is turned on, the second MOS transistor is turned off, and in the case of MOS transistor operation, the first MOS transistor is turned on, the second MOS transistor is turned on, and a current flows from the emitter electrode to the collector electrode. When the bipolar transistor is operated, the first MOS transistor is turned off and the second MOS transistor is turned on. When the MOS transistor is operated, the first MOS transistor is turned on and the second MOS transistor is turned on. Turn on And features.
Each component of this claim is described corresponding to the configuration of FIG. 13 as described above.

A seventh aspect of the present invention is an intelligent power module, the power semiconductor element according to any one of the first to sixth aspects, a current sensor that measures a current flowing through the power semiconductor element, and a measurement of the current sensor. It is determined whether the measured current exceeds a preset threshold value. When the measured current exceeds the threshold value, the power semiconductor element is operated as a bipolar transistor. When the measured current is equal to or lower than the threshold value, the power semiconductor element is operated as a MOS transistor. And a control circuit for outputting a control signal to the first gate electrode.
Each component of this claim is described corresponding to the configuration of FIG. 11 as described above.

The invention according to claim 8 is the intelligent power module according to claim 7, wherein the control circuit has a current range for operating the power semiconductor element as a MOS transistor by the control signal for each switching of the power semiconductor element. The threshold current range is adjusted so that the power consumption of the power semiconductor element obtained from the measurement current is increased or decreased and the power consumption of the power semiconductor element is further reduced.
Each component of this claim is described corresponding to the configuration of FIG. 11 as described above.

A ninth aspect of the present invention is an intelligent power module comprising the power semiconductor element according to any one of the first to sixth aspects, wherein a control signal for operating as a MOS transistor is always applied to the second gate electrode. And operating as a bipolar transistor with an increase in the current flowing through the power semiconductor element.
Each component of this claim is described corresponding to the configuration of FIG. 11 as described above.

A tenth aspect of the present invention is a matrix converter comprising a plurality of power semiconductor elements in which a current flows in both directions (that is, a function of switching a direction in which the current flows) according to any one of the fourth to sixth aspects. Yes, the power output from the power source is controlled by switching the first MOS transistor and the second MOS transistor in the power semiconductor element, and a current is passed in the forward direction or the reverse direction in the MOS transistor operation or the IGBT operation. A variable frequency AC power is output.
Each component of this claim is described corresponding to the configuration of FIG. 14 as described above.

  As described above, according to the power semiconductor element of the present invention, since the MOS transistor operation or the bipolar transistor operation is arbitrarily switched by the control signal applied to the second gate electrode, the small current region at the time of partial load is obtained. In FIG. 2, the power loss of the power semiconductor element is reduced and the operation of the bipolar transistor (hereinafter referred to as IGBT operation) is performed in a large current region as compared with the case where the operation of the MOS transistor is performed to perform the bipolar operation. Thus, it is possible to reduce the power loss of the power semiconductor element as compared with the case where the MOS transistor operation is performed, and to have a low power loss characteristic in a wide range of a small current region and a large current region.

  According to the intelligent power module of the present invention, the control circuit compares the current value detected by the current sensor with a preset threshold value, and performs the MOS transistor operation or the bipolar transistor operation to the second gate. Since switching is performed by a control signal applied to the electrode, the power loss of the power semiconductor element is reduced compared with the case where the MOS transistor is operated in a small current region at the time of partial load and the bipolar operation is performed. Compared with the case where the IGBT operation is performed in the current region and the MOS transistor operation is performed, it is possible to reduce the power loss of the power semiconductor element, and in the wide range of the small current region and the large current region, In comparison, the characteristic of lower power loss can be obtained.

In addition, according to the power semiconductor element of the present invention, it is not necessary to configure a power semiconductor element that allows a current to flow bidirectionally by combining a plurality of power semiconductor elements (for example, IGBT) as in the prior art. The size can be reduced, and since a plurality of power semiconductor elements are not used, the price can be reduced as compared with the prior art.
In addition, according to the matrix converter of the present invention, since a power conversion unit is not configured using a bidirectional IGBT in which a plurality of power semiconductor elements are combined as in the prior art, the matrix converter is reduced in size compared to the conventional one. It is possible to reduce the price of the apparatus as compared with the conventional one.

1 is a conceptual diagram showing a cross-sectional structure of a configuration example of a power semiconductor element 30 according to a first embodiment of the present invention. It is a conceptual diagram which shows the equivalent circuit of the power semiconductor element 50 of FIG. It is a graph which shows the IV characteristic of IGBT. It is a graph which shows the IV characteristic of a MOS transistor. It is a graph which shows the electric current value which flows corresponding to the gate voltage of a MOS transistor and IGBT in the area | region (area | region of a low load current) of the applied voltage. It is a conceptual diagram explaining the measurement system which measured energy loss. 6 is a waveform diagram showing a waveform of a voltage applied to the first MOS transistor 104 in measurement. FIG. 6 is a waveform diagram showing a waveform of a voltage applied to the first MOS transistor 104 in measurement. FIG. 4 is a graph showing a result of comparison of energy loss between a MOS transistor, an IGBT, and a power semiconductor element 30. The conceptual diagram which shows the cross-section of the structural example of the other power semiconductor element 30 in one Embodiment of this invention. It is a block diagram which shows the structural example of IPM using the power semiconductor element by this invention. 4 is a waveform diagram showing a drive waveform applied to the gate electrode 14 of the power semiconductor element 30. FIG. It is a conceptual diagram which shows the cross-section of the structural example of the power semiconductor element 30 by the 2nd Embodiment of this invention. It is a conceptual diagram which shows the structural example of the matrix converter using the power semiconductor element 30 by this invention. It is a conceptual diagram which shows the cross-section of the structural example of the power semiconductor element 30 by the 4th Embodiment of this invention. It is a conceptual diagram which shows the cross-section of the structural example of IGBT relevant to this invention. It is a conceptual diagram which shows the equivalent circuit of IGBT of FIG.

<First Embodiment>
Hereinafter, a power semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing a cross-sectional structure of the power semiconductor device according to the embodiment.
The back diffusion layer 15 is a p-type diffusion layer to which a p-type impurity is added, and forms the emitter of a pnp bipolar transistor. The drift layer 10 is formed as a semiconductor layer (or a semiconductor substrate) to which an n-type impurity is added on the main surface side of this back diffusion layer 15 (the surface in the lower direction of the back diffusion layer 15 in FIG. 1). This drift layer 10 forms the base of a pnp bipolar transistor. Further, a predetermined width and depth along the outer peripheral portion of the back surface on the surface on the back surface (surface in the upper direction of the back surface diffusion layer in FIG. 1) which is the surface opposite to the main surface side of the back surface diffusion layer 15 N-type MOS diffusion layer 150 is formed. That is, the n-type MOS diffusion layer 150 is formed in such a width that the back surface diffusion layer 15 is exposed on the back surface.
A base region 11 to which a p-type impurity is added is formed on the main surface of the drift layer 10 (the surface in the lower direction of the drift layer 10 in FIG. 1). This base region 11 forms the collector of a pnp bipolar transistor.

Further, the main surface of the base region 11 (the surface in the lower direction of the drift layer 10 in FIG. 1) is such that the n-type emitter region 12 terminates in the base region 11, that is, is completely included. Is formed. That is, emitter region 12 is thinner than base region 11, is included in base region 11 in the thickness direction, and is included in base region 11 in a plan view viewed from the direction perpendicular to the main surface of base region 11. It is formed to be.
The collector electrode 16 is formed on the back surface of the back surface diffusion layer 15 (the surface in the upper direction of the back surface diffusion layer 15 in FIG. 1). In the npn-type bipolar transistor, the collector is formed by the drift layer 10, the base is formed by the base region 11, and the emitter is formed by the emitter region 12.

The first MOS transistor 104 is an n-channel MOS transistor, and is formed using the drift layer 10 as a drain, the emitter region 12 as a source, and a gate electrode 14. That is, in the main surface of the power semiconductor element (the lower surface in FIG. 1), the surface of the base region 11 sandwiched between the emitter region 12 and the drift layer 10 is used as a channel region. On the main surface of the base region 11, the ends overlap with the emitter region 12 and the drift layer 10 that are formed on the surfaces of the emitter region 12, the base region 11, and the drift layer 10 and face each other with the base region 11 interposed therebetween. It is formed to have a region.
Further, the gate electrode 14 is formed on the gate insulating film 13 so as to overlap the gate insulating film 13, that is, to be aligned in position.
The second MOS transistor 50 is an n-channel MOS transistor, and is formed as a gate electrode 18 with the MOS diffusion layer 150 as a drain and the drift layer 10 as a source. That is, since the gate insulating film 17 uses the side surface of the back surface diffusion layer 15 sandwiched between the drift layer 10 and the MOS diffusion layer 150 as a channel region, the drift layer 10 and the back surface diffusion layer 15 are formed on the side surface of the power semiconductor element. And the MOS diffusion layer 150 are formed so as to have regions where the end portions overlap each other with respect to the drift layer 10 and the MOS diffusion layer 150 that are opposed to each other with the back surface diffusion layer 15 interposed therebetween.
The gate electrode 18 is formed on the side surface of the power semiconductor device so as to overlap the gate insulating film 17, that is, to align with the position.

Next, the operation of the power semiconductor device according to the present embodiment will be described with reference to FIGS.
FIG. 2 is a conceptual diagram showing an equivalent circuit of the power semiconductor element of FIG.
In FIG. 2, a pnp transistor 101 is a pnp-type bipolar transistor. The emitter is a back diffusion layer 15, the base is a drift layer 10, and the emitter is a base region 11. The npn transistor 102 is an npn-type bipolar transistor, and includes a drift layer 10 as a collector, a base region 11 as a base, and an emitter region 12 as an emitter.

  Here, the emitter of the pnp transistor 101 is connected to the collector electrode 16, the base of the pnp transistor 101 is connected to the collector of the npn transistor 102, the collector of the pnp transistor 101 is connected to the base of the npn transistor 102, and resistance The emitter of the npn transistor 102 is grounded. In this configuration, when the first MOS transistor 104 is turned on, the pnp transistor 101 and the npn transistor 102 are sequentially turned on, and a current flows from the collector electrode 16 to the emitter electrode E.

  The first MOS transistor 104 is an n-channel MOS transistor, and includes a drift layer 10 as a drain, a base region 11 as a source, and a gate electrode 14 as a gate. As described above, the second MOS transistor 50 is an n-channel MOS transistor, and includes a MOS diffusion layer 150 as a drain, a drift layer 10 as a source, and a gate electrode 18 as a gate. The gate electrode 14 or the gate electrode 18 is formed of silicide using, for example, cobalt. Further, the gate electrode 18 may be configured as a two-layer structure in which aluminum is superimposed on the silicide.

Further, as shown in FIG. 1, the IGBT is in a state where the drift layer 10 and the back electrode layer 15 are overlaid on the first MOS transistor 104. Accordingly, the second MOS transistor 50 is turned on and the collector electrode 16 and the drift layer 10 are short-circuited, so that the collector electrode 16 and the drift layer 10 are in ohmic contact with each other, and the drift layer 10 in the pnp transistor 101 Therefore, the conductivity state of the MOS transistor is not dominant, but the operation state of the MOS transistor is dominant.
As described above, the present invention is characterized in that the second MOS transistor 50 is provided in order to short-circuit the collector electrode 16 and the drift layer 10 and cause the IGBT to function as a MOS transistor.

  Further, the collector electrode 16 of the power semiconductor element 30 is connected to the terminal Tc, the emitter electrode E is connected to the terminal TE, and a power source 23 is inserted between the terminal Tc and the terminal TE as a power source. The power source 23 is a battery in which a DC current generated by a Taiyo battery or the like is stored, for example. For example, when the DC (direct current) voltage of the power source 23 is supplied to household electric appliances, it is necessary to convert the DC (direct current) voltage into an AC (alternating current) voltage corresponding to a commercial power source by an inverter using an IGBT or the like. The power semiconductor element 30 in the present embodiment is used as a switching element constituting a bridge circuit that converts a DC voltage into an AC voltage (and performs power conversion) in the inverter.

In FIG. 2, a resistor 103 is an on-resistance of the first MOS transistor 104 and the second MOS transistor 50, and a resistor 105 is a resistor (base region 11) between the base of the npn transistor 102 and the terminal TE.
In FIG. 1, the switch SW1 inserted between the power source 22 and the terminal TG1 of the gate electrode 14 is turned on (conductive state), whereby “H” is applied from the power source 22 to the gate electrode 14 via the terminal TG1. A level voltage (= VG1) is applied, while an “L” level voltage (= ground potential, for example) is applied to the gate electrode 18 by turning off the switch SW1 (non-conductive state).
Further, by turning on the switch SW2 inserted between the power source 21 and the gate electrode 18, an "H" level voltage (= VG2) is applied from the power source 21 to the gate electrode 18 through the terminal TG2. On the other hand, by turning off the switch SW2, a voltage of “L” level (= ground potential) is applied to the gate electrode.

When operating the IGBT in the power semiconductor element 30 of the present embodiment in the operating state in the large current region such as at the time of full load, the second MOS transistor 50 is turned off by turning off the switch SW2. The same operation as that of a typical IGBT is performed.
That is, when the switch SW2 is turned off and the switch SW1 is turned on, the first MOS transistor 104 is turned on, and the drain current flows from the drift layer 10 to the emitter region 12 in the first MOS transistor 104. Decreases, a base current flows through the pnp transistor 101, and the pnp transistor 101 is turned on.

Here, in the pnp transistor 101, conductivity modulation occurs due to the operation of the bipolar transistor, and the resistance value of the drift layer 10 decreases. As a result, even if the collector current flowing through the IGBT increases, carriers are injected into the drift layer 10, conductivity modulation occurs, and the voltage between the collector (collector electrode 16) and the emitter (emitter electrode E) due to the collector current increase. Rise is suppressed.
When the current flows through the resistor 105, the potential at the connection point B increases, a current flows between the base and the emitter of the npn transistor 102, the voltage at the connection point A decreases, and the collector current of the pnp transistor 101 decreases. Will increase.

On the other hand, in the operation state of the small current region such as during partial load, when the power semiconductor element 30 of this embodiment performs the operation of the MOS transistor, the second MOS transistor 50 is turned on by turning on the switch SW2. Thus, an operation similar to that of a general MOS transistor is performed.
That is, when the switch SW2 is turned on and the switch SW1 is turned on, the first MOS transistor 104 is turned on, and the drain current flows from the drift layer 10 to the emitter region 12 in the first MOS transistor 104.
Here, the drain current of the first MOS transistor 104 flows through the second MOS transistor 50, the potential at the connection point A does not decrease, the base current does not flow through the pnp transistor 101, and the pnp transistor 101 is turned on. It is hard to be in a state.

However, when the current that flows through the load increases and the current that can flow through the first MOS transistor 104 increases as compared with the current that can flow through the second MOS transistor 50, the potential at the connection point A decreases, and the base current of the pnp transistor 101 flows. The pnp transistor 101 is turned on, and the operation state of the IGBT is shifted.
Therefore, the load current that shifts from the operation of the MOS transistor to the operation of the IGBT is determined by the values of the on-resistances of the first MOS transistor 104 and the second MOS transistor 50.
In the present embodiment, when the power semiconductor element 30 is operated, the small current region indicates a current range below the load current in which the loss energy in the IGBT operation exceeds the loss energy in the MOS transistor, while the large current region is A current range in which the loss energy in the MOS transistor operation exceeds the load current exceeding the loss energy in the IGBT is shown.

As described above, by operating the power semiconductor element 30 as a MOS transistor or IGBT depending on the amount of current flowing through the load, as shown below, the energy loss of the IGBT in a low-capacity small current region such as during partial load Both the energy loss of the MOS transistor in a large-capacity, large-current region such as at full load can be reduced.
That is, as shown in FIG. 3, the on-characteristics of the IGBT are such that the collector (collector electrode 16) -emitter depends on the junction potential of the pn junction in a small current region (current range caused by partial load) where the load current (collector current) is small. It is limited by the lower limit value of the voltage between (emitter electrode E) (threshold voltage at the collector-emitter junction potential at which current starts to flow through the power semiconductor element 30). Energy does not flow and energy is lost.
On the other hand, in the large current region, carriers are injected from the back diffusion layer 15 into the drift layer 10, and the pnp transistor 101 and the npn transistor 102 are turned on, that is, collector (collector electrode 16) -emitter (emitter) by conductivity modulation. The voltage between the electrodes E) does not increase, and a large collector current can flow through the IGBT. In FIG. 3, the horizontal axis indicates the voltage value of the voltage VCE between the collector electrode 16 and the emitter electrode E in the power semiconductor element 30, and the vertical axis indicates between the collector electrode 16 and the emitter electrode E in the power semiconductor element 30. The current value of the flowing collector current is shown.

However, unlike the IGBT, the on characteristics of the MOS transistor have no junction potential because there is no pn junction, and the ohmic resistance of the drift layer 10 is dominant as the on resistance.
For this reason, since the MOS transistor has no junction potential at the pn junction, a current flows even in a small current region. Therefore, as shown in FIG. 4, energy loss between the collector and the emitter (collector electrode 16 and emitter electrode E) occurs. There is no.
However, in the large current region, the load current increases according to the resistance value of the ohmic resistance of the drift layer 10, and the energy loss increases due to the power consumed by the drift layer 10 as a load. It becomes. In FIG. 4, the horizontal axis indicates the voltage value of the voltage VDS between the drift layer 10 and the emitter electrode E, and the vertical axis indicates the current value between the drift layer 10 and the emitter electrode E.

  Therefore, as shown in FIG. 5, a threshold value is set in advance for the current value of the load current, and is operated as a MOS transistor with less energy loss than the IGBT in a small current region of the load current below the threshold value. By operating as an IGBT with less energy loss than the MOS transistor in the large current region of the load current exceeding the threshold, the present embodiment is able to achieve the entire load current from the low power region to the large current region. A power semiconductor element with low energy loss (conduction loss) in the range is realized. FIG. 5 is the same as FIG. 3 for the IGBT and the same as FIG. 4 for the MOS transistor (MOSFET). Here, in the present embodiment, the threshold value for the load current is set to a current value at which the energy loss in the MOS transistor operation exceeds the energy loss in the bipolar operation (IGBT operation).

6 is applied to an IPM (Intelligent Power Module) 81 having the configuration shown in FIG. 6 from an AC power supply 80 to change the resistance value of the resistive load 82 and control the numerical value of the load current. The energy loss due to the operation by the IGBT and the operation by the IGBT was obtained by simulation. The configuration of the IPM 81 will be described in detail with reference to FIG.
In this simulation, the conduction loss is obtained from the equation “conduction voltage × conduction current × conduction time”, the switching loss is obtained from the equation “applied voltage × conduction current × switching time / 6”, and the conduction loss and switching of the AC half cycle are calculated. Energy loss was calculated from the total loss. Here, the conduction voltage is a voltage between the collector (collector electrode 16) and the emitter (emitter electrode E), the conduction current is a load current, the conduction time is a time during which the element is on, and the applied voltage Is the voltage applied to the collector electrode 16, and the switching time is the time for switching from the on state to the off state (measured by the current value) during switching.
The operating condition of FIG. 7 is that the resistance value of the resistive load 82 is 30Ω, and switching is performed at a duty of 50% at a frequency of 5 kHz, while the operating condition of FIG. 50% duty switching is performed at the same frequency. 7 and 8, the horizontal axis represents time, and the vertical axis represents the current value flowing through the resistance load.

9 is the same as FIGS. 7 and 8 described above, and the load current peaks at 2 A (amperes), 5 A, 10 A, 20 A, 30 A, 40 A, and 50 A at a duty of 50% at a driving frequency of 5 kHz. As described above, the energy loss of the IGBT, the MOS transistor, and the power semiconductor element 30 in this embodiment is calculated by changing the resistance load 82, and the energy loss of the IGBT at each load current value is set to 1, and the energy loss is normalized. It is a figure, the horizontal axis shows the current value of the load current, and the vertical axis shows the energy loss normalized by the energy loss of the IGBT.
Here, GT80J101B (manufactured by Toshiba) as the IGBT, 2SK3911 (manufactured by Toshiba) as the MOS transistor, and the energy loss of the present embodiment uses the characteristics of 2SK3911 in the region where the load current is 5 A or less, and the load current exceeds 5 A. The characteristics of GT80J101B were used in the region.

As can be seen from FIG. 9, the IGBT has a larger energy loss than the MOS transistor in a small current region of a load current of 5 A or less. However, in the MOS transistor, as the load current increases, the energy loss also increases proportionally. Therefore, in the large current region of the load current exceeding 5 A, the energy loss of the IGBT is exceeded.
On the other hand, the power semiconductor device according to the present embodiment exhibits characteristics similar to those of a MOS transistor in a small current region of a load current of 5 A or less, has lower energy loss than an IGBT, and in a large current region of a load current exceeding 5 A. The same specification as that of the IGBT is shown, and it is shown that a power semiconductor element with less energy loss (conduction loss) in the entire range from the low current region to the large current region of the load current can be realized.

FIG. 10 shows a cross-sectional structure of another configuration example of the power semiconductor device according to the present embodiment. The second MOS transistor 50 in FIG. 1 is formed not only in the outer peripheral portion of the power semiconductor element but also in the vicinity of the center portion of the back diffusion layer 15.
That is, on the back surface of the back diffusion layer 15, one or a plurality of MOS diffusion layers 150 are formed on the surface in the vicinity of the central portion of the back diffusion layer 15, and penetrate the central portion of the MOS diffusion layer 150. A groove (trench) 30 having a depth that penetrates the diffusion layer 15 and reaches the drift layer 10 at the bottom is formed. Then, the gate insulating film 17 is formed on the entire inner surface of the groove 35, the gate electrode 18 is formed on the gate insulating film 17, and the channel region of the MOS transistor that increases the gate width of the second MOS transistor 50 is formed in the groove 35. Is formed on the inner surface of the groove 35, that is, the inner surface of the groove 35.
As a result, the amount of current flowing from the collector electrode 16 into the drift layer 10 increases, so that the on-resistance of the second MOS transistor can be reduced. When the power semiconductor element 30 is operated as a MOSMOS transistor, the current resistance is compared with FIG. Thus, it becomes possible to further reduce energy loss.

Next, FIG. 11 shows a configuration example of the IPM 81 using the power semiconductor element 30 shown in FIG. 1 or FIG. A reverse conducting diode 60 is provided between the terminal Tc (collector side) and the terminal TE (emitter) side. Here, the reverse conducting diode 60 has a cathode connected to the terminal Tc and an anode connected to the terminal TE.
The gate drive circuit 73 outputs, to the terminal TG1 of the power semiconductor element 30 (the gate electrode 14 of the first MOS transistor 104), a drive signal corresponding to a control signal for switching input from the outside of the IPM via the terminal TG. At this time, since the first MOS transistor 104 is an n-channel MOS transistor, the gate drive circuit 73 corresponds to the control signal, and when the control signal power semiconductor element 30 is turned on, it is equal to or higher than the threshold of the first MOS transistor 104 (“ When the control signal power semiconductor element 30 is turned off, a drive signal less than the threshold value (“L” level) of the first MOS transistor 104 is output.

  The gate drive circuit 74 controls the power semiconductor element 30 to operate as a MOS transistor or as an IGBT with respect to the terminal TG2 of the power semiconductor element 30 (the gate electrode 18 of the second MOS transistor 50). A drive signal corresponding to the switching control signal input from is output. At this time, since the second MOS transistor 50 is an n-channel MOS transistor, the gate drive circuit 74 corresponds to the control signal, and when the second MOS transistor 50 is turned on, it is equal to or higher than the threshold value of the second MOS transistor 50 (“H”). On the other hand, when the second MOS transistor 50 is turned off, a drive signal less than the threshold (“L” level) of the second MOS transistor 50 is output.

The control circuit 72 measures the load current flowing through the power semiconductor element 30 with the current sensor 71, and compares the measured current value with a threshold value (threshold value of the load current value) set inside.
Here, when the measured current value is less than or equal to the threshold value, the control circuit 72 outputs a switching signal indicating that the power semiconductor element 30 operates as a MOS transistor to the gate drive circuit 74, while the measured current value is When the threshold value is exceeded, a switching signal indicating that the power semiconductor element 30 is to perform the IGBT operation is output to the gate drive circuit 74.

Further, the threshold value of the load current for determining the operation switching of the MOS transistor or IGBT is determined at the stage of designing the power semiconductor element 30.
That is, according to the simulation for obtaining the energy loss already described based on the IV characteristics of the IGBT obtained from the simulation results and the IV characteristics of the second MOS transistor 50, the energy loss in the MOS transistor operation is the energy in the IGBT operation. A load current value exceeding the loss is obtained, and a numerical value of a load signal for driving the second MOS transistor 50 is set as a threshold value and set in the control circuit 72 in advance.

Further, as described above, the threshold value is not set at the stage of designing the power semiconductor element 30, but the threshold value is set when the IPM including the power semiconductor element 30 is assembled as an inverter or the like and shipped from the factory. .
That is, in the shipping inspection, the operation test of the inverter is performed while adjusting the threshold value, that is, adjusting the timing of turning on / off the second MOS transistor 50 (timing in the change of the current value of the load current). The threshold value at which the energy loss due to 30 is the lowest may be extracted, and the extracted threshold value may be set in the control circuit 72.

Further, not only the current sensor 71 but also a voltage sensor is provided between the terminal Tc and the terminal TE, and the control circuit 72 uses the current value measured by the current sensor 71 and the voltage value measured by the voltage sensor, You may comprise so that electric power may be calculated.
In this configuration, the control circuit 72 changes the threshold value for each period in which the first MOS transistor 104 is turned on or in units of a plurality of periods, and controls the power to be lower than the value obtained immediately before.

That is, when the control circuit 72 increases the numerical value of the threshold, when the power obtained from the measured current value and voltage value increases from the power obtained in the previous measurement, the control circuit 72 decreases the threshold, When the power obtained from the measured current value and voltage value is smaller than the power obtained in the previous measurement, the threshold is increased again.
The control circuit 72 increases the threshold value when the power value obtained from the measured current value and voltage value increases from the power value obtained in the immediately preceding measurement when the threshold value is decreased. When the power obtained from the measured current value and voltage value is smaller than the power obtained in the previous measurement, the threshold value is decreased again.

  In the inverter using the power semiconductor element 30 according to the present embodiment, the control signal based on the half-wave waveform shown in FIG. 12 is supplied to the gate electrode 14 of the first MOS transistor 104 in the switching of each first MOS transistor 104. By doing so, the power semiconductor element 30 can be efficiently switched by the set threshold value between the case where the MOS transistor (MOSFET) operation is easily performed and the case where the IGBT operation is performed.

  As described above, the power semiconductor element 30 is used for an inverter or the like by adjusting the threshold value for controlling whether to operate the MOS transistor or the IGBT so as to reduce the energy loss. In the low load current region, power conversion can be performed with higher efficiency than in the conventional example.

In the above description, the control circuit 72 compares the threshold value set inside with the load current to switch the power semiconductor element 30 to the MOS transistor operation or the IGBT operation corresponding to the load current. Instead, the gate electrode 18 of the second MOS transistor 50 may be fixed in advance in a state where a voltage higher than a threshold value for turning on the second MOS transistor 50 is applied.
In this case, in FIG. 2, in the low load current region, the potential at the connection point A does not decrease, the pnp transistor 101 does not turn on, and the load current increases and the potential at the connection point A decreases. As a result, a base current flows through the pnp transistor 101 and the pnp transistor 101 is turned on, so that the MOS transistor operation is shifted to the IGBT operation.

  In this configuration, for example, in the design stage of the power semiconductor element 30, the second MOS transistor is based on characteristics such as the on-resistance of the second MOS transistor 50, the resistance of the drift layer 10, and the on-resistance of the first MOS transistor 104. It is necessary to adjust the voltage value applied to the 50 gate electrodes 18 so that the switching between the MOS transistor operation or the IGBT operation is performed with the current value of the load current with little energy loss in each region.

<Second Embodiment>
Next, a power semiconductor device according to a second embodiment will be described with reference to the drawings. FIG. 13 is a conceptual diagram showing a cross-sectional structure of the power semiconductor device according to the second embodiment, and corresponds to the configuration of the first embodiment of FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. A configuration different from the first embodiment of FIG. 1 will be described below.
The drift layer 10 is an n-type substrate to which an n-type impurity is added. Base region 11 to which a p-type impurity is added is formed on the main surface of drift layer 10 (the surface in the lower direction of drift layer 10 in FIG. 13).
Further, the main surface of the base region 11 (the surface in the lower direction of the drift layer 10 in FIG. 13) is such that the n-type emitter region 12 terminates in the base region 11, that is, is completely included. Is formed. That is, emitter region 12 is thinner than base region 11, is included in base region 11 in the thickness direction, and is included in base region 11 in a plan view viewed from the direction perpendicular to the main surface of base region 11. It is formed to be. The configuration of the first MOS transistor 104 is the same as that of the first embodiment.

Since the surface of the base region 11 sandwiched between the emitter region 12 and the drift layer 10 serves as a channel region on the main surface of the power semiconductor element (the lower surface in FIG. 13), the gate insulating film 13 11 is formed on the surface of the emitter region 12, the base region 11, and the drift layer 10, and has a region where ends overlap with the emitter region 12 and the drift layer 10 that are opposed to each other through the base region 11. It is formed to have. An emitter electrode E is connected to the base region 11 and the emitter region 12.
Further, the gate electrode 14 is formed on the gate insulating film 13 so as to overlap the gate insulating film 13, that is, to be aligned in position.

Similarly, a back surface diffusion region 51 (corresponding to the back surface diffusion layer 15) to which a p-type impurity is added is formed on the back surface of the drift layer 10 (the surface in the upward direction of the drift layer 10 in FIG. 13).
Further, the n-type MOS diffusion layer 52 is completely included in the main surface of the back surface diffusion region 51 (the surface in the upper direction of the drift layer 10 in FIG. 13) so as to terminate in the back surface diffusion region 51, that is, completely. It is formed as follows. That is, the MOS diffusion layer 52 is thinner than the back surface diffusion region 51 and is included in the back surface diffusion region 51 in the thickness direction, and the back surface diffusion region in a plan view viewed from the direction perpendicular to the main surface of the back surface diffusion region 51. 51 to be included.
A part of the surface of the n-type substrate of drift layer 10 is exposed at the main surface and the back surface of drift layer 10.
Since the surface of the back surface diffusion region 51 sandwiched between the MOS diffusion layer 52 and the drift layer 10 is used as a channel region on the back surface of the power semiconductor element (the surface in the upper direction in FIG. 13), the gate insulating film 53 has a back surface diffusion. On the main surface of region 51, MOS diffusion layer 52 (corresponding to MOS diffusion layer 150), back surface diffusion region 51, and drift layer 10 are formed on the surface, and are opposed to each other through back surface diffusion region 51. The drift layer 10 is formed to have a region where end portions overlap each other. A collector electrode 56 (corresponding to the collector electrode 16) is connected to the back surface diffusion region 51 and the MOS diffusion layer 52.
Further, the gate electrode 54 (corresponding to the gate electrode 18) is formed on the gate insulating film 53 (corresponding to the gate insulating film 17) so as to overlap the gate insulating film 53, that is, to be aligned in position. Yes.

As described above, in the present embodiment, the second MOS transistor 50 is formed in the same configuration as the first MOS transistor 104. That is, the IGBT has a plane-symmetric structure with a plane perpendicular to the direction in which the current flows (the longitudinal direction of the IGBT in FIG. 13) as a symmetry plane.
In the forward direction in which current flows in the direction of arrow F in the IGBT operation mode, the back diffusion region 51 is the collector, the drift layer 10 is the base, and the base region 11 is the emitter as the configuration of the pnp transistor 101 shown in FIG. In the npn transistor 102 configuration, the drift layer 10 operates as a collector, the base region 11 operates as a base, and the emitter region 12 operates as an emitter.
On the other hand, in the reverse direction in which current flows in the direction of arrow R, the pnp transistor 101 has a configuration in which the base region 11 operates as an emitter, the drift layer 10 operates as a base, and the back diffusion region 51 functions as a collector. As a result, the drift layer 10 operates as a collector, the back diffusion region 51 serves as a base, and the MOS diffusion layer 52 serves as an emitter. When a current is passed in the reverse direction, the operation relationship between the first MOS transistor 104 and the second MOS transistor 50 is reversed similarly to the operation relationship between the pnp transistor 101 and the npn transistor 102.

  As can be seen from the description of FIG. 13 described above, the first MOS transistor 104 formed on the main surface of the drift layer 10 and the second MOS transistor 50 formed on the back surface of the drift layer 10 have the same configuration. With this configuration, it operates as a bidirectional IGBT that allows current to flow in both directions. In the case of the present embodiment, a voltage is applied between the collector electrode 56 and the emitter electrode E so that a current flows in both directions, that is, the polarity of the potential difference between the collector electrode 56 and the emitter electrode E is reversed. It will be used in the state that is done. For example, instead of the DC power source 23, an AC voltage or the like is applied between the collector electrode 56 and the emitter electrode E by the AC power source 230. A control circuit (not shown) causes current to flow from one to the other in the collector electrode 56 and the emitter electrode E depending on whether the AC waveform from the AC power supply 230 has a positive polarity or the AC waveform is −. Then, control for switching the direction of current flow is performed on the IGBT.

  Therefore, the switch SW1 is configured such that the terminal TG1 is connected to either the terminal TG1P or the terminal TG1M. The terminal TG1P is connected to the output of the power supply 22P (+ voltage power supply), and the terminal TG1M is connected to the output of the power supply 22M (−voltage power supply). Here, for example, the power supply 22P is a positive voltage (15V), and when the terminal TG1 and the terminal TG1P are in a conductive state, the first MOS transistor 104 is turned on. On the other hand, the power supply 22M is a negative voltage (0 V or less, for example, −15 V). When the terminal TG1 and the terminal TG1M are in a conductive state, the first MOS transistor 104 is turned off.

  Similarly, the switch SW2 is configured such that the terminal TG2 is connected to either the terminal TG2P or the terminal TG2M. The terminal TG2P is connected to the output of the power supply 21P (+ voltage power supply), and the terminal TG2M is connected to the output of the power supply 21M (−voltage power supply). The power supply 21P is a positive voltage (15V), and when the terminal TG2 and the terminal TG2P are brought into conduction, the second MOS transistor 50 is turned on. On the other hand, the power source 21M is a negative voltage (−15V), and when the terminal TG2 and the terminal TG2M are brought into conduction, the second MOS transistor 50 is turned off.

Next, the operation of the power semiconductor device according to the present embodiment will be explained with reference to FIG. In the following description, in FIG. 13, the direction of arrow F (current flow direction) is assumed to be the forward direction, and the direction of arrow R (current flow direction) is assumed to be the reverse direction.
A, forward direction (voltage of collector electrode 56> voltage of emitter electrode E)
a. Operation in IGBT Mode The switch SW1 is controlled so that the terminal TG1 and the terminal TG1P are connected and become conductive, and the switch SW2 is controlled so that the terminal TG2 and the terminal TG2M are connected.
As a result, the first MOS transistor 104 is turned on, the second MOS transistor 50 is turned off, and the current from the AC power supply 230 flows through the back electrode diffusion region 51, the drift layer 10, and the emitter region 12 via the collector electrode 56, It flows into the emitter electrode E.
b. Operation in MOSFET Mode The switch SW1 is controlled so that the terminals TG1 and TG1P are connected to be in a conductive state, and the switch SW2 is controlled so that the terminals TG2 and TG2P are connected to be in a conductive state.
As a result, the first MOS transistor 104 and the second MOS transistor 50 are turned on, and the current from the AC power supply 230 flows through the channel region of the second MOS transistor 50 and the drift layer 10 via the collector electrode 56. Flows into the emitter electrode E through the channel region.

B, reverse direction (collector electrode 56 voltage <emitter electrode E voltage)
a. Operation in IGBT Mode The switch SW1 is controlled so that the terminal TG1 and the terminal TG1M are connected and become conductive, and the switch SW2 is controlled so that the terminal TG2 and the terminal TG2P are connected.
As a result, the first MOS transistor 104 is turned off, the second MOS transistor 50 is turned on, and the current from the AC power supply 230 flows through the emitter region 11, the drift layer 10, and the back surface diffusion region 51 via the emitter electrode E, It flows into the collector electrode 56.
b. Operation in MOSFET Mode The switch SW1 is controlled so that the terminals TG1 and TG1P are connected to be in a conductive state, and the switch SW2 is controlled so that the terminals TG2 and TG2P are connected to be in a conductive state.
As a result, the first MOS transistor 104 and the second MOS transistor 50 are turned on, and the current from the AC power supply 230 flows through the emitter electrode E through the channel region of the first MOS transistor 104 and the drift layer 10. Flows into the collector electrode 56 through the channel region.

<Third Embodiment>
Next, a matrix converter according to a third embodiment using the bidirectional power semiconductor element according to the second embodiment will be described with reference to the drawings. FIG. 14 is a conceptual diagram illustrating a configuration example of a matrix converter according to the third embodiment. In FIG. 14, the power flow (flow for supplying power) is performed from the three-phase AC power source 200 to the three-phase load 250.
One end of the coil (201, 202, 203) is connected from the three-phase AC power source 200 to the output of each AC phase (U, V, W), and the output of each phase is connected to the coil from the other end of the coil. Is output via.
A capacitor 206 is connected between the other ends of the coil 201 and the other end of the coil 202 corresponding to the outputs of each phase, for example, the U phase and the V phase, and the coils corresponding to the outputs of the V phase and the W phase. A capacitor 207 is connected between the other end of 202 and the other end of the coil 203, and a capacitor 205 is connected between the other end of the coil 201 and the other end of the coil 203 corresponding to the U-phase and W-phase outputs. The

Bidirectional IGBTs 221, 222, and 223 are power semiconductor elements according to the third embodiment. One end of each is connected in common to the R-phase terminal of the three-phase load 250, and the other end is a coil 201. The other end of the coil 202, the other end of the coil 202, and the other end of the coil 203.
Similarly, the bidirectional IGBTs 231, 232, and 233 are also power semiconductor elements in the third embodiment, and one end of each is connected in common to the S-phase terminal of the three-phase load 250, and the other end Are connected to the other end of the coil 201, the other end of the coil 202, and the other end of the coil 203.
Similarly, the bidirectional IGBTs 241, 242, and 243 are also power semiconductor elements in the third embodiment, and one end of each is connected in common and connected to the T-phase terminal of the three-phase load 250. Each of the other ends is connected to the other end of the coil 201, the other end of the coil 202, and the other end of the coil 203.

A control unit (not shown) is configured to operate the bidirectional IGBTs 221, 222, 223, and the like so that the AC output of the three-phase AC power supply 200 has a preset frequency with respect to the three-phase AC load 250 from the three-phase AC power supply 200. Switching control of 231, 232, 233, 241, 242, 243 is performed.
As a result, the first MOS transistor 104 and the second MOS transistor 50 in each bidirectional IGBT are turned on / off, perform MOS transistor operation or IGBT operation, and forward or reverse from the three-phase AC power supply 200 to the three-phase AC load 250. A current is passed in the reverse direction, and variable frequency AC power is output to the three-phase AC load 250.

<Fourth Embodiment>
Next, a power semiconductor device according to a fourth embodiment will be described with reference to the drawings. FIG. 15 is a conceptual diagram showing a cross-sectional structure of the power semiconductor device according to the fourth embodiment, and corresponds to the configuration of the second embodiment of FIG. In the fourth embodiment, the configuration of the first MOS transistor 104 and the second MOS transistor 50 is the same as the configuration of the second MOS transistor 50 shown in FIG. 10 in the first embodiment.
That is, the back surface diffusion layer 51 is formed on the back surface side (upper part of the drawing) of the drift layer 10 which is an n-type semiconductor layer, and the back surface side of the back surface diffusion layer 15 (upper surface side of the back surface diffusion layer 15 in FIG. 15). ), An n-type MOS diffusion layer 150 having a predetermined width and a predetermined depth is formed along the outer peripheral portion of the rear surface.
Similarly to the second MOS transistor 50 shown in FIG. 10, not only the outer peripheral portion of the back surface but also the inner region of the back surface is separated by a predetermined distance on the back surface of the back diffusion layer 15. A plurality of MOS diffusion layers 150 are formed.
A trench 35 that penetrates the MOS diffusion layer 150 and the back surface diffusion layer 15 from the back surface side of the back surface diffusion layer 150 and reaches the drift layer 10 at the center of the MOS diffusion layer 150 formed in the internal region of the back surface. Form.

Here, the second MOS transistor 50 is an n-channel MOS transistor. The MOS diffusion layer 150 serves as a drain, the drift layer 10 serves as a source, and the MOS diffusion layer is formed on the side wall of the power semiconductor element 30 and the outer peripheral surface of the trench 35. A portion of the back diffusion layer 15 sandwiched between 150 and the drift layer 10 is used as a channel region.
Therefore, the gate insulating film 17 is formed at a position corresponding to the drift layer 10, the back surface diffusion layer 15, and the MOS diffusion layer 150 with respect to the side wall of the power semiconductor element 30. The gate oxide film 17 is formed so that the end portion of the gate oxide film 17 overlaps the side surface of the MOS diffusion layer 150 and the drift layer 10 which are formed to face each other with the back surface diffusion layer 15 therebetween as viewed from the side surface. The gate insulating film 35 is also formed on the entire inner surface of the trench 35.
The gate electrode 18 is formed so as to overlap the gate insulating film 17, that is, to be aligned in position. Further, the collector electrode 16 is formed on the back surface of the back surface diffusion layer 15 in a region including the surface of the MOS diffusion layer 150 (excluding the opening portion of the trench 35). Back diffusion layer 15

Similarly, a base region 11 is formed on the main surface side (lower part of the figure) of the drift layer 10 which is an n-type semiconductor layer, and the main surface side (in FIG. 15) of the base region 11 (base layer). An n-type emitter region 12 having a predetermined width and a predetermined depth is formed along the outer peripheral portion of the main surface side surface on the surface on the lower surface side of the base region 11.
Similarly to the second MOS transistor 50 shown in FIG. 10, not only the outer peripheral portion of the main surface side surface but also the inner region of the main surface side surface is separated by a predetermined distance on the main surface side of the base region 11. A plurality of emitter regions 12 are formed.
A trench 55 that penetrates the emitter region 12 and the base region 11 from the main surface side of the emitter region 12 and reaches the drift layer 10 is formed in the central portion of the emitter region 12 formed in the inner region of the main surface side surface. To do.

Similarly, here, the first MOS transistor 104 is an n-channel MOS transistor, the emitter region 12 is used as a drain, the drift layer 10 is used as a source, and on the side wall of the power semiconductor element 30 and the outer peripheral surface of the trench 55. The portion of the base region 11 sandwiched between the emitter region 12 and the drift layer 10 is used as a channel region.
Therefore, the gate insulating film 13 is formed on the surfaces of the drift layer 10, the base region 11, and the emitter region 12 on the sidewall of the power semiconductor element 30. The gate oxide film 13 is formed so that the end portion of the gate oxide film 13 overlaps the side surface of the emitter region 12 and the drift layer 10 that are formed to face each other with the berth region 11 therebetween when viewed from the side surface. The gate insulating film 13 is also formed on the entire inner surface of the trench 55.
The gate electrode 14 is formed so as to overlap the gate insulating film 13, that is, to be aligned in position. Further, an emitter electrode E is formed on the main surface side of the base region 11 in a region including the surface of the emitter region 12 (excluding the opening portion of the trench 55).
In addition, the operations of the first MOS transistor and the second MOS transistor in the fourth embodiment are the same as the operations of the first MOS transistor and the second MOS transistor in the second embodiment, and thus description of the operation is omitted. Similarly to the second embodiment, this embodiment can also be used for the matrix converter of the third embodiment.

DESCRIPTION OF SYMBOLS 10 ... Drift layer 11 ... Base area | region 12 ... Emitter area | region 13, 17, 53 ... Gate insulating film 14, 18, 54 ... Gate electrode 15 ... Back surface diffused layer 16, 56 ... Collector electrode 21, 22, 23, 21M, 22P, 22M, 22P ... Power supply 30 ... Power semiconductor element 35, 55 ... Trench (groove)
DESCRIPTION OF SYMBOLS 50 ... 2nd MOS transistor 51 ... Back surface diffusion area 52,150 ... MOS diffusion layer 71 ... Current sensor 72 ... Control circuit 73, 74 ... Gate drive circuit 80, 230 ... AC power supply 81 ... IPM
82 ... Resistance load 101 ... pnp transistor 102 ... npn transistor 103, 105 ... resistor 104 ... first MOS transistor 200 ... three-phase AC power supply E ... emitter electrodes SW1, SW2 ... switch

Claims (10)

A first MOS transistor that causes a base current of a bipolar transistor in the IGBT to flow and causes the IGBT to perform a switching operation;
The base potential of the bipolar transistor is controlled by an on / off operation. When performing a switching operation, the base current is supplied to the base of the bipolar transistor to operate as an IGBT or to operate only the first MOS transistor. And a second MOS transistor that controls whether to operate as a MOS transistor.
A drift layer of a first conductivity type;
A base region of a second conductivity type formed on the main surface side of the drift layer;
An emitter region of a first conductivity type formed at the surface of the base region so as to terminate in the base region;
A back diffusion layer of a second conductivity type formed on the back side of the drift layer;
In the back diffusion layer, a first conductivity type MOS diffusion layer formed on the back diffusion layer surface;
The base region between the emitter region and the drift layer is a first channel region of the first MOS transistor, and a first gate insulating film formed on the surface of the second channel region;
An emitter electrode connected to the emitter region and the base region;
A first gate electrode formed on the first gate insulating film;
A collector electrode formed on the back diffusion layer and the MOS diffusion layer;
A surface of the back diffusion layer between the drift layer and the MOS diffusion layer as a second channel region of the second MOS transistor, and a second gate insulating film formed on the surface of the second channel region;
A power semiconductor element comprising: a second gate electrode formed on the second gate insulating film. Forming a first MOS transistor comprising the first gate electrode having the drift layer as a drain, the emitter region as a source, and the base region surface as a channel formation region;
A second MOS transistor comprising a second gate electrode having the MOS diffusion layer as a drain, the drift layer as a source, and the back diffusion layer as a channel region;
When the MOS transistor operation is performed, when the first MOS transistor is turned on, the second MOS transistor is turned on. On the other hand, when the bipolar operation is performed, when the first MOS transistor is turned on, 2. The power semiconductor device according to claim 1, wherein the second MOS transistor is turned off.   From the back surface of the back surface diffusion layer, a groove that penetrates through the MOS diffusion layer and reaches the drift layer is formed, the second gate insulating film is formed on the inner surface of the groove, and the second gate insulating film is formed on the second gate insulating film. 3. The power semiconductor device according to claim 1, wherein the second gate electrode is provided, and an inner peripheral surface inside the groove in the collector layer is used as the second channel region. 4.   In the second MOS transistor, the surface of the back diffusion layer between the drift layer and the MOS diffusion layer is formed as the second channel region, and a plane perpendicular to the direction of current flow is symmetrical with respect to the first MOS transistor. The power semiconductor element according to claim 1, wherein the power semiconductor element has a plane symmetrical structure. In the first MOS transistor,
From the surface of the base region, a first groove penetrating the emitter region and reaching the drift layer is formed, the first gate oxide film is formed in the first groove, and the first The first gate electrode is provided in the form of a gate oxide film, and the inner peripheral surface inside the first groove in the emitter region is used as the first channel region,
In the second MOS transistor,
Forming a groove reaching the drift layer from the back surface of the collector layer, forming the second gate insulating film on the inner surface of the groove, and providing the second gate electrode on the second gate insulating film; The power semiconductor element according to claim 4, wherein an inner peripheral surface inside the groove in the collector layer is the second channel region. In the forward operation in which current flows from the collector electrode to the emitter electrode, in the case of bipolar transistor operation, the first MOS transistor is turned on, the second MOS transistor is turned off, and in the case of MOS transistor operation, the first MOS transistor is turned on. 1MOS transistor is turned on, 2nd MOS transistor is turned on,
In the reverse operation in which current flows from the emitter electrode to the collector electrode, in the case of bipolar transistor operation, the first MOS transistor is turned off, the second MOS transistor is turned on, and in the case of MOS transistor operation, the first MOS transistor is turned on. The power semiconductor element according to claim 4, wherein the first MOS transistor is turned on and the second MOS transistor is turned on. The power semiconductor element according to any one of claims 1 to 6,
A current sensor for measuring a current flowing through the power semiconductor element;
It is determined whether or not the measured current measured by the current sensor exceeds a preset threshold value.If the measured current exceeds the threshold value, the power semiconductor element is operated as a bipolar transistor. An intelligent power module comprising: a control circuit that outputs a control signal to the first gate electrode so as to operate as a MOS transistor.   The control circuit increases or decreases a current range for operating the power semiconductor element as a MOS transistor according to the control signal every time the power semiconductor element is switched, and the power consumption of the power semiconductor element obtained from the measurement current is further increased. The intelligent power module according to claim 7, wherein the current range of the threshold value is adjusted to be small.   A bipolar transistor comprising the power semiconductor element according to any one of claims 1 to 6, wherein a control signal for operating as a MOS transistor is always applied to the second gate electrode, and a current flowing through the power semiconductor element is increased. Intelligent power module characterized by operating as A plurality of power semiconductor elements that allow current to flow in both directions according to any one of claims 4 to 6,
The power output from the power supply is controlled to switch the first MOS transistor and the second MOS transistor in the power semiconductor element, and a current is passed in the forward direction or the reverse direction in the MOS transistor operation or the IGBT operation, so that the variable frequency with respect to the load Matrix converter that outputs AC power.

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