JP6098066B2 - PCI bus control system and PCI bus control method - Google Patents

Description

The present invention uses the PCI bus (Peripheral Component Interconnect Bus), a method of controlling the PCI bus control system and a PCI bus for transferring data.

  When a plurality of devices are connected to the PCI bus using PCI slots and a memory on the motherboard (on the host control unit) is accessed, the memory is accessed via a host bridge built on the motherboard. For example, when a printer device is used as a device, a video transfer circuit of the printer device is connected to a PCI slot, and a memory on the motherboard is accessed via the PCI bus.

  For example, when there is a data read request (REQ) from the device side, the host bridge accesses the memory, prepares the requested data, and sends a retry response (STOP) to the device until it is ready for transmission. When a data read request is made from the device side after that, when preparation for transmission is completed, a response (TRDY) indicating that transmission is possible is performed, and thereafter data is transmitted from the memory to the device side.

  However, today, the processing of the CPU and memory on the motherboard side has been accelerated, the operating frequency with the PCI bus is different, and there are many cases where they are asynchronous. In this case, the CPU on the motherboard side and the control unit on the PCI device side operate at different clock frequencies, and corresponding processing time is required.

  Note that Patent Document 1 measures the time until the retry is canceled, and improves access efficiency by masking the re-access from the corresponding PCI device until the time measured from the first access elapses. The invention to be disclosed is disclosed.

JP 2000-207354 A

  In the conventional PCI bus control method, when there is a second or subsequent data read request from the PCI device, the data is transmitted from the memory to the PCI device as soon as the data is prepared on the motherboard side. However, even if data is transferred from the motherboard side, if the prepared data amount is halfway, the data transfer process is interrupted and the data transfer is delayed.

Therefore, an object of the present invention is to provide a PCI bus control system and a PCI bus control method that can complete data transfer in a shorter time .

A PCI bus control system according to the present invention is a PCI bus control system in which a predetermined device accesses a first storage unit controlled by an arithmetic processing unit via a PCI bus, the first bus from the device. Unit time after the permission response is transmitted from the arithmetic processing unit in response to the access request to the storage unit until the transfer processing of the data stored in the first storage unit to the device is completed A counting unit that counts the number of occurrences of a clock signal repeatedly generated at an interval as a first number of occurrences, and after the retry response is output from the arithmetic processing unit at the time of initial setting, the device again after the occurrence of the previous access request The number of generations of an additional clock signal for changing the re-access request time until an access request is generated is determined every time counting by the counting unit is completed. A first setting unit that is added or subtracted by a few and set as the second occurrence number, and the second occurrence number is set in association with the second occurrence number set by the first setting unit. A second storage unit that stores the first number of occurrences counted by the counting unit, and after the initial setting, the first generation number stored in the second storage unit And a second setting unit configured to set the second generation number associated with the first generation number having a small value as the generation number of the additional clock signal.
The PCI bus control method according to the present invention is a PCI bus control method in which a predetermined device accesses the first storage unit controlled by the arithmetic processing unit via the PCI bus, and After the permission response is transmitted from the arithmetic processing unit in response to the access request to the first storage unit, the process of transferring the data stored in the first storage unit to the device is completed. A counting step that counts the number of clock signal occurrences repeatedly generated at unit time intervals as the first generation number, and the device makes a previous access after a retry response is output from the arithmetic processing unit in the initial setting. After the request is generated, the counting in the counting step is completed for the number of additional clock signals generated for changing the re-access request time until the access request is generated again. A first setting step of adding or subtracting a predetermined number of times each time and setting the second generation number of times and the second generation number of times set in the first setting step are associated with the second generation number of times. A storage step for storing the first number of occurrences counted in the counting step in the second storage unit when set, and the second storage unit in the storage step after the initial setting. A second setting step of setting, as the generation frequency of the additional clock signal, the second generation frequency associated with the first generation frequency having the smallest value among the first generation frequency stored in It is characterized by having.

According to the present invention , data transfer can be completed in a shorter time.

1 is a system configuration diagram including a PCI bus according to an embodiment. (A) is a time chart explaining a normal data transfer process using a PCI bus. (B) is a time chart when the request timing of the read access again is increased (delayed) by +1 clock after the retry response is made. (C) is a time chart when the read access request timing is increased (delayed) by +2 clocks after a retry response is made. (D) is a time chart when the read access request timing is increased (delayed) by +3 clocks after a retry response is made. (E) is a time chart when the request timing of the read access again is increased (delayed) by +4 clocks after the retry response is made. It is a flowchart explaining the basic processing of this embodiment. It is a flowchart explaining the process which measures the transfer rate of this embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a system configuration diagram including a PCI bus according to the present embodiment. In the figure, a CPU 1 and a memory 2 are constructed on a mother board (host control unit). The CPU 1 is a central processing unit (arithmetic processing unit), and performs processing according to a program stored in the memory 2. The memory 2 also stores video data created by command analysis of print data.

  The host bridge 3 is an interface (I / F) between the CPU 1 on the motherboard and a device connected to the PCI bus, and the PCI device 4 is connected to the host bridge 3 via the PCI bus. The PCI device 4 has a master function and accesses the memory 2 on the motherboard, for example. The host bridge 3 exchanges data with the memory 2 in response to an access request from the PCI device.

  The PCI device 4 includes a PCI slot 5 for connection to the PCI bus, a main control unit 6, a standby counter 7, a valid data number counter 8, and a clock number storage unit 9. For example, the PCI device 4 stores video data stored in the memory 2. Transfer to a video transfer circuit (not shown). The video transfer circuit transmits the video data transferred from the memory 2 to, for example, a print head (not shown).

  The main control unit 6 performs read access for reading video data to the host bridge 3 and controls transfer of video data read from the memory 2. Further, data for the number of clocks described later is sequentially prepared in the standby counter 7. The main control unit 6 is provided with a counter 10. The counter 10 starts counting after outputting a FRAME signal, which will be described later, and performs counting until video data transfer is completed.

  The standby counter 7 is a counter for adjusting a transmission timing when a read request after retry is performed. For example, data of the number of clocks to be sequentially updated every clock is set by the main control unit 6.

  The valid data number counter 8 is a counter that counts the number of data when the PCI device 4 reads video data from the memory 2, and in this example, 16 data of “0” to “15” are counted as the number of valid data. . The valid data number counter 8 outputs a count end signal to the clock number storage unit 9 after counting 16 video data.

  The clock number storage unit 9 stores the count result of the counter 10 corresponding to the clock number data set in the standby counter 7. For example, when the number of clocks of +1 is set in the standby counter 7, the number of clocks required to transfer the video data at this time is measured by the counter 10, and this measured value is stored. When the number of clocks of +2 is set in the standby counter 7, the number of clocks required for transferring video data at this time is measured by the counter 10, and the measured value is stored. Similarly, when the number of clocks of +3, +4,... Is set in the standby counter 7, the number of clocks required to transfer video data in each case is measured by the counter 10, and the measured value is stored.

  In addition to the PCI device 4 described above, a plurality of devices such as a device used when performing data compression processing and decompression processing, and a device used when transmitting / receiving display data are connected to the PCI bus. Is possible.

In the above configuration, the processing of this example will be described below.
FIGS. 2A to 2E are time charts for explaining the processing of this example, and FIGS. 3 and 4 are flowcharts for explaining the processing of this example.
First, normal processing when reading video data from the memory 2 on the motherboard will be described. The time chart shown in FIG. 2A and the flowchart shown in FIG. 3 explain this processing.

  First, the main control unit 6 of the PCI device 4 makes a read access request (REQ) to the host bridge 3 via the PCI bus in order to read the video data stored in the memory 2 on the motherboard (step (hereinafter referred to as “step”). 1).

  When the host bridge 3 receives the request for the request, it determines whether the PCI bus can be used. If the PCI bus can be used, the grant signal (GNT) is asserted (ST2 is YES), and the main control unit 6 determines the end of the standby count (ST3). This determination is to determine the end of the count of the number of clocks set in the above-described standby counter 7. In this normal processing, the standby counter 7 is reset to “0”, for example, and the PCI device 4 immediately performs the PCI. The bus can be used.

  Therefore, when a grant signal is output from the host bridge 3, the main control unit 6 outputs FRAME (ST4), and outputs an IRDY signal indicating that the PCI device 4 is ready for reception (ST5).

  The time chart shown in FIG. 2A shows the processing after the FARAME output. When the FRAME is output (“1” shown in FIG. 2A), the address presenting the address of the read data for the memory 2 Phase (AD) timing is ensured.

  Next, the host bridge 3 outputs a DEVSEL signal (ST6 is YES, “2” shown in FIG. 2A), reads the requested data from the memory 2, and stops the bus cycle until ready for transmission. Therefore, STOP (retry) is output (ST7 is YES, “3” shown in FIG. 2A). As described above, the clock frequency used differs between the motherboard side and the PCI bus side. For example, a shown in FIG. 2A recognizes the address of the requested read data on the memory 2 and stores the data in the memory 2. B indicates the time for synchronizing the data read from the memory 2 with the clock frequency on the PCI bus side.

  Therefore, in the case of this example, after the time shown in b above elapses, the data read from the memory 2 is ready for transmission. Further, “0” to “15” indicated by c in FIG. 4A indicate video data read from the memory 2.

  Therefore, the above process is repeated until the mother board is ready to transmit video data (ST1 to ST7). For example, in the example shown in FIG. 2A, a second STOP (retry) is output (FIG. 2A). When the next request is requested, the motherboard is ready to transmit video data.

  When the motherboard is ready for transmission, TRDY is output from the host bridge 3 (ST8 is YES, “5” shown in FIG. 2), and the main control unit 6 reads the video data from the memory 2 via the PCI bus, and Transmission is performed from the device 4 to a video transfer circuit (not shown) (NO in ST9, NO in ST10). During this time, the valid data number counter 8 counts the number of clocks until the transfer of the video data is completed. When the transfer of the scheduled number of video data is completed (YES in ST9), the count is finished from the valid data number counter 8 The signal is output to the clock number storage unit 9 and further notified to the main control unit 6, and the process is terminated.

  Next, the processing of this example for shortening the time until video data transfer is completed with respect to the processing at the time of normal access will be described. In this example, for example, when transferring the video data of the valid data number, the time until the re-access after the STOP (retry) output from the CPU 1 is increased for each clock with respect to the normal processing (delayed). And measure the time until video data transfer is completed. Then, the time until re-access that completes the transfer of video data in the shortest time is acquired. Hereinafter, the case where the time until the re-access after the STOP (retry) output is increased (delayed) every clock will be described in detail using a time chart.

  FIG. 2B shows a time chart in the case where the time until re-access is increased (delayed) by 1 clock with respect to the normal access, and FIG. 2 (d) shows a time chart when 3 clocks are increased (delayed) with respect to normal access, and FIG. 2 (e) shows 4 clocks (delayed) with respect to normal access. ) Shows the time chart.

  FIG. 4 is a flowchart for measuring the transfer rate by counting the number of clocks until the video data transfer is completed in each case. The counter 10 is used for the measurement of the transfer rate. Although the flowchart shown in FIG. 3 is basically used, it overlaps with the above description, and therefore the flowchart shown in FIG. 3 explains the end processing of the standby counter added in the processing of this example. To do.

  First, a case where the time until re-access shown in FIG. 2B is increased by one clock will be described. In this case, as described above, first, a read access request is made to the host bridge 3 via the PCI bus in order to read the video data stored in the memory 2 on the motherboard (step (hereinafter referred to as S in FIG. 4). 1). Thereafter, when the grant signal is asserted from the host bridge 3 (S2 is YES), the main control unit 6 of the PCI device 4 outputs FRAME, and the counter 10 starts the counting process (S3, “shown in FIG. 2B”). 1 ").

  Thereafter, the standby counter 7 continues the counting process, and the CPU 1 outputs STOP (retry) until data transfer preparation is completed (“3” shown in FIG. 2B). In this case, as described above, the time from the first retry output to the re-access is delayed by one clock. That is, the output timing of the re-FRAME shown in FIG. 2B (shown in FIG. 2B) with respect to the output timing of the re-FRAME shown in FIG. 2A (“6” shown in FIG. 2A). “7”) is delayed by one clock. As a result, the next STOP (retry) output from the CPU 1 is also delayed by one clock. However, since transfer data is not ready during this time, the STOP (retry) is output again from the CPU 1 (FIG. 2B). "4").

  This process is executed by the determination of the flowchart shown in FIG. 3 (ST3). In this example, the standby counter 7 is set with data of the number of clocks “1” from the main controller 6, and the standby counter 7, after one clock is counted, FRAME is output to the host bridge 3.

  Thereafter, when the CPU 1 side is ready for transmission, TRDY is output from the host bridge 3 (“5 ′” shown in FIG. 2B). Therefore, in this example, after that, video data is read from the memory 2 via the PCI bus, and transmitted from the PCI device 4 to a video transfer circuit (not shown). The counter 10 continues the counting process until the transfer of the video data is completed after the FRAME is output (S4 is NO), and when the transfer process is completed, the counter 10 ends the counting process (S4 is YES). Then, the clock number data as the measurement result is stored in the clock number storage unit 9 (S5). At this time, the count value of the counter 10 is stored in the clock number storage unit 9 corresponding to the data of the clock number “1” until the re-access after the retry.

  In this case, if the count value of the counter 10 is “41”, the clock frequency of the PCI bus is 66 MHz, and the bit width is 32 bits, the transfer rate is 90.1 MB / s (66 MHz × 4 bytes × 14 words / 41). Clock). The count value “41” is a value obtained by adding the count value until the FRAME output for reading the next video data to the count value of the counter 10.

  Next, the case where the time until the re-access shown in FIG. In this case as well, a read access request is first made to the host bridge 3 via the PCI bus in order to read the video data stored in the memory 2 on the motherboard (S1). After that, the grant signal is asserted from the host bridge 3 (S2 is YES), FRAME is transmitted from the main control unit 6 to the host bridge 3, and the counting process of the counter 10 is started (S3, shown in FIG. 2C). 1 ").

  Thereafter, the counter 10 continues counting processing as described above, and the CPU 1 outputs STOP (retry) until preparation for data transfer is completed (“3” shown in FIG. 2C). In this example, the time from the first retry output to the re-access is delayed by 2 clocks. That is, the output timing of the re-FRAME shown in FIG. 2C (shown in FIG. 2C) with respect to the output timing of the re-FRAME shown in FIG. 2A (“6” shown in FIG. 2A). “8”) is delayed by two clocks. As a result, the next STOP (retry) output from the CPU 1 is also delayed by 2 clocks. During this time, transfer data is ready, and TRDY # is output from the host bridge 3 (“9” shown in FIG. 2C). ).

  This process is also executed by the determination of the flowchart shown in FIG. 3 (ST3). In this example, the standby counter 7 is set with the data of the clock number “2” from the main control unit 6, and the standby counter 7 7, after 2 clocks are counted, FRAME is output to the host bridge 3. Therefore, in this example, after that, video data is read from the memory 2 via the PCI bus and transmitted from the PCI device 4 to a video transfer circuit (not shown).

  However, in this example, disconnection occurs during the transfer of 16 data, and the data transfer is stopped. In this example, after video data “0” to “13” is transferred, disconnection occurs, and all data transfer is not completed (NO in S4), and the counter 10 continues the count process. After that, when FRAME is output again and TRDY is output again from the host bridge 3 (“10” shown in FIG. 2C), the remaining video data (“14”, “14” from the memory 2 via the PCI bus). 15 ″) is transmitted to a video transfer circuit (not shown) via the PCI bus. When the transfer process ends, the counter 10 ends the counting process (YES in S4), and stores the clock number data as the measurement result in the clock number storage unit 9 (S5). At this time, the count value of the counter 10 is stored in the clock number storage unit 9 corresponding to the data of the clock number “2” until the re-access after the retry.

  In this case, the count value of the counter 10 is “44”, and the transfer rate is 84.0 MB / s (66 MHz × 4 bytes × 14 words / 44 clocks). The count value “44” is also a value obtained by adding the count value until the FRAME output for reading the next video data to the count value of the counter 10.

  Next, the case where the time until the re-access shown in FIG. In this case as well, a read access request is first made to the host bridge 3 via the PCI bus in order to read the video data stored in the memory 2 on the motherboard (S1). Thereafter, GNT is asserted from the host bridge 3 (S2), FRAME is transmitted from the main control unit 6 to the host bridge 3, and the counting process of the counter 10 is started (S3, “1” shown in FIG. 2D). .

  After that, the counter 10 continues counting processing as described above, and the CPU 1 outputs STOP (retry) until preparation for data transfer is completed (“3” shown in FIG. 2D). In this example, the time from the first retry output to the re-access is delayed by 3 clocks. That is, with respect to the output timing of the re-FRAME shown in FIG. 2A (“6” shown in FIG. 2A), the output timing of the re-FRAME shown in FIG. “11”) is delayed by 3 clocks.

  This process is also executed by the determination of the flowchart shown in FIG. 3 (ST3). In this example, the standby counter 7 is set with data of the number of clocks “3” from the main control unit 6, and the standby counter After counting for 3 clocks in 7, FRAME is output to the host bridge 3. As a result, the next STOP (retry) output from the CPU 1 is also delayed by 3 clocks. During this time, transfer data is ready, and TRDY is output from the host bridge 3 (“12” shown in FIG. 2D). . Therefore, in this example, after that, video data is read from the memory 2 via the PCI bus and transmitted from the PCI device 4 to a video transfer circuit (not shown).

  When the transfer process ends, the counter 10 ends the counting process (S4 is YES), and stores the value of the clock number as the measurement result in the clock number storage unit 9 (S5). At this time, the count value of the counter 10 is stored in the clock number storage unit 9 corresponding to the data of the clock number “3” until the re-access after the retry.

  In this case, the count value of the counter 10 is “36”, and the transfer rate is 117.3 MB / s (66 MHz × 4 bytes × 14 words / 36 clocks). The count value “36” is also a value obtained by adding the count value until the FRAME output for reading the next video data to the count value of the counter 10.

  Finally, a case where the time until the re-access shown in FIG. 2E is delayed by 4 clocks will be described. In this case as well, a read access request is first made to the host bridge 3 via the PCI bus in order to read the video data stored in the memory 2 on the motherboard (S1). Thereafter, GNT is asserted from the host bridge 3 (S2), the main control unit 6 transmits FRAME to the host bridge 3, and the counter 10 starts counting processing (S3, “1” shown in FIG. 2 (e)). .

  After that, the counter 10 continues counting processing as described above, and the CPU 1 outputs STOP (retry) until preparation for data transfer is completed (“3” shown in FIG. 2E). In this example, the time from the first retry output to the re-access is delayed by 4 clocks. That is, the output timing of the re-FRAME shown in FIG. 2 (e) (shown in FIG. 2 (e)) with respect to the output timing of the re-FRAME shown in FIG. 2 (a) (“6” shown in FIG. 2 (a)). “13”) is delayed by 4 clocks.

  This process is also executed by the determination of the flowchart shown in FIG. 3 (ST3). In this example, the standby counter 7 is set with data of the number of clocks “4” from the main control unit 6, and the standby counter 7, four clocks are counted, and FRAME is output to the host bridge 3. As a result, the next STOP (retry) output from the CPU 1 is also delayed by 4 clocks. During this time, transfer data is ready, and TRDY is output from the host bridge 3 (“14” shown in FIG. 2E). . Therefore, in this example, after that, video data is read from the memory 2 via the PCI bus and transmitted from the PCI device 4 to a video transfer circuit (not shown).

  When the transfer process ends, the counter 10 ends the counting process (S4 is YES), and stores the value of the clock number as the measurement result in the clock number storage unit 9 (S5). At this time, the count value of the counter 10 is stored in the clock number storage unit 9 corresponding to the data of the clock number “4” until the re-access after the retry.

  In this case, the count value of the standby counter 7 is “38”, and the transfer rate is 111.2 MB / s (66 MHz × 4 bytes × 14 words / 38 clocks). The count value “38” is also a value obtained by adding the count value until the FRAME output for reading the next video data to the count value of the counter 10.

  Thereafter, the number of clocks “5”, “6”,... Are sequentially set in the standby counter 7 and the same processing as described above is repeated. Then, the count value data of the counter 10 is stored together with the clock number data sequentially increased in the clock number storage unit 9, and the count value obtained by the counter 10 is stored as the smallest clock number data. Set as the number of clocks.

By processing in this way, the data of the clock number with the smallest count value by the counter 10 is set in the standby counter 7 and used for the transfer of the video data from the memory 2. Accordingly, data having the number of clocks capable of performing the video data transfer process in the shortest time is set in the standby counter 7 so that the most efficient video data transfer process can be performed.
The process for obtaining the optimum generation time of the transfer request signal is performed before the actual data transfer operation. After the apparatus power is turned on, the CPU 1 finishes the PCI setting, and when the CPU 1 recognizes the PCI device 4, the CPU 1 instructs the PCI device 4 to start the process for measuring the optimum time.

  In the description of the above embodiment, the count value set in the standby counter 7 is set to be updated in the order of +1 clock, +2 clock,..., But in reverse, for example, +10 clock, +9 clock, -You may set to update in the direction of decreasing sequentially.

  In the case of the normal processing shown in FIG. 2A, the set value of the standby counter 7 is “0”. In this case, if the counter 10 counts until the video data transfer processing is completed, the count number In this case, assuming that the clock frequency of the PCI bus is 66 MHz and the bit width is 32 bits, the transfer rate is 94.8 MB / s (66 MHz × 4 bytes × 14 words / 39 clocks).

  Although several embodiments of the present invention have been described, the present invention is included in the inventions described in the claims and their equivalents. Hereinafter, the invention described in the scope of claims at the beginning of the filing of the present patent application will be added.

Appendix 1
An arithmetic processing unit;
A first storage unit controlled by the arithmetic processing unit;
A device for accessing the first storage unit via a PCI bus,
The device is
After a permission response is transmitted from the arithmetic processing unit in response to an access request from the device to the first storage unit, transfer processing of the data stored in the first storage unit to the device is completed. A counting unit that counts the number of occurrences of a clock signal repeatedly generated at unit time intervals until
A setting unit for setting the number of occurrences of the clock signal for changing the re-access request time after the retry response is output from the arithmetic processing unit until the device again generates an access request after the occurrence of the previous access request;
A standby time changing unit for setting and counting the number of occurrences of the clock signal for changing the re-access request time sequentially updated in the setting unit;
The number of generations of the clock signal counted by the counting unit until the completion of the transfer process processed according to the number of generations of the clock signal for changing the re-access request time set in the setting unit A second storage unit that stores the number of occurrences of the clock signal for changing the re-access request time set in the setting unit;
The number of generations of the clock signal counted by the counting unit until the completion of the transfer process processed according to the number of generations of the clock signal that changes the re-access request time set in the setting unit is A control unit that reads out the number of generations of the clock signal that changes the re-access request time set in the setting unit when it is the least from the second storage unit, and sets the setting in the setting unit;
And a PCI bus control device.

Appendix 2
The completion of the transfer processing of the data stored in the first storage unit to the device is determined by a predetermined number of data transferred from the first storage unit by a third counter provided in the device. The PCI bus control device as set forth in appendix 1, wherein the control is performed by counting.

Appendix 3
The retry response from the arithmetic processing unit is output from the standby time changing unit until the preparation of transfer data to the device is completed, and the re-access request time sequentially set in the setting unit 3. The PCI bus control device according to appendix 1 or 2, wherein the number of times of generation of the clock signal that changes the number is a sequentially increasing number or a sequentially decreasing number.

Appendix 4
The device is a video data transfer circuit of a printing apparatus, and generates the clock signal to the setting unit when transferring the video data stored in the first storage unit to the print head via the PCI bus. 4. The PCI bus control device according to appendix 1, 2, or 3, wherein the number of times is set to minimize the transfer time of the video data.

Appendix 5
A PCI bus control method for accessing a first storage unit controlled by an arithmetic processing unit from a device via a PCI bus,
After a permission response is transmitted from the arithmetic processing unit in response to an access request from the device to the first storage unit, transfer processing of data stored in the first storage unit to the device is completed. A counting process for counting the number of occurrences of a clock signal repeatedly generated at unit time intervals until
A setting process for setting the number of generations of the clock signal for changing the re-access request time after the retry response is output from the arithmetic processing unit until the device generates an access request again after the previous access request is generated,
A waiting time changing process for setting and counting the number of occurrences of the clock signal for changing the re-access request time sequentially updated in the setting process;
The clock signal counted by the counting process until the completion of the transfer process processed according to the number of times the clock signal is generated to change the re-access request time set by the waiting time changing process Storing the number of occurrences in the second storage unit corresponding to the number of occurrences of the clock signal for changing the re-access request time set in the setting unit;
The number of clock signal generations counted by the counting process until the completion of the transfer process processed according to the number of clock signal generations changing the re-access request time set in the setting unit is the largest. When the time is small, the clock number signal generation times for changing the re-access request time used for the setting process is read from the second storage unit, and used as the number of generations of the clock signal for the setting process.
And a PCI bus control method.

1 ... CPU
2 ... Memory 3 ... Host bridge 4 ... PCI device 5 ... PCI slot 6 ... Main control unit 7 ... Standby counter 8 ... Valid data counter 9 ... Clock count Storage unit 10 ・ ・ Counter

Claims (3)

A PCI bus control system in which a predetermined device accesses a first storage unit controlled by an arithmetic processing unit via a PCI bus,
After a permission response is transmitted from the arithmetic processing unit in response to an access request from the device to the first storage unit, transfer processing of data stored in the first storage unit to the device is completed. A counting unit that counts the number of occurrences of the clock signal repeatedly generated at unit time intervals as the first number of occurrences,
In initialization, an additional clock signal for changing the re-access request time after the retry response is output from the arithmetic processing unit until the device generates an access request again after the previous access request occurs A first setting unit that sets the number of occurrences as a second number of occurrences by adding or subtracting a predetermined number of times each time counting by the counting unit is completed;
A second storage unit that stores the first occurrence number counted by the counting unit when the second occurrence number is set in association with the second occurrence number set by the first setting unit When,
After the initial setting, the second occurrence count associated with the first occurrence count having the smallest value among the first occurrence counts stored in the second storage unit is set as the additional occurrence count. A second setting unit for setting the number of clock signal generations;
A PCI bus control system comprising: The PCI bus control system according to claim 1, wherein the data is stored in the first storage unit in advance for the initial setting. A PCI bus control method in which a predetermined device accesses a first storage unit controlled by an arithmetic processing unit via a PCI bus,
After a permission response is transmitted from the arithmetic processing unit in response to an access request from the device to the first storage unit, transfer processing of data stored in the first storage unit to the device is completed. A counting step of counting the number of occurrences of the clock signal repeatedly generated at unit time intervals as the first number of occurrences until
In initialization, an additional clock signal for changing the re-access request time after the retry response is output from the arithmetic processing unit until the device generates an access request again after the previous access request occurs A first setting step of setting the number of occurrences as a second number of occurrences by adding or subtracting a predetermined number of times each time counting in the counting step is completed;
In association with the second occurrence count set in the first setting step, the first occurrence count counted in the counting step when the second occurrence count is set is stored in the second storage unit. Memory step to keep,
After the initial setting, the second occurrence count associated with the first occurrence count having the smallest value among the first occurrence counts stored in the second storage unit in the storing step is A second setting step for setting the number of occurrences of the additional clock signal;
A PCI bus control method characterized by comprising: