JP2000122969A - Data transfer device, data transfer method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To distribute the load on a bus, to suppress the generation of response delay, and to greatly improve the reliability by providing a delay time storage means and a control means which inputs and outputs data while shifting the timing by a delay time according to the data transfer processing. SOLUTION: A CPU 101 is able to access the delay time storage means 3 by one of an I/O space, a memory space, and a PCI configuration space. Then, a value calculated by a software program in a memory 102 can be written to the delay time storage means 3. The delay time storage means 3 is a storage area mounted on a video interface 1 and connected to a control means 2. Then when the control means 2 transfers data to a PCI bus 102, the value stored in the storage area is read out and the start of the transfer is delayed by the time corresponding to the value to perform the data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus and a data transfer method for inputting and outputting a predetermined amount of data to and from a bus of a computer within a predetermined period, and the functions or steps of those means are provided to a computer. The present invention relates to a recording medium for storing a program to be executed, and is particularly suitable for use in a video server, a nonlinear editing machine, and the like.

[0002]

2. Description of the Related Art FIG. 10 is a schematic diagram showing a configuration of a video server which inputs and outputs video data to a VTR, a display, and the like using a computer.

A CPU 103 is connected to a bus 103 in a computer.
01, memory 102, disk interface 104,
Video interface 105, communication interface 106
Is connected. The video interface 105 includes an unillustrated PLD (Programmable Logic Device) or another ROM (Read Only Memory) and a RAM (Random Access Memory).
(mory). CPU
A VTR 101 operates according to a software program stored in a memory 102 and is connected from a hard disk 107 connected to a disk interface 104 to a video interface 105 via the memory 102.
8 and the display 109. Conversely, video data is input from the VTR 108 to the hard disk 107 via the memory 102. The CPU 101 is connected to an external terminal 110 connected to the communication interface 106.
To interpret video commands and input / output video data and VTR10
8 is performed.

For example, when the external terminal 110 is connected to the display 1
When the CPU 101 instructs the image reproduction to the CPU 09, the CPU 101 transmits the designated image data from the hard disk 107 to the memory 10 via the disk interface 104 and the bus 103.
2 and then from the memory 102 to the video interface 105 via the bus 103 with synchronization necessary for video reproduction. Thereafter, the video data is decoded and displayed on the display 109. Such a flow of video data is hereinafter referred to as a stream. The server simultaneously inputs and outputs a plurality of data respectively corresponding to a plurality of streams to and from the hard disk 107 in accordance with an instruction from the external terminal 110 or a content instructed by the user interface of the server itself.

[0005] Video data is processed according to a synchronization signal. In the case of the NTSC system, one second of video is composed of 30 frames. That is, video data for one frame is processed every 1/30 second. Therefore, the server must continuously transfer the required number of streams of video data in 1/30 seconds. VTR10
8 is a high-speed VTR capable of recording and reproducing at 4 times the normal speed,
Input / output to / from this VTR is a data transfer having a data amount four times as large as that of a normal stream, and it is necessary to process video data for four frames in 1/30 second.

[0006]

However, the above configuration has the following problems.

Since the video interface 105 transfers video data in accordance with a predetermined reference signal, a large amount of video data is simultaneously concentrated on the bus 103 when a plurality of streams are sent. This will be described with reference to FIG.

FIG. 11 is a schematic diagram showing the transfer timing of data, showing the lapse of time from time T1 to time T5 from left to right. In order from the top, a reference signal 200, a normal speed stream signal 210, and a quadruple speed stream Signal 220,
The synchronous communication signal 230 is shown. Time interval Tf is 1/30
Second, and the reference signal 200 repeats the same waveform in this cycle. The normal speed stream, the quadruple speed stream and the synchronous communication start processing in synchronization with the rise of the reference signal.
Each processing time is indicated by a processing time 211, a processing time 221, and a processing time 231 in the hatched portion. Also, a time allowable as the processing time of the synchronous communication is indicated by an allowable time Ta. At times T1 and T2, only the normal speed stream is present, and the synchronous communication is within the allowable time Ta. At time T3, the transfer of the quadruple-speed stream is further started, and the load on the bus 103 and the CPU 101 is concentrated to reduce the processing margin, so that the signal processing of the communication interface 106 is delayed. Then, the processing exceeds the allowable time Ta. As described above, a case occurs in which a response within a predetermined time becomes impossible. This is a fatal problem for a server that sends many streams, and causes a loss of reliability.

The present invention disperses the load on the bus in consideration of the above-mentioned problems of the conventional data transfer apparatus and data transfer method, thereby suppressing the occurrence of response delay and improving reliability. It is an object of the present invention to provide a data transfer device, a data transfer method, and a recording medium that can be greatly improved.

[0010]

The reason why the synchronous communication process is delayed as described above is that a plurality of processes are started at the same time when the reference signal rises. The present invention disperses the load on the bus by shifting the processing start timing within a predetermined time by the following means, thereby making it difficult to generate a response delay.

According to a first aspect of the present invention (corresponding to the first aspect of the present invention), there is provided a memory for holding data, and a data input / output for inputting / outputting the data to the memory at regular intervals via a bus. Output means, and the data input / output means,
Delay time storage means for storing a delay time set as a time for shifting the data input / output timing for each of the fixed times from the reference time for each of the fixed times; and a timing for the delay time according to the data transfer processing. And a control means for inputting and outputting the data by shifting the data.

According to a second aspect of the present invention (corresponding to the second aspect of the present invention), the data input / output means inputs and outputs the plurality of data corresponding to a plurality of streams at regular intervals. The control unit may be configured so that, when the data input / output unit inputs / outputs the plurality of data at regular intervals, the control unit corresponds to at least one of the plurality of streams. A data transfer device according to a first aspect of the present invention, characterized in that data is input / output at a timing shifted by the delay time.

A third aspect of the present invention (corresponding to the third aspect of the present invention) comprises a first or second delay time determining means for setting and / or resetting the delay time. 3 is a data transfer device of the present invention.

According to a fourth aspect of the present invention (corresponding to the fourth aspect of the present invention), there is provided a measuring means for measuring a transfer processing time of the data on the bus at every predetermined time, and the delay time determining means is provided. However, the data transfer apparatus according to a third aspect of the present invention is characterized in that the delay time is reset every time the fixed time elapses so that the transfer processing time approaches a predetermined value.

A fifth aspect of the present invention (corresponding to the fifth aspect of the present invention) is that, when the plurality of data respectively corresponding to the plurality of streams are inputted and outputted at the predetermined time, A stream information holding unit that stores the type of each stream as stream information in association with a transfer amount of each stream, and wherein the control unit refers to the stream information, and transfers the stream of the plurality of streams. A third or fourth data transfer apparatus according to the present invention, wherein the data corresponding to the stream having a smaller amount is input / output at a timing shifted by the delay time.

According to a sixth aspect of the present invention (corresponding to the sixth aspect of the present invention), when the plurality of data respectively corresponding to the plurality of streams are input and output at the predetermined time, Comprises stream information holding means for storing the type of each stream as stream information in association with each transfer amount, and wherein the delay time determining means comprises:
Referring to the stream information, the data corresponding to the stream having the relatively large transfer amount corresponds to the stream having the relatively small transfer amount such that the delay time is relatively short. A data transfer apparatus according to a third aspect of the present invention, wherein the delay time is set and / or reset so that the delay time of the data is relatively long.

According to a seventh aspect of the present invention (corresponding to the seventh aspect of the present invention), the stream information holding means stores the priority of data transfer processing for each type of the stream, However, when the set or reset delay time is longer than a predetermined maximum allowable delay time,
According to the priority, the stream for which data input / output is stopped is selected, and the data input / output corresponding to the stream is not performed at least within the fixed time corresponding to the delay time. Or a data transfer device according to a sixth aspect of the present invention.

An eighth aspect of the present invention (corresponding to the eighth aspect of the present invention) is that, when the plurality of data respectively corresponding to the plurality of streams are input / output at the predetermined time, the A stream information holding unit that stores the type of each stream as stream information in association with the priority of each data transfer process, and wherein the delay time determining unit refers to the stream information and has a low priority. A data transfer apparatus according to a third aspect of the present invention, wherein the delay time is set and / or reset so that the data corresponding to the type of the stream has a longer delay time.

According to a ninth aspect of the present invention (corresponding to the ninth aspect of the present invention), the delay time determining means sets the delay most frequently set or reset under substantially the same transfer condition. The time is stored as a standard delay time for each transfer condition, and thereafter, under substantially the same transfer conditions as the stored transfer conditions, the initially set delay time is set to the same value as the standard delay time. 3rd to 3rd, characterized by setting
An eighth aspect of the present invention is the data transfer device according to the present invention.

A tenth aspect of the present invention (corresponding to the tenth aspect of the present invention) is characterized by including a CPU connected to the bus and performing input / output processing of the memory according to a software program. A ninth data transfer device of the present invention.

An eleventh invention (corresponding to the invention according to claim 11) is the data input / output means or the CPU.
However, when the CPU has the delay time determining means and the CPU has the delay time determining means, the delay time is set according to the processing of the software program. This is a data transfer device of the present invention.

According to a twelfth aspect of the present invention (corresponding to the twelfth aspect of the present invention), when at least one of the measuring means and the stream information holding means is provided, the data input / output means or the CPU is provided. An eleventh aspect of the present invention is a data transfer device according to the present invention, comprising the above-mentioned or both of them together with the above-mentioned delay time determining means.

According to a thirteenth aspect of the present invention (corresponding to the thirteenth aspect of the present invention), when the plurality of data respectively corresponding to a plurality of streams are transferred via a bus at regular time intervals, the plurality of data are transferred. At least one of the streams
A data transfer method, comprising a delay transfer step of transferring the data corresponding to the stream of a book at a timing shifted by a predetermined delay time.

In a fourteenth aspect of the present invention (corresponding to the fourteenth aspect of the present invention), the delay transfer step causes the data transfer processing time on the bus within the fixed time to approach a predetermined value. A data transfer method according to a thirteenth aspect of the present invention, further comprising a delay time resetting step of resetting the delay time every time the fixed time elapses.

A fifteenth invention (corresponding to the invention according to claim 15) is characterized in that the delay transfer step sets the delay time set or reset most frequently under substantially the same transfer conditions. A standard delay time storing step for storing each transfer condition as a standard delay time, and under the same transfer conditions as the stored transfer conditions, the first set delay time is set to the same value as the standard delay time. Setting a delay time initial setting step.
4 is a data transfer method according to the present invention.

According to a sixteenth aspect of the present invention (corresponding to the present invention as defined in claim 16), when the plurality of data respectively corresponding to the plurality of streams having different transfer amounts are transferred at the fixed time intervals, In the delay transfer step, the data corresponding to the stream having the smaller transfer amount among the plurality of streams is transferred with the timing shifted by the delay time. This is the data transfer method of the present invention.

[0027] A seventeenth invention (corresponding to the invention according to claim 17) is characterized in that the delay transfer step is performed when the set or reset delay time becomes longer than a predetermined allowable maximum delay time. Having a transfer stop step of selecting the stream for which input / output of data is to be stopped, and not transferring the data corresponding to at least the fixed time corresponding to the delay time. The data transfer method according to any one of the thirteenth to sixteenth aspects of the present invention.

An eighteenth aspect of the present invention (corresponding to the eighteenth aspect of the present invention) provides all or a part of the functions of each means of the data transfer apparatus of the present invention, or each step of the data transfer method of the present invention. Is a storage medium storing a program for causing a computer to execute all or part of the program.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In the following description of each embodiment, components designated by the same reference numerals as those in FIGS. 10 and 11 will be described with reference to FIGS. 10 and 11 unless otherwise specified.
It is assumed that the device has the same function as that described in the above, and the description of the function will be omitted.

In the following, PCI (Peripheral Comp
onent Interconnect) bus as an example, but the ISA (Ind
ustrial Standard Architecture) bus, EISA (Extend
Other buses such as an ed Industrial Standard Architecture) bus and an S bus may be used. In the following, video data is targeted, but similar processing can be performed on audio data, auxiliary data, and the like. The format of these data is DVCPRO format, DV format, MPEG format, Motion-JPEG format, etc., and processing is performed on a frame-by-frame basis, but the same method is applied when processing multiple frames at once. It is easy to do.

(First Embodiment) First, the first embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing a data transfer device according to a first embodiment of the present invention. The configuration of a video server which inputs and outputs video data to a VTR or a display using a computer. FIG. The video interface 1 (corresponding to the data input / output means of the present invention) is a PCI card which is used by being attached to the PCI bus 103, and has a connector for the PCI bus 103 and a terminal for connecting to an external device such as a VTR or a display. Have. SDTI (Serial DataTranspor
t Interface) or a dedicated bus to connect to external devices. The transfer of data between the PCI bus 103 and the external device is controlled by the control means 2, and the PLD, ROM, R
It operates according to a program stored in a device such as an AM.

The delay time storage means 3 is a storage area mounted on the video interface 1, and is connected to the control means 2. When the control means 2 transfers data to the PCI bus 103, it reads the value stored in the storage area and delays the start of transfer by a time corresponding to the value to perform data transfer.

In order to count the waiting time, the control means 2 controls any of a clock mounted on the video interface 1, a clock obtained from the PCI bus 103, and a clock obtained from an external device (neither is shown). ), And counts up or down an internal counter in synchronization with it. Therefore, the value set in the delay time storage means 3 may be the value of the counter itself, but is preferably in units of time such as milliseconds or microseconds in consideration of user's convenience. At this time, the control means 2 holds a table or a calculation formula for converting between the counter value and the time unit in the program.

In the present embodiment, the function of the delay time determining means of the present invention is provided by the CPU 101.

The delay time storage means 3 may be physically mounted in the same device as the control means 2 or may be mounted in a different part. The delay time storage means 3 can be accessed from the CPU 101 through any one of the I / O space, the memory space, and the PCI configuration space. Therefore, the memory 10
2 can be written in the delay time storage means 3. Also, by preparing areas for the number of streams to be transferred, it is possible to control the delay time for each stream.

Hereinafter, as an example, the operation timing when the normal speed stream and the quadruple speed stream are simultaneously transmitted will be described with reference to FIGS.

FIG. 2 is a diagram showing an example of the operation timing of the data transfer device according to the present embodiment, and shows a case where the transfer of the quadruple speed stream 220 is started from the time T3 during the transfer of the normal speed stream 210. ing. FIG.
5 is a flowchart of a software program in the present embodiment. When the CPU 101 receives a normal-speed stream transfer start command from the external terminal 110 or a user interface (not shown) according to the software program in the memory 102, it starts processing (step S30). Next, in step S31, it is checked whether another stream is being used. At time T1 and time T2, only the normal-speed stream is used, so that the process proceeds to step S33. At time T3 and time T4, two streams of the normal speed stream and the quadruple speed stream are transferred,
Proceeding to step 32, the delay time Td is set in the delay time storage means 3 corresponding to the normal speed stream. In step 33, after completion of preparation for transfer of data for one frame, C
The PU 101 notifies the control unit 2 of the notification, and the control unit 2 transfers data. The control means 2 refers to the delay time storage means 3 corresponding to each stream to delay the start of transfer by a predetermined time. When the transfer of one frame is completed, the flow returns to the processing by the CPU 101 again, and it is determined in step 34 whether or not the stream transfer is to be ended. When continuing, this processing is repeated from step S31, and when ending, the end processing is performed in step S35. Steps S31 to S34 correspond to the delay transfer step of the present invention.

As described above, concentration of the load can be avoided, and the processing time of the synchronization signal 230 falls within the allowable time Ta, so that the occurrence of a response delay can be prevented. Here, the transfer start is delayed for the normal speed stream,
The quad-speed stream may be delayed. The same effect can be obtained by delaying from the beginning instead of delaying from time T3.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
This embodiment is different from the above-described first embodiment only in the point that the measuring means of the present invention is provided, and other than that, it is the same as the first embodiment. Therefore, in the present embodiment, parts that are not particularly described are the same as those in the first embodiment, and those components that are assigned the same reference numerals as those in the first embodiment are unless otherwise specified. Have the same functions as those of the first embodiment.

FIG. 4 is a configuration diagram of a video interface of the data transfer device according to the second embodiment of the present invention.

The measuring means 4 is connected to the control means 2 and is capable of measuring the time required for synchronous communication processing (hereinafter referred to as synchronous processing time; corresponding to the transfer processing time of the present invention). Specifically, the control unit 2 or the measurement unit 4 includes a flag indicating that the synchronous communication process is being performed.
The CPU 101 sets and resets the flag according to the software program stored in the memory 102, and the measuring unit 4 measures the synchronization processing time by monitoring the flag.

The value of the measuring means 4 is read out by the CPU 101 in accordance with the software program stored in the memory 102 and used for calculating the delay time. The calculated delay time is written to the delay time storage means 3.

In order to count the waiting time, the measuring means 4 is provided with a clock mounted on the video interface 1, a clock obtained from the PCI bus 103, or a clock obtained from an external device (neither is shown). ), And counts up or down an internal counter in synchronization with it.

The measuring means 4 may be physically mounted in the same device as the control means 2 or the delay time storing means 3, or may be mounted in a different part. For example, if the CPU 101 has the function of the delay time determining means of the present invention, and if it also has the function of the measuring means of the present invention, the output of the measuring means does not need to pass through a bus, so that the delay time can be more efficiently reduced. The settings are made. When the CPU 101 has the function of the delay time determining means of the present invention and the data input / output means (video interface 1) of the present invention also has the function of the measuring means of the present invention, as in the present embodiment,
The measurement means 4 can be accessed from the PU 101 through any of the I / O space, the memory space, and the PCI configuration space. Therefore,
The value of the measuring means 4 can be read by a software program in the memory 102. Also, by preparing areas for the number of streams to be transferred, it is possible to control the delay time for each stream.

Next, a more detailed description will be given with reference to FIG. FIG. 6 is a flowchart of a software program according to the present embodiment.

If there is a data transfer request, step S6
The processing is started from 0. First, a predetermined delay time Td1 is set in the delay time storage means 3 in step 61. Next, in step S62, data transfer is performed as in the first embodiment, and at the same time, the synchronization processing time is measured.
In step S63, it is checked whether the measured processing time falls within the allowable time Ta. If not, it is determined that a transfer error has occurred and the processing is terminated.
If it is within the allowable time, the processing time measured in step S64 is compared with the reference time Tb. As a result of the comparison, if the processing time is longer, the delay time is extended in step S65, and if the processing time is shorter, the delay time is reduced in step S66. If the reference time and the processing time are equal or within a predetermined difference, the delay time is not changed. These delay times are set in the delay time storage means 3 in step S67, and the transfer processing is performed in step S68. At this time, the processing time is measured at the same time.
When the transfer is to be ended, it is determined in step S69, and the process ends in step S70. To continue the transfer, the same processing is repeated from step S63. Step S61
Steps S69 to S69 correspond to the delay transfer step of the present invention.
64 to S67, in the delay time resetting step of the present invention,
Each corresponds.

Hereinafter, the operation timing when the normal speed stream and the quadruple speed stream are made to flow simultaneously will be described with reference to FIG. 5 as an example. FIG. 5 is a diagram showing an example of operation timing of the data transfer device according to the present embodiment. 5, the description of the same reference numerals as those in FIG. 2 is omitted.

At time T1, the normal speed stream 21
0 is transferred in the delay time Td1, and the synchronization signal 230 is completed in the processing time Tc1. Since the processing time Tc1 measured by the measuring means 4 is shorter than the allowable time Ta but longer than the reference time Tb, the next transfer (transfer at time T2).
Sets the transfer start delay time of the normal speed stream to be long. Thus, the transfer of the normal speed stream at the time T2 has a delay time Td2. Where Td2> Td
It is one. Further, the synchronization signal 230 at this time is completed in the processing time Tc2, which is shorter than the reference time Tb, so that the next transfer (transfer at time T3) sets the transfer start delay time short. Thus, the delay time at time T3 is Td3. Here, Td2> Td3.

As described above, since the delay time can be adjusted each time data is transferred at regular intervals, a more reliable system can be provided to the user.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
This embodiment is different from the above-described second embodiment in that the function of the delay time determining means of the present invention is not the CPU but the data input / output means of the present invention. Only the points are the same, and the rest is the same as the second embodiment. Therefore, in the present embodiment, components that are not particularly described are assumed to be the same as those in the second embodiment, and the components denoted by the same reference numerals as those in the second embodiment are described unless otherwise specified. Have the same functions as those of the second embodiment.

FIG. 7 is a configuration diagram of a video interface of a data transfer device according to the third embodiment of the present invention.

The delay time determining means 5 is mounted on the video interface 1 and includes the measuring means 4 and the delay time storing means 3
The delay time in the next transfer is calculated with reference to the synchronization processing time measured by the measuring means 4, and the value is set in the delay time storing means 3. The calculation algorithm is the same as in FIG. The control means 2 delays the start of the transfer by a predetermined time with reference to the value of the delay time storage means 3.

As a result, the delay time can be adjusted each time data is transferred at regular intervals, so that a more reliable system can be provided to the user. Further, since the delay time determining means 5 is provided in the data input / output means (video interface 1) of the present invention together with the control means 2 and the measuring means 4, the synchronization processing time can be calculated on the hardware side. Therefore, there is an effect that the delay of the synchronous communication processing is suppressed.

The delay time determining means 5 may be physically mounted in the same device as the control means 2 or the measuring means 4, or may be mounted in a different part. However, if the data input / output means (video interface 1) of the present invention is not provided with the delay time determination means 5 together with the control means 2 and the measurement means 4, the CPU 10
The effect of reducing the load of No. 1 cannot be obtained.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
This embodiment is different from the above-described third embodiment in that the data input / output unit of the present invention has the stream information holding unit of the present invention instead of the measuring unit of the present invention. Only the other is the same as the third embodiment. Therefore, in the present embodiment, components that are not particularly described are the same as those in the third embodiment, and components denoted by the same reference numerals as those in the third embodiment are described unless otherwise specified. Have the same functions as those of the third embodiment.

FIG. 8 is a configuration diagram of a video interface of a data transfer device according to the fourth embodiment of the present invention.

The stream information holding means 6 includes the control means 2
, And holds at least information on the number of streams being transferred and the type of stream (normal speed / 4 × speed). The delay time determining means 5 determines the delay time with reference to the stream information of the stream information holding means 6, and sets a value in the delay time storing means 3. At this time, the delay time of the quadruple speed stream, which has a large transfer amount and takes a long time for the transfer process, is set to 0 or shorter, and the delay time of the normal speed stream is increased. As a result, even when a plurality of streams are transferred, concentration of load can be avoided.

When the stream information holding means 6 holds information indicating whether or not data loss is permitted for each stream, the control means 2 determines a predetermined maximum delay in the above-mentioned delay time determination. When the delay time becomes longer than the time, the transfer of the data corresponding to the stream may be stopped (corresponding to the transfer stop step of the present invention) at least for the transfer of the data.

When the stream information holding means 6 holds the processing priority for each stream, the delay time determination means 5 sets the delay of a high priority stream to 0 or reduces it. As described above, the delay of the low-priority stream is increased, and if the maximum delay time is exceeded, the control unit 2 sets the transfer of the data corresponding to the low-priority stream to at least the transfer of the data. May be stopped (corresponding to the transfer stop step of the present invention).

Thus, even when a normal speed stream is monitored while transferring a 4 × speed stream, a high quality 4 × speed stream transfer can be provided to the user.

The stream information holding means 6 and the delay time determining means 5 may be physically mounted in the same device as the control means 2, or may be mounted in a different part. However, when the delay time determining means 5 is not provided in the data input / output means (video interface 1) of the present invention together with the control means 2 and the stream information holding means 6, the same as described in the fourth embodiment In addition, the effect of reducing the load on the CPU 101 cannot be obtained.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
This embodiment differs from the above-described second embodiment only in that the delay transfer step of the present invention has a standard delay time storing step of the present invention and a delay time initial setting step of the present invention. Yes, the rest is the same as the second embodiment. Therefore, in the present embodiment, components that are not particularly described are assumed to be the same as those in the second embodiment, and the components denoted by the same reference numerals as those in the second embodiment are described unless otherwise specified. ,
It has the same function as the second embodiment.

FIG. 9 is a flowchart of a software program according to the fifth embodiment of the present invention.

When the transfer of a certain stream is started, the process starts from step S90. First, in step S91, transfer conditions such as the number of streams and the type of stream are checked. Next, it is checked whether or not a pattern matching the condition checked in step S92 has been learned before. If it has been learned, the learning value is set as the delay time in step S93, and the data transfer is executed in step S94. If it has not been learned, a predetermined delay time is set, and the routine proceeds to step 94. Step S9
4 corresponds to step S62 in FIG. 6 shown in the second embodiment.
The same processing as steps S69 to S69 is included, and the delay time is appropriately adjusted. Of course, the first learning value may be used as it is. When ending the transfer of the stream, the most frequent delay time obtained during the transfer is stored as a learning value under the condition in step S95, and the process ends in step S96. Steps S91 to S95 are as follows:
Steps S91 to S93 are included in the delay transfer step of the present invention.
Corresponds to the step S in the delay time initial setting step of the present invention.
Reference numeral 95 corresponds to the standard delay time storage step of the present invention. By following the above procedure, it can be expected that the adjustment of the delay time is performed more efficiently than in the second embodiment.

According to the data transfer apparatus of the present invention, in the first to fifth embodiments, the data input / output means of the present invention converts the plurality of data corresponding to a plurality of streams to the predetermined data. Although it has been described that data can be input and output at each time, the present invention is not limited to this. For example, even if the data input / output means of the present invention corresponds to a single stream, What is necessary is just to input and output data at a different timing from data input and output by other input / output means.
In short, a memory for holding data, and a data input / output unit for inputting / outputting the data to / from the memory at regular intervals via a bus, the data input / output unit includes:
Delay time storage means for storing a delay time set as a time for shifting the data input / output timing for each of the fixed times from the reference time for each of the fixed times; and a timing for the delay time according to the data transfer processing. Any data transfer device having control means for inputting and outputting the data by shifting the data may be used.

In the first to fifth embodiments described above, the data transfer apparatus and the data transfer method of the present invention have been mainly described. However, as a recording medium of the present invention, the recording medium of each means described above is used. A recording medium that stores a program that causes a computer to execute all or a part of the functions or all or a part of each step is included.

[0069]

As is clear from the above description, the present invention distributes the load on the bus to
It is possible to provide a data transfer device, a data transfer method, and a recording medium that can suppress occurrence of a response delay and greatly improve reliability.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an operation timing of the data transfer device according to the first embodiment of the present invention.

FIG. 3 is a flowchart of a software program according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a video interface of a data transfer device according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of an operation timing of a data transfer device according to a second embodiment of the present invention.

FIG. 6 is a flowchart of a software program according to the second embodiment of the present invention.

FIG. 7 is a configuration diagram of a video interface of a data transfer device according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a video interface of a data transfer device according to a fourth embodiment of the present invention.

FIG. 9 is a flowchart of a software program according to the fifth embodiment of the present invention.

FIG. 10 is a system configuration diagram showing a conventional data transfer device.

FIG. 11 is a diagram showing an example of operation timing of a conventional data transfer device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 video interface 2 control means 3 delay time storage means 4 measuring means 5 delay time determination means 6 stream information holding means 101 CPU 102 memory 103 bus 200 reference signal 210 normal speed signal 220 quadruple speed signal 230 synchronization signal

Claims (18)

[Claims] A memory for holding data; and a data input / output means for inputting / outputting the data to / from the memory at regular intervals via a bus, wherein the data input / output means comprises: Delay time storage means for storing a delay time set as a time for shifting the input / output timing of the data from the reference time for each constant time, and, according to the data transfer processing, shifting the timing by the delay time A data transfer device, comprising: control means for inputting and outputting data. 2. The data input / output unit is capable of inputting / outputting the plurality of data corresponding to a plurality of streams at regular intervals, and the control unit is configured to control the data input / output unit to Wherein the data corresponding to at least one of the plurality of streams is input and output at a timing shifted by the delay time. The data transfer device according to claim 1, wherein 3. The data transfer device according to claim 1, further comprising a delay time determining unit that sets and / or resets the delay time. 4. A measuring means for measuring a transfer processing time of the data on the bus at every constant time, wherein the delay time determining means sets the fixed time so that the transfer processing time approaches a predetermined value. 4. The data transfer device according to claim 3, wherein the delay time is reset every time the time elapses. 5. When the plurality of data respectively corresponding to the plurality of streams are input / output at a certain time interval, the type of each stream being processed is associated with a transfer amount as stream information. A stream information holding unit for storing, the control unit refers to the stream information, and converts the data corresponding to the stream having the smaller transfer amount among the plurality of streams by the delay time. The data transfer device according to claim 3, wherein input / output is performed at a shifted timing. 6. When the plurality of data respectively corresponding to the plurality of streams are input / output at a predetermined time interval, the type of each stream being processed is associated with a transfer amount as stream information. A stream information holding unit for storing, wherein the delay time determining unit refers to the stream information, and the delay time is relatively short for the data corresponding to the stream having the relatively large transfer amount. As described above, for the data corresponding to the stream having a relatively small transfer amount, the delay time is relatively long,
The data transfer device according to claim 3, wherein the delay time is set and / or reset. 7. The stream information holding unit stores the priority of data transfer processing for each type of the stream, and the control unit sets the delay time set or reset to a predetermined allowable maximum. When the time is longer than the delay time, the stream for which input / output of data is stopped is selected in accordance with the priority, and at least within the certain time corresponding to the delay time, input / output of the data corresponding thereto is performed. 7. The data transfer device according to claim 5, wherein the data transfer is not performed. 8. When the plurality of data respectively corresponding to the plurality of streams are input / output at the fixed time, the type of each stream being processed is associated with the priority of each data transfer process. Stream information holding means for storing the stream information as stream information, the delay time determining means refers to the stream information,
4. The data transfer device according to claim 3, wherein the delay time is set and / or reset so that the data corresponding to the type of the stream having the lower priority has a longer delay time. 9. The delay time determining means stores the delay time set or reset most frequently under substantially the same transfer condition as a standard delay time for each transfer condition,
9. The transfer method according to claim 3, wherein, under subsequent transfer conditions substantially the same as the stored transfer conditions, the delay time set first is set to the same value as the standard delay time. The data transfer device according to any one of the above. 10. A CPU connected to the bus and performing input / output processing of the memory according to a software program.
The data transfer device according to any one of claims 3 to 9, further comprising: 11. The data input / output means or the CP
U has the delay time determining means, and when the CPU has the delay time determining means, the delay time is set according to processing of the software program. The data transfer device according to any one of the above. 12. When both or one of the measuring unit and the stream information holding unit is provided, the data input / output unit or the CPU has the both or one of them together with the delay time determining unit. The data transfer device according to claim 11, wherein: 13. When the plurality of data respectively corresponding to a plurality of streams are transferred via a bus at regular time intervals, the data corresponding to at least one of the plurality of streams is transmitted. A data transfer method comprising a delay transfer step of transferring data at a timing shifted by a predetermined delay time. 14. The delay transfer step, wherein the delay time is reset every time the fixed time elapses so that a transfer processing time of the data on the bus within the fixed time approaches a predetermined value. 14. The data transfer method according to claim 13, further comprising a delay time resetting step. 15. The standard delay time storing step of storing the most frequently set or reset delay time as a standard delay time for each transfer condition under substantially the same transfer condition. A delay time initial setting step of setting the initially set delay time to the same value as the standard delay time under substantially the same transfer conditions as the stored transfer conditions. 15. The data transfer method according to 14. 16. In the case where the plurality of data respectively corresponding to the plurality of streams having different transfer amounts are transferred at the predetermined time intervals, in the delay transfer step,
The data according to any one of claims 13 to 15, wherein the data corresponding to the stream having the smaller transfer amount among the plurality of streams is transferred at a timing shifted by the delay time. Transfer method. 17. The delay transfer step, wherein when the set or reset delay time is longer than a predetermined allowable maximum delay time, the stream for which data input / output is stopped is selected. 17. The data transfer method according to claim 13, further comprising a transfer stop step of not transferring the data corresponding to the delay time within the predetermined time. 18. The method according to claim 1, wherein
A recording medium storing a program for causing a computer to execute all or a part of the function of each means or all or a part of each step.