JP2005242437A - Information processor, and information processing method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable each device of a system bus to much more validly utilize the system bus. <P>SOLUTION: An initial away value setting part supplies an initial away value to an initiator in a step S21. An address set processing part supplies an access destination address for setting the latency value of each target corresponding to the initiator in a step S22. A measurement processing performance control part makes the initiator start the performance of measurement processing to the i-th target in a step S24, and monitors a completion flag in a step S25, and when a completion flag has been asserted, increments variables i in a step S26, and when any unprocessed target exists, returns processing to the step S24 to repeat the following processing, and when measurement processing has been performed to all the targets, ends the processing. This invention may be applied to, for example, a PCI bus system. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus, method, and program, and in particular, each device of the system bus makes more effective use of the system bus, for example, by reducing bus traffic by reducing the number of accesses. The present invention relates to an information processing apparatus and method, and a program.

  Conventionally, in an information processing apparatus such as a personal computer, an ISA bus (Industry Standard Architecture bus), a PCI bus (Peripheral Components Interconnect bus), or the like is used as a system bus for connecting each device in the apparatus.

  The PCI bus is a bus standard established by PCI SIG (PCI Special Interest Group), and is rapidly spreading as a standard that replaces the ISA bus, which has long been an industry standard. In the first PCI standard, the bus width (the amount of data that can be sent in one transfer) is 32 bits, the operating frequency (number of transfers per second) is 33 MHz (megahertz), and the maximum data transfer rate is 133 MB / s ( Megabyte second). The latest PCI standard also defines a high-speed specification with a bus width of 64 bits, an operating frequency of 66 MHz, and a maximum data transfer rate of 533 MB / s.

  An example of a PCI bus system using the PCI bus is shown in FIG. The PCI bus system 1 includes the PCI bus 11 as described above and a plurality of PCI devices 12-1 to 12-N connected to the PCI bus 11.

  The PCI devices 12-1 to 12-N access each other via the PCI bus 11, and exchange commands and transfer data. Communication via the PCI bus 11 is controlled by a PCI bus controller (not shown), and the right to use the bus is assigned based on a request from a PCI device.

  For example, one of the PCI devices 12-1 to 12 -N connected to the PCI bus 11, and the initiator 14 that controls the PCI data transfer 13 is first a PCI bus controller (not shown). Request the right to use the bus. When the right to use the PCI bus 11 is given from the PCI bus controller, the initiator 14 is connected to the target 15 via the local bus 16 with respect to the target 15 which is a PCI device to be a communication partner in the PCI data transfer 13. The data stored in the local memory 17 is requested (read request). The target 15 that has acquired the read request from the initiator 14 reads data corresponding to the address requested from the local memory 17 via the local bus 16 and accumulates it in the built-in cache memory 18. When the requested data is accumulated in the cache memory 18 and preparation for data transfer is completed, the target 15 supplies the data to the initiator 14 via the PCI bus 11. When the initiator 14 acquires data from the target 15, the initiator 14 ends the PCI data transfer 13 and releases the PCI bus 11.

  Details of the exchanges performed between the initiator 14 and the target 15 in the PCI data communication 13 are shown in FIG. As shown in FIG. 2, the initiator 14 given the right to use the PCI bus 11 first issues a read request 21-1 to the target 15 and supplies it to the target 15 through the PCI bus 11. (Arrow 22-1 and Arrow 24-1). As a result, a transaction 23-1 occurs on the PCI bus 11. When a read request is supplied as indicated by an arrow 24-1, the target 15 performs a response process 25-1, accesses the local memory 17 via the local bus 16 as indicated by an arrow 26, and receives the requested address. Processing for acquiring data and storing it in the cache memory 18 is started. At this time, since the data (cache data) in the cache memory 18 is invalid data 27 that is not the requested data, the target 15 returns a retry process to the initiator 14 without supplying the cache data. (Arrow 28-1 and Arrow 29-1).

  When the initiator 14 detects the retry 30-1 supplied in this way, the initiator 14 temporarily releases the PCI bus 11 so as not to occupy the PCI bus 11 unnecessarily. However, the initiator 14 immediately secures the right to use the bus again as indicated by an arrow 31-1 so as not to unnecessarily extend the waiting time, and reads after several clocks as in the case of the read request 21-1. A request 21-2 is issued to the target 15. The target 15 performs response processing 25-2 to the read request supplied as indicated by the arrows 22-2 and 24-2, and invalid data is still accumulated in the cache memory 18, so that the above-described response Similar to the case of the process 25-1, the retry process is returned to the initiator 14 (arrow 28-2 and arrow 29-2). A new transaction 23-2 is generated on the PCI bus 11 by such a command exchange.

  When the initiator 14 detects the retry 30-2, the PCI bus 11 is once released, the right to use the PCI bus 11 is secured again, and the read request 21 is received after several clocks, as when the retry 30-1 is detected. -2 is issued to the target 15.

  The initiator 14 and the target 15 repeat the above-described processing ((M−1) times) until the requested data is accumulated in the cache memory 18. The initiator 14 issues an M-th read request and supplies it to the target 15 via the PCI bus 11 (transaction 23-M) as indicated by arrows 22-M and 24-M. If the valid data 32 is stored in the cache memory 18 when the response process 25-M is performed, the target 15 accesses the cache memory 18 as indicated by an arrow 33 as the response process 25-M. The valid data 32 is supplied to the initiator 14. The valid data 32 is supplied to the initiator 14 via the PCI bus 11 (transaction 35) as indicated by arrows 34 and 36. The initiator 14 acquires the valid data 37 supplied in this way.

  As described above, until the preparation for data transfer in the target 15 is completed (section 41), the target 15 issues a retry process to the read request from the initiator 14, and the initiator 14 detects this retry. Repeat the read request based on Therefore, in this case, in the section 41, M-2 transactions occur on the PCI bus 11, and these become unnecessary traffic and occupy the PCI bus 11.

  In the PCI bus system 1, for example, as shown in FIG. 3, burst transfer for transferring a plurality of data at a time by one command can be executed. In this case, the transaction by the retry processing as described above occurs only when the first command is issued.

  In addition, there is a method of reducing transactions in the section 41 by using a target prepared in advance with information on the standby time of the initiator (see, for example, Patent Document 1). In this case, the predetermined register of the target holds in advance latency information, that is, information on the time until the target is ready for data transfer after receiving the request, in response to the access request from the initiator, The information is supplied to the initiator. When the initiator acquires the information, when requesting PCI data transfer to the target, the initiator waits for a time specified by the latency information supplied from the target after making a retry, and then makes a transfer request. That is, in this case, the initiator does not repeat the request until the target is ready.

JP-A-10-293744

  However, in the bus system as described above, as shown in FIG. 2, when a read request is issued again immediately after detecting a retry for the read request issued by the initiator 14, the initiator 14 performs processing in this way. , The target 15 can start data transfer as soon as it is ready for data transfer, but it generates unnecessary traffic on the PCI bus 11 as described above until the target 15 is ready. In other words, other master devices may not be able to use the PCI bus 11 during that time because the bus is substantially occupied during that time.

  In particular, in the case of a bus system in, for example, video equipment or a broadcasting station server, it is necessary to frequently transfer a large amount of data such as video data and audio data. In such a video device, for example, video data captured from the outside is recorded on a recording medium, video data recorded on the recording medium is reproduced, displayed on a monitor, or output to the outside. Is mainly performed. Therefore, each data transfer in the bus system often requires immediacy, and in the data transfer via the bus, if the standby time becomes too long due to unnecessary traffic as described above, a recording process, a reproduction process, etc. Could collapse.

  In addition, as described with reference to FIG. 3, there is a method for efficiently transferring a large amount of data by burst transfer. However, even in this case, unnecessary traffic is generated by retry processing in the first command issue phase. End up. In the case of such a burst transfer, at first glance, since a transaction due to a read request does not occur during a subsequent series of data transfer, the bus traffic seems to be reduced, but the series of data transfer starts data transfer. Since the time from when the bus is released until the bus is released becomes longer, the bus occupation time by one PCI data transfer becomes longer. That is, for other master devices, the waiting time itself for the originally necessary transaction becomes long. Therefore, when burst transfer is performed in this way, the allowable amount of other master devices with respect to the waiting time due to unnecessary traffic as described above is smaller than that of normal data transfer.

  Furthermore, in order to avoid this unnecessary traffic, in the case of a method for causing the target to hold information related to the standby time of the initiator, each target holds information related to the standby time in advance so that it can be received from the master device (initiator). It was necessary to be able to perform processing such as supplying an access request to the initiator. In general, if all devices are developed in a bus system, the manufacturing cost increases. Therefore, it is possible to use existing devices as targets. In such a case, in a data transfer process targeting a conventional device that cannot perform such a process, there is a possibility that a transaction due to a retry process as shown in FIG. 2 may occur.

  In the bus system, it is assumed that various devices are connected to the bus depending on circumstances. Therefore, such a waiting time is not always determined only by the performance of the target, and may vary depending on, for example, the performance of the master device (initiator), the performance of the PCI bus controller, or the connection status of the device. is there. Therefore, in this way, when the target always supplies the same latency information (specifying the waiting time) to any master device, the initiator is not ready for data transfer of the target because the waiting time is too short. However, it makes an access request again (ie, a retry occurs), waits too long, and waits unnecessarily even though the target is ready for data transfer. The data transfer efficiency may also be reduced.

  The present invention has been made in view of such a situation, and enables each device of the system bus to utilize the system bus more effectively.

  The information processing apparatus of the present invention controls a waiting time until a master device, which is a device that performs data transfer by controlling data transfer, issues a command requesting the start of data transfer, and reissues the command, Latency value that sets the value corresponding to the master device waiting time measured by the measuring means that measures the master device waiting time set as the waiting time of the master device as the latency value that the master device uses in data transfer And setting means.

  The measuring means controls the standby time, and measures the time from the acquisition of the command by the target, which is the partner device of the master device to the data transfer, to the preparation of the data transfer as the master device standby time. can do.

  The measuring means controls the standby time so as to measure a master device standby time longer than a time from when a target, which is a device to which the master device is to transfer data, acquires a command and prepares for data transfer. Can be.

  The measuring means may control the standby time and measure an optimal standby time that is a standby time optimized to be the shortest as the master device standby time.

  The measuring means can control the standby time and measure the optimal standby time on the control unit of the standby time.

  The control unit may be a time unit based on a system clock of the information processing apparatus.

The measuring means can measure the master device standby time by causing the master device to repeatedly execute data transfer while controlling the standby time to change the length of the standby time.

  Counting means for counting the clock is further provided, and the measuring means changes the length of the waiting time by changing the number of clocks to be counted by the counting means while the period during which the counting process is being performed by the counting means is set as the waiting time. However, the master device standby time can be measured by causing the master device to repeatedly execute data transfer.

  The apparatus further comprises initial standby time setting means for setting an initial value of standby time in data transfer repeatedly executed by the master device in the measurement processing by the measurement means, and the measurement means is set by the initial standby time setting means in the measurement processing The initial value can be used to cause the master device to perform an initial data transfer.

  In the data transfer repeatedly executed in the measurement process, the measurement unit sets the initial value set by the initial standby time setting unit as the maximum value of the standby time, and the standby time is shortened each time the master device repeats the data transfer. So that the waiting time can be reset.

  The measurement means is a response indicating that the preparation for data transfer is not completed, issued to the master device by the target corresponding to the data transfer while resetting the standby time so that the standby time is shortened. Until the retry is detected, the master device can repeatedly execute the data transfer.

  When the measurement unit detects a retry, it can stop repeating the data transfer and set the standby time in the previous data transfer as the master device standby time.

  The measuring unit measures a master device standby time for each target with respect to one master device, and the latency value setting unit calculates a value corresponding to the master device standby time for each target measured by the measuring unit. It can be set as a latency value for each.

  In the measurement process by the measurement unit, the measurement unit further includes an address setting unit that sets an access destination address accessed by the master device, and the measurement unit transfers data to the access destination address set by the address setting unit. It is possible to control the waiting time until the command is reissued after issuing the command requesting the start of the device, and measure the master device waiting time.

  The address setting means sets two different access destination addresses corresponding to one target, and the measuring means alternately selects the master device for the two access destination addresses set by the address setting means. The master device waiting time can be measured based on both of the two data transfers to be performed.

  Master device specifying means for specifying a master device for performing data transfer for measuring the master device standby time by the measuring means from among a plurality of devices connected to the system bus is further provided, and the measuring means is specified as the master device. The master device standby time corresponding to the master device can be measured.

  Measurement processing execution control means for controlling execution of measurement processing by the measurement means can be further provided.

  The control unit may include a device selection unit that selects a device that performs data transfer in which the measurement unit measures the master device standby time, and a start control unit that controls the start of measurement processing by the measurement unit. .

  In the data transfer performed by the plurality of devices to each other via the system bus, a retry issued by the target to the master device indicating a response indicating that preparation for data transfer is not completed is detected. Retry monitoring means for monitoring the number is further provided, and the start control means starts measurement processing by the measurement means when the retry monitoring means detects more retries than a predetermined number in one data transfer. You can make it.

  The information processing method of the present invention controls a waiting time until a master device, which is a device that controls data transfer and performs data transfer, issues a command requesting the start of data transfer and reissues the command, A measurement step for measuring the master device standby time set as the master device standby time, and a value corresponding to the master device standby time measured by the processing of the measurement step are set as a latency value used by the master device in data transfer. And a latency value setting step.

  The program of the present invention controls a waiting time until a master device, which is a device that controls data transfer and performs data transfer, issues a command requesting the start of data transfer and reissues the command. Latency value that sets the master device standby time that is set as the standby time for the master device and the value that corresponds to the master device standby time measured by the processing of the measurement step as the latency value that the master device uses for data transfer Let the computer execute the configuration steps.

  In the information processing apparatus, method, and program according to the present invention, the master device, which is a device that controls data transfer and performs data transfer, issues a command for requesting the start of data transfer and then issues the command again. The standby time is controlled, the master device standby time set as the master device standby time is measured, and a value corresponding to the measured master device standby time is set as a latency value used by the master device in data transfer.

  According to the present invention, data transfer can be controlled. In particular, each device of the system bus can use the system bus more effectively, for example, by reducing the traffic of the bus by reducing the number of accesses.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

  The present invention has a system bus (for example, PCI bus 110 in FIG. 4) to which a plurality of devices (for example, PCI device 111 in FIG. 4) are connected, and the plurality of devices are connected to each other via the system bus. An information processing apparatus (for example, the image processing apparatus 100 of FIG. 4) that performs data transfer (for example, the PCI data transfer 112 of FIG. 4) is provided. In this information processing apparatus, a master device (for example, the initiator 113 in FIG. 4) that controls data transfer and performs data transfer requests a command (for example, a read request 321-in FIG. 14) that requests the start of data transfer. 1) After issuing 1), the master device that controls the standby time (eg, section 341 in FIG. 14) until the command (eg, read request 321-2 in FIG. 14) is reissued and is set as the standby time of the master device Measuring means for measuring the waiting time (for example, the section 411 in FIG. 19) (for example, the measurement processing unit 131 in FIG. 14 that executes the processes in steps S61 to S70 in FIG. 11 and steps S81 to S89 in FIG. 12). And the value corresponding to the master device standby time measured by the measuring means Latency values have been used (e.g., latency value 283 in FIG. 6) and a latency value setting means for setting as a (e.g., measurement processing unit 131 in FIG. 14 for executing the processing of step S92 or step S95 in FIG. 13).

  The measuring means controls the standby time, and prepares for the data transfer after the target (for example, the target 114 in FIG. 4), which is the device that is the data transfer partner of the master device, acquires the command as the master device standby time. The time until adjustment (for example, the time from time T1 to time T2 in FIG. 14) can be measured.

  The measuring means controls the standby time, and the time from when the target (for example, the target 114 in FIG. 4), which is the device to which the master device transfers data, obtains the command until preparation for data transfer is completed (for example, The master device standby time (for example, section 411 in FIG. 19) longer than the time T1 to time T2 in FIG. 14 can be measured.

  The measurement means controls the standby time, and measures the optimum standby time (for example, section 411 in FIG. 19) that is the standby time optimized to be the shortest time as the master device standby time. be able to.

  The measuring means controls the standby time, and can measure the optimal standby time on the control unit of the standby time (for example, the section 361A in FIG. 17).

  The control unit may be a time unit based on a system clock (for example, CLK in FIG. 15) of the information processing apparatus.

  The measurement unit controls the standby time to change the length of the standby time (for example, step S69 in FIG. 11 or step S88 in FIG. 11), and causes the master device to repeatedly execute data transfer (for example, FIG. 11). The master device standby time can be measured by performing steps S62 to S68 of FIG. 12 or steps S81 to S87 of FIG.

  Counting means for counting clocks (for example, the away timer 255 in FIG. 6) is further provided, and the measuring means sets the number of clocks to be counted by the counting means (for example, the counting time as a waiting time) The master device standby time can be measured by causing the master device to repeatedly perform data transfer while changing the length of the standby time by changing the away timer value 285) of FIG.

  Initial waiting time setting means (for example, initial away value setting in FIG. 5) for setting an initial value (for example, initial away value 284 in FIG. 6) of waiting time in data transfer repeatedly executed by the master device in the measurement processing by the measuring means. Unit 204), and the measurement means can cause the master device to execute the first data transfer in the measurement process using the initial value set by the initial standby time setting means.

  In the data transfer repeatedly executed in the measurement process, the measurement unit sets the initial value set by the initial standby time setting unit as the maximum value of the standby time, and the standby time is shortened each time the master device repeats the data transfer. Thus, the standby time can be reset (for example, step S69 in FIG. 11 or step S88 in FIG. 12).

  The measurement means is a response indicating that the preparation for data transfer is not completed, issued to the master device by the target corresponding to the data transfer while resetting the standby time so that the standby time is shortened. Until the retry (for example, retry 330-1 in FIG. 14) is detected, the master device can repeatedly execute the data transfer (for example, step S67 in FIG. 11 or step S86 in FIG. 12).

  When the measurement unit detects a retry, it can stop repeating the data transfer and set the standby time in the previous data transfer as the master device standby time (for example, step S91 in FIG. 13). .

  The measuring unit measures a master device standby time for each target with respect to one master device, and the latency value setting unit calculates a value corresponding to the master device standby time for each target measured by the measuring unit. Each latency value (for example, the latency value 283 set in each latency value register 273 of the target-specific register spaces 261-1 to 261-3 in FIG. 6) may be set.

  In the measurement process by the measurement unit, the measurement unit further includes an address setting unit (for example, the address setting unit 202 in FIG. 5) for setting an access destination address (for example, the address A221 or the address B222 in FIG. 5) accessed by the master device. The means controls the waiting time until the master device issues a command for requesting the start of data transfer to the access destination address set by the address setting means and then issues the command again. Can be measured.

  The address setting means sets two different access destination addresses (for example, address A221 and address B222 in FIG. 5) corresponding to one target, and the measuring means is set by the master device by the address setting means. The master device waiting time can be measured based on both of the two data transfers executed alternately with respect to the two accessed addresses.

  Master device specifying means (for example, master specifying unit 203 in FIG. 5) for specifying a master device for performing data transfer for measuring the master device standby time by the measuring means from among the plurality of devices connected to the system bus. The measuring means may measure a master device standby time corresponding to the master device specified as the master device.

  A measurement process execution control unit (for example, the measurement process execution control unit 206 in FIG. 5) that controls execution of the measurement process by the measurement unit may be further provided.

  The control means is a device selection means for selecting a device that performs data transfer in which the measurement means measures the master device standby time (for example, the measurement process execution control unit in FIG. 5 that executes the processes in steps S26 and S27 in FIG. 9). 206) and start control means for controlling the start of the measurement process by the measurement means (for example, the measurement process execution control unit 206 in FIG. 5 that executes the process in step S24 in FIG. 9). it can.

  In data transfer performed by the plurality of devices to each other via the system bus, a retry issued by the target to the master device indicating that the preparation for data transfer is not completed (for example, retry 330 in FIG. 14). -1) is detected, and further includes a retry monitoring unit (for example, the retry monitoring unit 421 in FIG. 21) for monitoring the number of retries, and the start control unit performs a single data transfer by the retry monitoring unit. When more retries are detected than a predetermined number, a measurement process by the measurement unit can be started (for example, step S135 and step S136 in FIG. 22).

  The present invention has a system bus (for example, PCI bus 110 in FIG. 4) to which a plurality of devices (for example, PCI device 111 in FIG. 4) are connected, and the plurality of devices are connected to each other via the system bus. An information processing method of an information processing apparatus (for example, the image processing apparatus 100 of FIG. 4) that performs data transfer (for example, the PCI data transfer 112 of FIG. 4) is provided. In this information processing method, a master device (for example, the initiator 113 in FIG. 4) that controls data transfer and performs data transfer requests a command (for example, a read request 321 in FIG. 14) that requests the start of data transfer. -1) is issued, and a standby time (for example, section 341 in FIG. 14) until a command (for example, read request 321-2 in FIG. 14) is reissued is controlled and set as a standby time of the master device. A measurement step (for example, step S61 to step S70 in FIG. 11 and step S81 to step S89 in FIG. 12) for measuring the device standby time (for example, section 411 in FIG. 19), and the master measured by the processing of the measurement step The value corresponding to the device wait time is the rate that the master device uses for data transfer. Shi value (e.g., latency value 283 in FIG. 6) and a latency value setting step of setting as a (e.g., step S92 or step S95 in FIG. 13).

  The present invention has a system bus (for example, PCI bus 110 in FIG. 4) to which a plurality of devices (for example, PCI device 111 in FIG. 4) are connected, and the plurality of devices are connected to each other via the system bus. A program for causing a computer (for example, the image processing apparatus 100 in FIG. 4) to perform a process for performing data transfer (for example, the PCI data transfer 112 in FIG. 4) is provided. In this program, a master device (for example, the initiator 113 in FIG. 4) that controls data transfer and performs data transfer requests a command (for example, a read request 321-1 in FIG. 14) to request the start of data transfer. Device standby time to control the standby time (for example, section 341 in FIG. 14) until the command (for example, read request 321-2 in FIG. 14) is reissued and set as the standby time of the master device The master device standby time measured by the measurement step (for example, step S61 to step S70 in FIG. 11 and step S81 to step S89 in FIG. 12) for measuring (for example, the section 411 in FIG. 19) and the process of the measurement step. The latency value used by the master device for data transfer (example If, and a latency value setting step of setting a latency value 283 in FIG. 6) (e.g., step S92 or step S95 in FIG. 13).

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 4 shows a main configuration example of an image processing apparatus to which the present invention is applied.

  The image processing apparatus 100 shown in FIG. 4 is a video device such as a video data recording / reproducing apparatus, for example, and a PCI bus (Peripheral Components Interconnect bus) 110 is applied as a system bus.

  For example, the PCI bus 110 has a bus width (the amount of data that can be sent in one transfer) of 32 bits, an operating frequency (number of transfers per second) of 33 MHz (megahertz), and a maximum data transfer rate of 133 MB / s (megabyte par) This is the second bus.

  PCI devices 111-1 to 111 -N are connected to the PCI bus 110. In the following, when there is no need to distinguish between the PCI devices 111-1 to 111 -N, they are referred to as PCI devices 111. In FIG. 4, the PCI device 111 is connected to the PCI bus 110 by a double-headed arrow, but is actually connected by a plurality of signal lines, a power source, a ground, and the like. As the PCI device 111, various devices that can mutually transfer data via the PCI bus 110 are applied. For example, a SCSI (Small Computer System Interface) interface, an IDE (Integrated Drive Electronics) interface, a mass storage controller such as a flexible disk drive, a network controller such as an Ethernet (registered trademark) interface or an ATM (Asynchronous Transfer Mode) interface, Multimedia controllers such as video controllers and audio controllers, memory controllers such as SDRAM (Synchronous Dynamic Random Access Memory) and flash memory, ISA (Industry Standard Architecture) bridge, PCI-PCI bridge, PCMCIA (Personal Computer Memory Card International Association) bridge Bridges, input interfaces such as keyboard and mouse, processors such as CPU, IEEE (Institute of Electrical and Electronic Engineers) 1394 and USB (Universal Serial Bus) Controller or the like is included in the serial bus and the like. Of course, other devices may be connected to the PCI bus 110 as the PCI device 111.

  Hereinafter, a PCI device that controls data transfer (PCI data transfer) performed via the PCI bus 110 is referred to as a master, and a PCI device that is a communication partner of the master is referred to as a target. In addition, the PCI device 111 that can operate as a master is referred to as a master device, and a device that operates only as a target is referred to as a target device.

  In one PCI data transfer, there is only one PCI device 111 operating as a master, and the master at this time is called an initiator. That is, in one PCI data transfer, the initiator controls data transfer as a master, communicates with other targets, and exchanges data. Note that the master device may operate as a target and perform PCI data transfer with other master devices. The initiator in the PCI data transfer at this time is another master device.

  In FIG. 4, an initiator 113 is one of the PCI devices 111, and accesses a target 114 that is also one of the PCI devices to perform PCI data transfer 112. That is, the initiator 113 controls the PCI data transfer 112 to the target 114. In the following, the PCI data transfer 112 by the initiator 113 and the target 114 will be described. However, the PCI data transfer 112 does not indicate data transfer between specific PCI devices, but all data transfer in the PCI bus system of the PCI bus 110. Can be adapted to. That is, the initiator 113 indicates an arbitrary master device included in the PCI device 111, and the target 114 indicates all the PCI devices 111 that perform PCI data transfer with the initiator 113.

  The target 114 is a device that is connected to the PCI bus 110 and is connected to the local memory 121 via the local bus 120 and controls input / output of data in the local memory 121. The target 114 has a cache memory 122 inside. The cache memory 122 is used for data transfer and the like, for example, to absorb a difference in data transfer speed between the PCI bus 110 and the local bus 120. For example, when the initiator 113 requests the target 114 to read data in the local memory 121 by the PCI data transfer 112, the target 114 first accesses the local memory 121 via the local bus 120 and is requested. Data is read and held in the cache memory 122. Then, the data to be transferred is held in the cache memory 122, and when preparation for data transfer is completed, the target 114 supplies it to the initiator 113 via the PCI bus 110.

  The initiator 113 includes a measurement processing unit 131 that measures an optimum waiting time after outputting a command in the PCI data transfer 112 to the target 114. As will be described in detail later, the measurement processing unit 131 is controlled by the CPU 141, and an optimum standby time (optimal time) as a master device standby time that is a time for which the initiator 113 waits for all targets to which PCI data transfer is performed. (Waiting time) is measured. The initiator 113 implements effective use of the PCI bus 110 by performing the PCI data transfer 112 using the standby time measured by the measurement processing unit 131.

  A CPU (Central Processing Unit) 141 that controls the entire image processing apparatus 100 is also connected to the PCI bus 110. The CPU 141 accesses the main memory 161 via the host bus 160, executes various processes according to a program loaded in the main memory 161, and controls the operation of each unit of the image processing apparatus 100. The main memory 161 also appropriately stores data necessary for the CPU 141 to execute various processes. The CPU 141 has a host PCI bridge 151 therein, and also operates as a bridge between the PCI bus 110 and the host bus 160 that connects the CPU 141 and the main memory 161. Further, the CPU 141 includes a latency value setting control unit 152 that controls processing for setting an optimal standby time (optimal standby time) as a master device standby time that each master device waits after outputting a command. The CPU 141 uses the latency value setting control unit 152 to cause each master device to set a standby time (latency value) for each target before starting the data transfer process on the PCI bus 110.

  Although not shown, the host PCI bridge 151 of the CPU 141 includes a PCI bus controller that controls data transfer in the PCI bus 110, an arbiter that assigns control rights for data transfer, and the like.

  The CPU 141 further includes a ROM (Read Only Memory) 171 in which programs and data executed by the CPU 141 are stored in advance, a rewritable flash memory, and the like, and a storage unit 172 in which programs and data executed by the CPU 141 are stored. Also connected is a drive 173 that reads the program and data stored in the attached removable medium 174 and supplies it to the CPU 141 under the control of the CPU 141. Further, other devices such as an input device such as a keyboard and an output device such as a monitor may be connected to the CPU 141 as a matter of course.

  FIG. 5 is a block diagram showing an example of a detailed configuration inside the CPU 141 of FIG. In FIG. 5, the CPU 141 is shown only for the processing unit related to the setting of the latency value of the initiator 113.

  The CPU 141 includes a PCI configuration processing unit 201, an address setting unit 202, and a master specifying unit 203 in addition to the host PCI bridge 151 and the latency value setting control unit 152.

  The PCI configuration processing unit 201 accesses each PCI device 111 via the host PCI bridge 151, and for each PCI device, a memory address, an I / O address, an interrupt level, and a DMA (Direct Memory Access transfer) channel Configuration processing for assigning system resources such as, loading / unloading drivers, setting various parameters, and the like is performed. Then, the PCI configuration processing unit 201 supplies the processing result to the address setting unit 202.

  The address setting unit 202 sets the access destination address of each target in the latency value setting process based on the address assigned by the PCI configuration processing unit 201, and sets it as the latency value setting access destination of the latency value setting control unit 152. This is supplied to the address holding unit 207 and held. The address setting unit 202 supplies the configuration processing result supplied from the PCI configuration processing unit 201 to the master specifying unit 203.

  The master specifying unit 203 specifies a master device from the PCI devices 111 connected to the PCI bus 110 based on the configuration processing result by the PCI configuration processing unit 201. In addition, the master specifying unit 203 supplies information regarding the specified master device to the initial away value setting unit 204 of the latency value setting control unit 152.

  The latency value setting control unit 152 includes an initial away value setting unit 204, an address set processing unit 205, a measurement process execution control unit 206, and a latency value setting access destination address holding unit 207.

  The initial away value setting unit 204 is a processing unit that sets an initial away value that is an initial value of the standby time used when each master device measures the standby time for each target, and is specified by the master specifying unit 203. The initial away value 211 held in advance is supplied to the master device via the host PCI bridge 151 and set.

  The address set processing unit 205 acquires the latency value setting access destination address set by the address setting unit 202 and held in the latency value setting access destination address holding unit 207, and the master specified by the master specifying unit 205 The access target address for setting the latency value of the corresponding target is supplied to the device via the host PCI bridge 151.

  The measurement processing execution control unit 206 accesses each master device via the host PCI bridge 151 and controls the measurement processing unit 131 included in each master device to execute measurement processing on the target. The measurement process execution control unit 206 includes a completion flag 212 indicating the completion of the measurement process. When the measurement process unit 131 of the master device (initiator) ends the measurement process, the completion flag 212 is turned on. Set (assert). The measurement process execution control unit 206 determines whether or not the measurement process by the master device is completed based on the value of the completion flag 212.

  As shown in FIG. 5, the latency value setting access destination address holding unit 207 sets the latency value setting access destination address for each target set by the address setting unit 202 as the latency value setting access destination address 213-1. .., 213-2, 213-3,..., And the addresses are supplied to the address set processing unit 205 as necessary. The address setting unit 202 sets two addresses (address A221 and address B222) as latency value setting access destination addresses for each target, as will be described later. The latency value setting access destination address holding unit 207 holds these two addresses (address A and address B) for each target.

  FIG. 6 is a block diagram illustrating a detailed internal configuration example of the initiator 113 in FIG. In FIG. 6, the initiator 113 is omitted for blocks related to normal processing as the PCI device 111, and only the processing unit related to setting of the latency value is shown.

  6, in addition to the above-described measurement processing unit 131, the initiator 113 includes a PCI interface processing unit 251 that performs interface processing between the PCI bus 110 and the inside of the initiator 113, and a device control unit that controls the operation of each unit of the initiator 113. 252, an initial away value setting processing unit 253 that sets an initial away value used in the standby time measurement process by the measurement processing unit 131 in a register, and a target latency value setting used in the standby time measurement process by the measurement processing unit 131 The information is controlled by the address set processing unit 254 and the measurement processing unit 131 for setting the access destination address in the register, and stores information such as an away timer 255 that is a timer used for measuring a waiting time (latency value), and various registers. RAM (Random Access Memory) 256 doing.

  The PCI device 251 is a processing unit that performs interface processing with the PCI bus 110, and is connected to the PCI bus 110, and also includes a device control unit 252, an initial away value set processing unit 253, an address set processing unit 254, and measurement processing. Connected to the unit 131 and the like.

  The device control unit 252 performs processing related to operation control of each unit of the initiator 113. For example, the device control unit 252 operates the respective units such as the initial away value set processing unit 253, the address set processing unit 254, the away timer 255, the RAM 256, and the measurement processing unit 131 based on programs and data loaded in the RAM 256. The timing and processing procedure are controlled, the program and data supplied from the CPU 141 and the like are loaded into the RAM 256, and the program and data held in the RAM 256 are unloaded.

  When the initial away value set processing unit 253 acquires the initial away value supplied from the initial away value setting unit 204 of the CPU 141 via the PCI interface processing unit 251, the initial away value set processing unit 253 stores the initial away value in the initial away value register 274 provided in the RAM 256. And set an initial away value 284.

  When the address set processing unit 254 obtains the latency value setting access destination addresses (address A221 and address B222) supplied from the address set processing unit 205 of the CPU 141 via the PCI interface processing unit 251, they are provided in the RAM 256. To the specified register space for each target.

  The away timer 255 is controlled by the measurement processing unit 131, counts the clock for the away timer value set in the measurement control unit 131, and notifies the measurement control unit 131 when the count is completed.

  In the RAM 256, in addition to programs and data executed by the device control unit 252 and the respective units of the initiator 113, information on targets for which the initiator 113 performs data transfer is stored (set). -2, 261-3,... Are provided as many as the number of targets. In the following description, when there is no need to explain each target register space separately, it is referred to as a target register space 261.

  Each target register space 261 corresponds to a latency value setting access destination address register A271 in which an address A221 which is a target latency value setting access destination address corresponding to each register is stored (set). The latency value setting access destination address register B272 in which the address B222, which is the target latency value setting access destination address, is stored (set), and the target corresponding to each register set by the measurement processing by the measurement processing unit 131. A latency value register 273 is provided in which the latency value 283 is stored (set).

  The address A221 of the latency value setting access destination address register A271 and the address B222 of the latency value setting access destination address register B272 are supplied from the address set processing unit 205 of the CPU 141 via the PCI bus 110, and the address set processing unit 254 Set by Further, these values are referred to by the measurement processing unit 131, and are used for the measurement process as the access destination address of the target when the latency value is set.

  Further, the RAM 256 is provided with an initial away register 274 in which the initial away value 284 is set by the initial away value set processing unit 253. The initial away value 284 is referred to by the measurement processing unit 131 and is used as an initial value of the number of clocks counted by the away timer 255. That is, the initial away value 284 is an initial value of the waiting time until the initiator 113 in the measurement process issues the same command for the same address again after issuing the command.

  Further, the RAM 256 is provided with an away timer value register 275 for storing (setting) an away timer value 285 indicating the number of clocks counted by the away timer in the measurement processing of the measurement processing unit 131. The away timer value 285 set in the away timer value register 275 is the number of clocks counted by the away timer 255 in the measurement process, and the value is updated as the measurement process proceeds. The initial value of the away timer value 285 is set to the initial away value 284.

  The measurement processing unit 131 is controlled by the CPU 141 via the PCI interface 251, refers to the initial away value 284 set in the initial away value register 274, and sets the value in the away timer value register 275 as the away timer value 285. To do. Next, the measurement processing unit 131 is controlled by the CPU 141 to determine a target on which the measurement process is performed, and the latency value setting access destination address (address A221 and address B222) of the target is set to the latency value setting access destination address register. The data is read from A271 and the latency value setting access destination address register B272, and a command is issued to one of the addresses (for example, address A221). When a retry for the command is detected after the command is issued, the measurement processing unit 131 controls the away timer 255 to count the number of clocks of the away timer value 285 set in the away timer value 275.

  When the away timer 255 finishes counting and returns the process, the measurement processing unit 131 accesses the same address again and issues the same command. When the PCI data transfer is started by this command and is normally completed, the measurement processing unit 131 decreases the away timer value 285 set in the away timer value 275 once (for a predetermined number of clocks). To do. Then, the measurement processing unit 131 issues a command to the other address (for example, the address B222). When a retry for the command is detected after the command is issued, the measurement processing unit 131 controls the away timer 255 to count the number of clocks of the away timer value 285 set in the away timer value 275.

  When the away timer 255 finishes counting and returns the process, the measurement processing unit 131 accesses the same address again and issues the same command. When the PCI data transfer is started by this command and is normally completed, the measurement processing unit 131 decreases the away timer value 285 set in the away timer value 275 once (for a predetermined number of clocks). To do. Then, the measurement processing unit 131 issues a command to the first address (for example, address A221).

  By repeating the above process, the measurement processing unit 131 continues the measurement process while gradually decreasing the away timer value 285 (decreasing the standby time). When the retry is detected in the command issuance after waiting for the waiting time corresponding to the away timer value 285, the measurement processing unit 131 ends the measurement process, and the value of the previous away timer value 285 (then A value obtained by incrementing the number of clocks for one time to the away timer value 285 at the time) is stored (set) as a latency value 283 in the latency value register 273 of the target-specific register space 261 corresponding to the target.

  As described above, the initiator 113 performs the optimum standby time measurement process that is optimal as the master device standby time.

  The latency value is set as described above, for example, after the PCI bus 110 is reset at power-on or the like. In the subsequent normal data transfer processing, the latency value set at that time is applied. The

  In FIG. 4, the reset of the PCI bus 110 is executed under the control of the CPU 141. For example, when the initialization processing of the PCI bus 110 is performed according to an instruction from the user or the like, or when the image processing apparatus 100 is powered on, the CPU 141 starts the reset processing. The reset process executed by the CPU 141 will be described with reference to the flowchart of FIG.

  First, in step S1, the PCI configuration processing unit 201 of the CPU 141 executes configuration processing, initializes the PCI bus 110 and the PCI device 111, and performs various settings and assignments. Specifically, the PCI configuration processing unit 201 acquires information related to the PCI device 111 such as a vendor ID, a device ID, and a class code from the configuration register of each PCI device 111 via the PCI bus 110. The PCI configuration processing unit 201 identifies each PCI device 111 based on the ID and code, and system resources such as a memory address, an I / O address, an interrupt level, and a DMA channel for each device. Assignment, driver loading / unloading, and various parameter settings. At this time, the PCI configuration processing unit 201 assigns the address area of each PCI device connected to the PCI bus 110 to the PCI bus address space, that is, the CPU memory space, for example, as shown in FIG. Assign to 300.

  In FIG. 8, the PCI configuration processing unit 201 uses a memory space other than the CPU address area 310 of addresses 00000h to 0FFFFh in the CPU memory space 300 as a target 1 address area 311, a target 2 address area 312, and a target As in the address area 313 for 3, 64 KB is allocated to each target. Also, the PCI configuration processing unit 201 allocates 32 bits each for the register address space and the local memory address space in each target address area. That is, for example, as shown in FIG. 8, the target 1 address area 311 includes a 32 KB target 1 register space 314 from 10000h to 17FFFh and a 32 KB target 1 local memory space 315 from 18000h to 1FFFFh. Is done. The same applies to other target address areas (for example, the target 2 address area 312 and the target 3 address area 313), and each is constituted by a register space and a local memory space.

  When the configuration processing as described above is performed, the PCI configuration processing unit 201 of the CPU 141 ends the configuration processing in step S1 and proceeds to step S2 in FIG.

  In step S2, the address setting unit 202 uses the memory space allocated to each PCI device 111 by the configuration process as described above, and sets the address A and the address B for the latency value setting of each PCI device. Set two each.

  As will be described later, in the measurement process for setting the latency value, the initiator 113 normally repeats access to the same target 114 a plurality of times. On the other hand, the target 114 determines whether or not data is stored in the cache memory 122, and determines whether or not data transfer is ready. Normally, the cache memory 122 holds data of several clocks (for example, 6 clocks) and then discards the data. Therefore, the address setting unit 202 sets only one address as the latency value setting access destination address for one target 114, and the initiator 113 continuously repeats access to the same address of the same target 114. Then, when the access interval becomes narrower, the target 114 determines that the cache memory 122 is not updated with the correct data (the old data remains), but is ready for data transfer. Data) may be transferred to the initiator 113.

  Therefore, the address setting unit 202 sets two addresses as latency value setting access destination addresses so that the access interval to the same address by the initiator 113 does not become too short with respect to the update cycle of the cache memory 122. .

  For example, in the case of FIG. 8, the address setting unit 202 sets the address 18000h as the address A221 from the local memory space 315 of the target 1 in the target 1 address area 311 as the access destination address for setting the latency value of the target 1 Set address 1C000h as B222. Note that these two addresses (address A221 and address B222) are local memory space 315 of target 1 if they are addresses separated from each other to some extent (for example, 512 words) so that each address indicates data for different data transfer. Any address may be used.

  The address setting unit 202 sets the latency value setting access destination addresses for the target 2 and the target 3 in the same manner as in the case of the target 1, and the latency value setting access destination addresses for all the targets. Set. When the access destination addresses for setting latency values of all targets are set, the address setting unit 202 advances the process to step S3.

  In step S <b> 3, the master specifying unit 203 of the CPU 141 determines a master device that can be a master for PCI data transfer from the PCI devices 111 connected to the PCI bus 110 based on the configuration processing result by the PCI configuration processing unit 201. And the process proceeds to step S4. In step S4, the latency value setting control unit 152 of the CPU 141 controls each of the master devices specified by the master specifying unit 203 to perform latency value setting processing. The latency value setting control process for each master device will be described later with reference to the flowchart of FIG.

  After completing the latency value setting control process, the latency value setting control unit 152 ends the reset process. When the reset process ends, each PCI device 111 connected to the PCI bus 110 starts the process of PCI data transfer 112 as necessary.

  Next, the latency value setting control process executed in step S4 of FIG. 7 will be described with reference to the flowchart of FIG. The flowchart of FIG. 9 is a process for the initiator 113 which is one of the master devices.

  When the latency value setting control process is started, the initial away value setting unit 204 of the latency value setting control unit 152 uses the initial away value 211 stored therein as an initiator via the host PCI bridge 151 in step S21. 113, and this value is set in the register (initial away value register 274). The initial away value 211 is a predetermined value, and is the maximum value of the away timer value 285 (latency value 283) as described later.

  The initial away value setting unit 204 that has supplied the initial away value 211 advances the process to step S22. In step S 22, the address set processing unit 205 of the latency value setting control unit 152 corresponds to the initiator 113 from among the latency value setting access destination addresses 213 held in the latency value setting access destination address holding unit 207. The access destination address for setting the latency value of each target 114 (where the initiator 113 can perform data transfer) is supplied to the initiator 113 via the host PCI bridge 151, and these values (address A221 and address B222) are supplied. A register (latency value setting access destination address register A 271 or latency value setting access destination address B 272, whichever address corresponds to) is set.

  The address setting unit 205 that has supplied the latency value setting access destination address proceeds to step S23. In step S <b> 23, the measurement process execution control unit 206 sets the value of the variable i for selecting the master device to be processed as an initial value “0”. At this time, the measurement process execution control unit 206 may be any value as long as it is a predetermined integer initial value.

  When the variable i is set, the measurement process execution control unit 206 accesses the initiator 113 via the host PCI bridge 151 in step S24, and the measurement process for the i-th target 114 among the targets 114 corresponding to the initiator 113. Start running.

  When the measurement process is started, the measurement process execution control unit 206 monitors the completion flag 212 in step S25, determines whether the completion flag 212 is asserted, and the initiator 113 ends the measurement process and completes. Wait until 212 is asserted. Note that if the completion flag 212 is not asserted even after a predetermined time has elapsed since the start of the execution of the measurement process, the measurement process execution control unit 206 forcibly terminates the latency value setting control process. Of course.

  When the initiator 113 asserts the completion flag 212 in step S25 as described above, the measurement process execution control unit 206 proceeds to step S26, increments the variable i, and in step S27, the value of the variable i. Is greater than the number of targets 114 corresponding to the initiator 113. When it is determined that the value of the variable i is not larger than the number of targets, that is, when there are unprocessed targets, the measurement process execution control unit 206 returns the process to step S24 and repeats the subsequent processes.

  That is, the measurement process execution control unit 206 controls the initiator 113 to perform the measurement process on all the targets corresponding to the initiator 113 by repeating the processes of steps S24 to S27. In step S27, when it is determined that the value of the variable i is larger than the number of targets, that is, when it is determined that the initiator 113 has performed measurement processing for all the targets corresponding to the initiator 113, measurement processing execution control is performed. The unit 206 ends the latency value setting control process.

  As described above, the latency value setting control unit 152 of the CPU 141 executes the latency value setting control process after the configuration process. Note that the latency value setting control unit 152 executes the latency value setting control process as described with reference to the flowchart of FIG. 9 for each master device. In other words, the latency value setting control unit 152 performs control so as to calculate a latency value for PCI data transfer by all PCI devices 111 connected to the PCI bus 110.

  In this way, each master device can set an optimum optimum waiting time (latency value) as a waiting time for each target, and by using the optimum waiting time, PCI Occurrence of unnecessary traffic (transaction due to repeated read requests) on the bus 110 is suppressed, and each PCI device 111 can effectively use the PCI bus 110.

  Next, processing related to setting of a latency value by the initiator 113, which is executed under the control of the latency value setting control unit 152 of the CPU 141 as described above, will be described. When power is turned on and configuration processing is performed on the initiator 113 that is the PCI device 111, the device control unit 252 of the initiator 113 controls each unit of the initiator 113 and starts latency value setting processing. The latency value setting process will be described with reference to the flowchart of FIG.

  When the latency value setting process is started, the initial away value set processing unit 253 determines whether or not the initial away value 211 is supplied from the initial away value setting unit 204 of the CPU 141 in step S41. When it is determined that the initial away value 211 has been supplied via the PCI interface processing unit 251, the initial away value set processing unit 253 proceeds to step S42, and the supplied initial away value 211 is stored in the initial away value register 274. Set (initial away value 284).

  The initial away value set processing unit 253 that has set the initial away value 211 (initial away value 284) advances the process to step S43. If it is determined in step S41 that the initial away value 211 is not supplied, the initial away value set processing unit 253 skips step S42 and proceeds to step S43.

  In step S43, the address set processing unit 254 determines whether or not the latency value setting access destination addresses (address A221 and address B222) are supplied from the address set processing unit 205 of the CPU 141. If it is determined that the latency value setting access destination address has been supplied, the address set processing unit 254 advances the process to step S44, and the supplied address is the latency value setting access in the corresponding target register space 261. The supplied address A221 is set in the destination address register A271, and the supplied address B222 is set in the latency value setting access destination address register B272.

  The address set processing unit 254 that has set the address advances the processing to step S45. If it is determined in step S43 that the latency value setting access destination address is not supplied from the address set processing unit 205, the address set processing unit 254 omits the process in step S44 and performs the process in step S45. To proceed.

  In step S <b> 45, the measurement processing unit 131 determines whether or not the measurement process execution control unit 206 of the CPU 141 has instructed the start of the measurement process. When it is determined that the start of the measurement process is instructed, the measurement processing unit 131 advances the process to step S46, and executes the measurement process for the instructed target together with the start instruction of the measurement process. Details of the measurement process will be described later with reference to the flowcharts of FIGS.

  After completing the measurement process in step S46, the measurement processing unit 131 advances the process to step S47. In Step S45, when it is determined that the start of the measurement process is not instructed, the measurement processing unit 131 omits the process of Step S46 and proceeds to Step S47.

  In step S47, the device control unit 252 determines whether to end the latency value setting process. If it is determined not to end the process, the device control unit 252 returns the process to step S41 and repeats the subsequent processes. In step S47, for example, when all the latency values have been set and it is determined that the latency value setting process is to be ended when the mode is shifted to the normal mode or the power is turned off, the device control unit 252 The latency value setting process is terminated.

  Next, details of the measurement process executed in step S46 of FIG. 10 will be described with reference to the flowcharts of FIGS.

  The measurement processing unit 131 that has started the measurement process first reads the initial away value 284, which is the value of the initial away value register 274, in step S61 in FIG. 11, and sets it in the away timer value register 275 (away). Timer value 285). In step S62, the measurement processing unit 131 reads the address A221 set in the latency value setting access destination address A271 of the target-specific register space 261 corresponding to the target 114 specified by the measurement processing execution control unit 206. Then, a read request is made to the target address A221.

  In step S63, the measurement processing unit 131 that has made the read request determines whether data has been acquired as a response to the read request. The measurement processing unit 131 that has determined that data has not been acquired proceeds to step S64, and determines whether or not a retry has been acquired as a response to the read request. If it is determined that neither retry nor data has been acquired, that is, the response to the read request has not been acquired, the measurement processing unit 131 returns the process to step S63 and repeats the subsequent processes.

  If it is determined in step S64 that the retry process has been acquired, the measurement processing unit 131 supplies the away timer value 285 (the number of standby clocks) set in the away timer value register 275 to the away timer 255. The away timer 255 supplied with the away timer value 285 counts clocks corresponding to the supplied away timer value 285 in step S65. The measurement processing unit 131 waits until the end of the count is notified from the away timer 285.

  When the count by the away timer 255 ends, the away timer 255 notifies the measurement processing unit 131 of the end of the count. When the count end is notified, the measurement processing unit 131 advances the process to step S 66, and sets the latency value setting access destination address A 271 in the target-specific register space 261 corresponding to the target 114 specified by the measurement processing execution control unit 206. A read request is made again for the set address A221.

  In step S67, the measurement processing unit 131 that has made the read request again determines whether or not a retry has been acquired as a response to the read request. The measurement processing unit 131 that has determined that the retry has not been acquired from the target 114 proceeds to step S68, and determines whether or not the data requested as a response to the read request has been acquired. If it is determined that neither retry nor data has been acquired, that is, the response to the read request has not been acquired, the measurement processing unit 131 returns the process to step S67 and repeats the subsequent processes.

  If it is determined in step S68 that the requested data has been acquired as a response to the read request, the measurement processing unit 131 sets the away timer value 285 (the number of clocks to wait) set in the away timer value register 275 in step S69. Decrease the value once (for a preset number of clocks). The measurement processing unit 131 that has decremented the away timer value 285 advances the process to step S81 in FIG.

  In step S81 in FIG. 12, the measurement processing unit 131 this time corresponds to the target 114 specified by the measurement processing execution control unit 206 so that the standby time is not continuously measured for the same address. The address B222 set in the latency value setting access destination address B272 of the separate register space 261 is read, and a read request is made to the target address B222.

  When the measurement processing unit 131 that has made the read request determines whether or not the data is acquired as a response to the read request in step S82, as in the case of the address A221, and determines that the data is not acquired. Then, the process proceeds to step S83, and it is determined whether a retry is acquired as a response to the read request. If it is determined that neither retry nor data has been acquired, that is, a response to the read request has not been acquired, the measurement processing unit 131 returns the process to step S82 and repeats the subsequent processes.

  If it is determined in step S83 that the retry process has been acquired, the measurement processing unit 131 uses the away timer value 285 (the number of clocks to wait) set in the away timer value register 275 as in the case of the address A221. To supply. The away timer value 285 is the away timer value that is decreased in step S69 of FIG. The away timer 255 counts the clock for the supplied away timer value 285 in step S84 of FIG. The measurement processing unit 131 stands by until the count end is notified from the away timer 285.

  When the count by the away timer 255 ends, the away timer 255 notifies the measurement processing unit 131 of the end of the count. When the count end is notified, the measurement processing unit 131 proceeds to step S85, and sets the latency value setting access destination address B272 of the target-specific register space 261 corresponding to the target 114 specified by the measurement processing execution control unit 206. A read request is again made to the set address B222.

  The measurement processing unit 131 that has made the read request again determines whether or not a retry has been acquired as a response to the read request in step S86 as in the case of the address A221, and has acquired the retry from the target 114. If not, the process proceeds to step S87, and it is determined whether or not the requested data is acquired as a response to the read request. If it is determined that neither retry nor data has been acquired, that is, a response to the read request has not been acquired, the measurement processing unit 131 returns the process to step S86 and repeats the subsequent processes.

  If it is determined in step S87 that the requested data has been acquired as a response to the read request, the measurement processing unit 131 sets the away timer value 285 (the number of clocks to wait) set in the away timer value register 275 in step S88. The value is decremented by one time (for a preset number of clocks), the process returns to step S62 in FIG. 11, and the subsequent processes are repeated.

  As described above, the measurement processing unit 131 repeats the processes in steps S62 to S69 in FIG. 11 and steps S81 to S88 in FIG. 12, and the away timer value 285 held in the away timer value register 275. By decreasing, the time to wait after detecting a retry is reduced.

  If the away timer value 285 is decreased by repeating the above processing, the waiting time becomes shorter than the time required for the target to prepare for data transfer. In that case, the measurement processing unit 131 detects a retry as a response to the read request made again after waiting. In such a case, the measurement processing unit 131 determines that the away timer value 285 in the previous process of the process when the retry is detected is the optimum waiting time (the time until the target 114 is ready for data transfer). Long and the shortest waiting time), and the value is stored as the latency value 283 in the latency value register 273 of the target corresponding register 261 corresponding to the target.

  That is, if it is determined in step S67 in FIG. 11 or step S86 in FIG. 12 that a retry has been acquired as a response to the read request, the measurement processing unit 131 proceeds to step S91 in FIG. 13 and sets the away timer value 285. Incremented by one time (by the number of clocks decremented at one time), and in step S92, the incremented away timer value 285 is set as the latency value 283 in the latency value register 273 for the target that has been processed. The measurement processing unit 131 that has set the latency value 283 advances the processing to step S93, asserts the completion flag 212 of the measurement processing execution control unit 206 of the CPU 141, and resets unnecessary register values in step S94. An end process is performed, and the measurement process ends.

  Note that the ideal standby time as the master device standby time is the time until the target 114 prepares for data transfer (the same length of time). However, in practice, it is difficult to set the master device standby time to a time that is exactly the same as the time until the target 114 prepares for data transfer. Although it is possible to set these lengths to the same length on the system clock, which is the synchronization unit of each unit, the actual measurement load and measurement processing time will be reduced if you actually make such fine adjustments. There is also a risk of increase. Accordingly, the standby time is controlled in units of a plurality of clocks as a practically possible processing unit according to the capability of the apparatus, and longer than the time until the target 114 prepares for data transfer on the control unit. In addition, it is desirable that the shortest waiting time is the optimum waiting time.

  If it is determined in step S63 in FIG. 11 that the requested data has been acquired as a response to the read request, that is, if the target 114 immediately responds to the first read request issued by the initiator 113, the target Although it is conceivable that 114 does not really need a waiting time, it is possible that old data held in the cache memory 122 of the target 114 has been transferred by mistake.

  Therefore, in such a case, the measurement processing unit 131 proceeds to step S70 in FIG. 11 and determines whether or not the data is acquired without waiting in the measurement process for the address B222. As described above, the measurement processing unit 131 suppresses data transfer due to old data remaining in the cache memory 122 by alternately repeating the measurement process based on the read request for the address A221 and the measurement process based on the read request for the address B222. The process is performed. Therefore, when the data is returned immediately in response to the first read request without waiting time as described above, the measurement processing unit 131 immediately performs both the read request for the address A221 and the read request for the address B222. Whether or not data is returned is confirmed, and if data is returned in a read request for any of the two addresses, it is determined that the target 114 does not really require a waiting time.

  That is, as described above, the measurement processing unit 131 determines whether or not the data is acquired without waiting in the measurement process for the address B222 in step S70, and the measurement process for the address B222 is not performed, or If it is determined that a retry has been detected in the measurement process for the address B222, the process proceeds to step S81 in FIG. 12, and the process proceeds to a measurement process by a read request for the address B222.

  If it is determined in step S70 in FIG. 11 that data has been acquired without waiting even in the measurement process for address B222, that is, it is determined that data has been acquired without waiting in the measurement process for both address A221 and address B222. The processing unit 131 advances the process to step S95 of FIG. 13, sets the value “0” as the latency value 283 in the latency value register 273 for the processed target, advances the process to step S93, and measures the CPU 141 The completion flag 212 possessed by the process execution control unit 206 is asserted, an end process is performed by resetting unnecessary register values in step S94, and the measurement process ends.

  The above processing is the same when a read request for address B is made. That is, if the measurement processing unit 131 determines in step S82 in FIG. 12 that data has been acquired for the first read request that has not passed the standby time, the process proceeds to step S89 in FIG. 12, and the measurement process for the address A221 is performed. If it is determined whether or not the data has been acquired without waiting and the measurement process for the address A221 is not performed, or if it is determined that the retry is detected in the measurement process for the address A221, the process is as shown in FIG. Proceeding to step S62, the process proceeds to measurement processing by a read request for address A221.

  If it is determined in step S89 in FIG. 12 that data has been acquired without waiting even in the measurement process for address A221, that is, it is determined that data has been acquired without waiting in the measurement process for both address A221 and address B222. The processing unit 131 advances the process to step S95 of FIG. 13, sets the value “0” as the latency value 283 in the latency value register 273 for the processed target, advances the process to step S93, and measures the CPU 141 The completion flag 212 possessed by the process execution control unit 206 is asserted, an end process is performed by resetting unnecessary register values in step S94, and the measurement process ends.

  Since the measurement processing unit 131 performs the measurement process as described above, the initiator 113 is unnecessary for the PCI bus 110 by using the set latency value 283 in the subsequent data transfer process (normal PCI data transfer process). Initiator 113 itself can perform data transfer without generating unnecessary traffic (transaction due to repeated unnecessary read requests) and without reducing the efficiency of data transfer. Therefore, each PCI device 111 connected to the PCI bus 110 can be used more effectively.

  Next, a specific example of the above measurement process will be described with reference to FIGS.

  As shown in FIG. 14, the initiator 113 given the right to use the PCI bus 11 first issues a read request 321-1 to the target 114 and supplies it to the target 114 via the PCI bus 110. (Arrow 322-1 and Arrow 324-1).

  FIG. 15 is a diagram illustrating an example of main signal state transitions of the PCI bus 110 in the read cycle. In FIG. 15, the signal with the symbol “#” added to the signal name on the left in the figure indicates negative logic. In the case of a read cycle, the initiator 113 asserts a request (REQ #) (not shown) and requests the right to use the bus from the arbiter. When the arbiter asserts a grant (GNT #) in response to this request, the initiator 113 can obtain the right to use the PCI bus 110 and can start a transaction.

  In this way, the initiator 113 that has acquired the right to use the PCI bus 110 first samples the frame (FRAME #) and the initiator ready (IRDY #) at the timing of the clock (CLK) 1, as shown in FIG. Since both are deasserted, it is determined that the PCI bus 110 is in an idle state (released state) and a new bus cycle can be started, and a frame (FRAME #) is asserted to start the bus cycle. To be notified.

  Further, the initiator 113 outputs an address (for example, the access destination address A221 of the target 114) to the address / data bus (AD [31:00]) at the timing of this clock (CLK) 1, and the bus command / byte enable Supply a bus command to (C / BE [3: 0] #). In this case, since it is a memory read request, the initiator 113 drives “L”, “H”, “H”, “L” to each line of the bus command / byte enable (C / BE [3: 0] #). To do.

  As described above, the transaction 323-1 occurs on the PCI bus 110 as shown in FIG. When a read request is supplied as indicated by an arrow 24-1, the target 15 performs a response process 25-1.

  In FIG. 15, all target devices (all PCI devices 111 connected to the PCI bus 110) have a frame (FRAME #) and an address / data bus (AD [31:00]) at the timing of the clock (CLK) 2. ), And bus command / byte enable (C / BE [3: 0] #), knows that a new bus cycle has started and is now in the address phase, and the address / data bus (AD [31: 00]) is decoded to determine whether or not the user is the access target.

  The target 114 determined to be the target to be accessed asserts device selection (DEVSEL #) at the timing of the clock (CLK) 2 and notifies that it responds to this bus cycle. At this time, the initiator 113 shifts the state of the address / data bus (AD [31:00]) and the bus command / byte enable (C / BE [3: 0] #) to the data phase.

  Then, the target 114 accesses the local memory 121 via the local bus 120 as shown by an arrow 326-1 in FIG. 14, and starts processing for acquiring data at the requested address and storing it in the cache memory 122. . At this time, the data (cache data) in the cache memory 122 is invalid data 327 that is not the requested data and is not ready for data transfer, so the target 114 sends the cache data to the initiator 113. Without supplying (without asserting target ready (TRDY #)), the retry process is returned (arrow 328-1 and arrow 329-1). When the initiator 113 detects the retry 330-1 supplied in this manner, the initiator 113 temporarily releases the PCI bus 110 so as not to occupy the PCI bus 110 unnecessarily.

  FIG. 16 is a diagram illustrating an example of a state transition in each signal when the target 114 returns the retry process.

  When returning the retry process, the target 114 asserts STOP (STOP #) while asserting device selection (DEVSEL #). Upon confirming the assertion of the stop (STOP #), the initiator 113 deasserts the frame (FRAME #), further deasserts a request (REQ #) (not shown), and temporarily releases the PCI bus 110. When the target 114 confirms that the frame (FRAME #) is deasserted, the target 114 deasserts the stop (STOP #) and the device selection (DEVSEL #). As a result, the initiator 113 also deasserts initiator ready (IRDY #).

  Returning to FIG. 14, when the retry processing is detected and the bus is released, the measurement processing unit 131 of the initiator 113 uses the away timer 255 to count the clock of the away timer value 285 (count processing 351), and the away timer 255. Wait until the end of the count is notified. That is, as shown in FIG. 14, the initiator 113 stands by without making a read request in a section (section 341) from time T1 to time T3.

  During this time, the target 114 continues to prepare for data transfer processing for the previous read request 321-1, and the data read from the local memory 121 is accumulated in the cache memory 122. At time T <b> 2, the storage process of the data requested in the read request 321-1 in the cache memory 122 is completed, and the data in the cache memory 122 becomes valid data 332.

  In the initiator 113, when the away timer 255 ends the count processing 351 and notifies the measurement processing unit 131 of the end of the count, the initiator 113 again secures the right to use the bus and sets the same address (for example, the address A221). A read request 321-2 is issued (that is, the same data is requested). This read request 321-2 is supplied to the target 114 via the PCI bus 110 (arrow 322-2 and arrow 324-2), as in the case of the read request 321-1. As a result, a transaction 323-2 occurs on the PCI bus 110.

  The target 114 performs a response process 325-2 for the read request 321-2 and accesses the cache memory 122 as indicated by an arrow 326-1. At this time, the valid data 332 is accumulated in the cache memory 122. Therefore, the valid data 332 is supplied to the initiator 113 as indicated by the arrow 333. The valid data 332 is supplied to the initiator 113 via the PCI bus 110 (transaction 334) as indicated by arrows 333 and 335. The initiator 113 acquires the valid data 336 supplied in this way.

  In the case of FIG. 15, when the target 114 is ready for data transfer in response to the read request, the target 114 asserts the target ready (TRDY #) as in the timing of the clock (CLK) 3, and the address / data bus (AD [ 31:00]), the data of the cache memory 121 is output. The initiator 113 can acquire the requested data by reading the value of this address / data bus (AD [31:00]). As described above, the initiator 113 and the target 114 that have completed the data transfer deassert each signal, end the bus cycle, and release the PCI bus 110.

  The above is one process for one address (process corresponding to steps S62 to S68 in FIG. 11). As described above, during normal data transfer, the initiator 113 counts (waits) the number of clocks corresponding to the away timer value 285 after detecting the retry, so that the transaction generated in the PCI bus 110 in this bus cycle is the transaction 323-1. 323-2 and 334, and the PCI bus 110 can suppress the generation of unnecessary traffic. Further, since the initiator 113 releases the PCI bus 110 in the section 341, other master devices can also perform PCI data transfer processing, and each PCI device 111 can use the PCI bus 110 more effectively. .

  However, as shown in FIG. 14, the initiator 113 has not made a read request until time T3 even though valid data 332 is prepared in the cache memory 122 of the target 114 at time T2. That is, the initiator 113 waits unnecessarily from time T2 to time T3. Therefore, with this away timer value 285, the waiting time is too long, and the data transfer efficiency of the initiator 113 may be reduced.

  Therefore, as shown in FIG. 17, the measurement processing unit 131 of the initiator 113 decrements the away timer value 285 by one time (a predetermined number of clocks) (step S69 in FIG. 11), and again described above. Perform the following process. That is, in the case of FIG. 17, the operations of the initiator 113 and the target 114 are basically the same as those described above with reference to FIGS. 14 to 16, but the length of the count process 361 by the away timer 255 is Compared to the case of the count process 351 of 14, the interval 361A corresponding to one subtraction amount of the predetermined away timer value 285 is shortened.

  That is, in the case of FIG. 17, the initiator 113 starts the count process 361 at time T1 and, when the count process 361 ends at time T4, issues a read request 321-2 as indicated by an arrow 362. Accordingly, the standby time after the retry detection of the initiator 113 is a section 371 from time T1 to time T4. Naturally, this section 371 is shorter than the section 341 in FIG. 14 by the section 361A.

  Note that the read request shown in FIG. 17 is a request for a different address (for example, address B222) of the same target as the address (for example, address A221) requested in the case of FIG. This access destination address is set in advance as described above.

  In the case of FIG. 17, the initiator 113 has made a read request by shortening the waiting time by one time compared with the process of FIG. 14, but even in this case, the initiator 113 still waits unnecessarily from time T2 to time T4. Will be. Therefore, the measurement processing unit 131 of the initiator 113 similarly repeats the processes shown in FIGS. 14 and 17 while subtracting the away timer value 285. At this time, the initiator 113 alternately performs processing on the two access destination addresses, that is, the address A221 and the address B222.

  Then, by repeating the above processing, the away timer value 285 becomes shorter, and when the count ends earlier than time T2, the initiator 113 responds to the read request after waiting as shown in FIG. A retry is also detected.

  In the case of FIG. 18, since the count process 381 shorter than the count process 351 of FIG. 14 by the section 381A ends at time T5 before time T2, the initiator 113 reads the read request 321-as indicated by the arrow 382 at this time T5. Issue 2 again. Accordingly, when the target 114 performs the response process 325-2, the valid data 331 is not yet prepared in the cache memory 122 (not ready for data transfer), so the arrows 328-2 and 329- Returns retry as in 2.

  As a result, the initiator 113 detects the retry process 330-2. As described above, when the time of the section 391 in which the initiator 113 waits becomes shorter than the time from the time T1 to the time T2, the initiator 113 detects the retry process even in the read request after waiting. If the away timer value 285 at this time is set to the latency value 283, an unnecessary transaction 323-2 occurs, so the measurement processing unit 131 of the initiator 113 has been decrementing the away timer value 285 until now. Increment the batch.

  That is, the initiator 113 makes a read request as shown in FIG. In the case of FIG. 19, after detecting the retry 333-1, the initiator 113 uses the away timer 255 to count the section 401A shorter than the count process 351 in FIG. 14 and longer than the section 401B than the count process 381 in FIG. Process 401 is executed. When the count process 401 ends at time T6, the initiator 113 issues a read request 321-2 as indicated by an arrow 402. That is, in this case, the initiator 113 waits for a section 411 from time T1 to time T6 and releases the PCI bus 110. That is, in this section 411, other PCI devices 111 can use the PCI bus 110.

  Therefore, the initiator 113 can make a read request in an optimal standby time after detecting a retry by making a read request in this way. Therefore, the detection processing unit 131 of the initiator 113 stores the one-time incremented away timer value 285 in the latency value register 273 as the latency value 283. Accordingly, the initiator 113 can perform processing using the latency value 283 in normal data transfer processing, and each PCI device 110 can effectively use the PCI bus 110.

  A normal memory read process will be described with reference to the flowchart of FIG.

  The device control unit 252 of the initiator 113 that has started the memory read process asserts the frame (FRAME #) as described above in step S101 and notifies the start of the bus cycle. In step S102, the address / data bus ( AD [31:00]) outputs an address, and supplies a read command by supplying a bus command to the bus command / byte enable (C / BE [3: 0] #). In step S103, the device control unit 252 that has supplied the read command sets the state of the address / data bus (AD [31:00]) and the bus command / byte enable (C / BE [3: 0] #) to the data phase. Prepare for data acquisition by migrating.

  In step S104, the device control unit 252 monitors a stop (STOP #) and determines whether a retry is detected. When it is determined that a stop (STOP #) is asserted and a retry is detected, the device control unit 252 advances the process to step S105, deasserts a frame (FRAME #) or a request (REQ #), and the PCI bus 110 The latency value 283 is read from the latency value register 273 of the target-specific register space 261 corresponding to the target 114 that has made the read request, and the time is counted by the away timer 255, and the process waits. When the away timer 255 outputs the count end, the device control unit 252 detects this, returns the process to step S10, repeats the subsequent processes, and issues the read command to the target 114 again.

  If it is determined in step S104 that a retry corresponding to the read command has not been detected, the device control unit 252 advances the process to step S107, the stop (STOP #) is deasserted, and the read By determining whether or not data is output from the target that has output the command to the address / data bus (AD [31:00]), it is determined whether or not data supply is ready.

  Determined that data is ready to be supplied (stop (STOP #) is deasserted and data is output to the address / data bus (AD [31:00]) from the target that output the read command) In this case, the device control unit 252 advances the process to step S108, latches the address / data bus (AD [31:00]), acquires the data, performs the termination process in step S109, and then performs the memory read. The process ends.

  If it is determined in step S107 that the response to the read command has not been acquired when the stop (STOP #) and the target ready (TRDY #) are deasserted, the device control unit 252 advances the process to step S110. Then, it is determined whether a target abort has been detected as a response to the read command. If it is determined that the target abort has not been acquired, the device control unit 252 returns the process to step S104 and repeats the subsequent processes.

  In step S110, when it is determined that stop (STOP #) is asserted and target ready (TRDY #) and device selection (DEVSEL #) are deasserted and target abort is detected, the device control unit 252 Then, the process proceeds to step S111, the abort process is executed, the error is notified to the device driver, and the memory read process is terminated.

  As described above, by performing the memory read process, the initiator 113 can repeat the read request using the optimum standby time as shown in FIG. By performing the request processing in this way, the initiator 113 reduces the number of unnecessary accesses in the data transfer processing, so that the PCI bus 110 can be used more effectively by reducing the PCI bus 110 traffic. it can.

  As described above, the initiator 113 and the target 114 are arbitrary PCI devices 111 connected to the PCI bus 110, and the PCI data transfer 112 by them is applied to data transfer between arbitrary PCI devices 111. Can do. That is, each master device performs the latency value setting process described above with reference to the flowchart of FIG. 10 for each target. That is, when all the latency value settings are completed, all the master devices connected to the PCI bus 110 hold the optimum latency values for all the targets, respectively. Therefore, all the PCI devices 111 connected to the PCI bus 110 can perform data transfer processing using an optimal standby time, and the PCI bus 110 can be used more effectively.

  The PCI device 111 may be any device that is connected to the PCI bus 110 and performs data transfer with other PCI devices 111 via the PCI bus 110, and includes, for example, a CPU 141. Therefore, the CPU 141 can be the initiator 113 or the target 114. Furthermore, the initiator 113 or the target 114 may be, for example, a PCI device (not shown) of another PCI bus connected to the PCI bus 110 via a PCI-PCI bridge or the like. For example, when the initiator 113 and the target 114 are connected to different PCI buses, the initiator 113 operates using a bridge connecting the two PCI buses as a target, and the bridge operates as a target for the initiator 113. To do. Conversely, the bridge behaves like an initiator with respect to the target 114, and the target 114 operates with the bridge as an initiator.

  In the above description, the bus system using the PCI bus 110 has been described. However, the system bus may be any other bus as long as the target returns a retry to the initiator as described above. . In such a bus, the initiator and the target may be connected to different types of buses connected to each other by a bridge.

  Furthermore, when the initiator 113 has a function as a plurality of devices (when it is a multi-function device), the initiator 113 may perform a latency value setting process for each function, or 1 for the same target. One latency value may be shared within one PCI device 111. Conversely, when the target 114 has functions as a plurality of devices, the initiator 113 may measure the latency value for each function, or measure only one function, and the result is obtained. Of course, the latency value may be applied to all the functions of the target.

  In the above description, the initiator 113 performs the measurement process using the memory read process and determines the optimum latency value 283. However, the present invention is not limited to this, and the memory write process, the I / O read process, Of course, other processing such as I / O write processing may be used. For example, the initiator 113 selects a process to be actually performed on the target 114 according to the function of the target 114, measures the waiting time when the process is repeated, and determines the latency value 283 as described above. You may do it.

  Further, as illustrated in the flowcharts of FIGS. 11 to 13, the initiator 113 has been described to alternately repeat the read request for two addresses (for example, the address A 221 and the address B 222). The number of may be one or plural. However, when there is one access destination address, the initiator 113 needs to wait until the data held in the cache memory 122 of the target 114 is securely cleared.

  In the above, it has been described that all the PCI devices 111 correspond to the above-described processing. However, the present invention is not limited to this, and only some master devices of the PCI devices 111 are as shown in FIG. The measurement processing unit 131 may be provided so that the latency value setting process described with reference to the flowchart of FIG. 10 and the measurement process described with reference to the flowcharts of FIGS. In that case, the CPU 141 identifies master devices that can set latency values in step S3 of FIG. 7 (reset processing), and in step S4, the latency is controlled so as to control only those identified master devices. Execute value setting control processing. In this case, as a method for determining whether or not the latency value can be set for each master device, the master specifying unit 203 includes, for example, the information in the configuration register of the master device capable of setting the latency value. There is a method of storing in advance. In step S3 of FIG. 7, the master specifying unit 203 refers to the information stored in the configuration register to determine whether or not the latency value can be set.

  In the above description, the latency value setting process is performed when the PCI bus 110 is reset. However, for example, the CPU 141 constantly monitors the state of the PCI bus 110 and performs unnecessary transactions (retry). Frequent transactions) may be detected, and in that case, the latency value of the PCI device may be reset.

  An example of the internal configuration of the CPU 141 in that case is shown in FIG. In addition, the same code | symbol is attached | subjected about the block of the structure similar to the case of FIG. That is, the CPU 141 includes a retry monitoring unit 421 that monitors a transaction due to a retry in addition to the configuration in the case of FIG.

  The retry monitoring unit 421 monitors each PCI data transfer performed via the PCI bus 110 via the host PCI bridge 151 and monitors a transaction due to the retry. When the number of retries exceeds a predetermined number, the retry monitoring unit 421 controls the measurement processing execution control unit 206 to perform measurement processing of the initiator and target that performed the PCI data transfer. Start execution control.

  Such retry monitoring processing will be described with reference to the flowchart of FIG.

  The retry monitoring processing unit 421 that has started the retry monitoring process monitors the PCI bus 110 in step S131 and monitors the PCI data transfer currently being performed. In step S132, the retry monitoring processing unit 421 determines whether or not a retry has been detected. If a retry is detected, the retry monitoring processing unit 421 proceeds to step S133, increments a counter that counts the retry, and counts the retry. .

  The retry monitoring unit 421 that has counted the retry advances the process to step S134. If it is determined in step S132 that no retry has been detected, the retry monitoring unit 421 skips step S133 and proceeds to step S134.

  In step S134, the retry monitoring unit 421 determines whether or not the PCI data transfer has been completed. If it is determined that the PCI data transfer has not ended, the retry monitoring unit 421 returns the process to step S131 and repeats the subsequent processes, thereby transferring the PCI data transfer. Monitoring is continued, and each time a retry is detected, the retry is counted. If it is determined in step S134 that the PCI data transfer has ended, the retry monitoring unit 421 proceeds to step S135, and the counted value (that is, the number of retries detected in the monitored PCI data transfer) is obtained. It is determined whether it is larger than a predetermined number.

  If it is determined that the count value is greater than the predetermined number, the retry monitoring unit 421 advances the process to step S136 to control the measurement process execution control unit 206, and the latency value as described with reference to the flowchart of FIG. The setting control process is executed, and the initiator 113 that has performed PCI data transfer in which many retries have been detected is started to execute the measurement process for the target 114. However, in this case, the measurement process execution control unit 206 may cause the initiator 113 to reset the latency value for at least the target 114 that is the communication partner of the monitored PCI data transfer, and the latency for all the targets. There is no need to execute the value setting process (FIG. 10).

  The retry monitoring unit 421 that has finished the process of step S136 advances the process to step S137. If the retry monitoring unit 421 determines in step S135 that the count value is not greater than the predetermined number, the process of step S136 is omitted, and the process proceeds to step S137.

  In step S137, the retry monitoring unit 421 resets the count value, proceeds to step S138, determines whether or not to end the retry monitoring process, and determines that the retry monitoring process is not ended, the process proceeds to step S131. Start monitoring for the next PCI data transfer. If it is determined in step S138 that the retry monitoring process is to be terminated, the retry monitoring unit 421 ends the retry monitoring process.

  As described above, the retry monitoring unit 421 counts the number of retries in each PCI data transfer during normal PCI data transfer, and if the number of retries is too large, the measurement process execution control unit 206 is controlled and the latency is set to the initiator 113. By causing the value to be reset, for example, even when the optimum latency value changes during a period in which normal PCI data transfer is performed, the initiator 113 immediately resets the latency value. PCI data transfer can always be performed with the optimum latency value.

  In the above description, when the PCI bus 110 is reset, the setting process of the latency value is performed by each master device. However, the present invention is not limited to this, and for example, a part or all of the master device is reset. Of course, the previously used latency value may be held in a non-volatile memory or the like, the setting process may be omitted after resetting, and the held latency value may be used. By doing so, each master device can omit the latency value setting process as described with reference to FIG. 10, thereby reducing the load of the reset process.

  In FIG. 4, the CPU 141 of the image processing apparatus 100 has been described as including the host PCI bridge 151. However, the present invention is not limited thereto. For example, as illustrated in FIG. 23, the CPU 141 and the host PCI bridge 151 are mutually connected. Of course, it may be configured as a separate body.

  23, the host PCI bus 431 is connected to the PCI bus 110 and the host bus 440, has the same function as the host PCI bridge 151 in FIG. 4, and performs the same processing. In the case of FIG. 23, the CPU 141 does not have the host PCI bridge 151 unlike the case of FIG. 4, but the communication with the PCI bus 110 side (PCI device 111) is performed via the host PCI bus 431. The processing of each part in the CPU 141 can be realized by processing substantially similar to the case of FIG.

  The CPU 141 is connected to the main memory 161 in addition to the host PCI bus 431 via the host bus 440. The host bus 440 is basically the same bus as the host bus 160 in FIG.

  Although not shown in FIG. 23, the arbiter and PCI controller of the PCI bus 110 are built in the host PCI bridge 431. However, these arbiters, PCI controllers, and the like may be further configured separately from the host PCI bridge 431.

  In the above description, the latency value setting process and the measurement process are described as being performed by each master device (by the control of the CPU 141). However, the CPU 141 may naturally perform these processes. In this case, the CPU 141 needs to monitor signals other than those described above, such as a request (REQ #) and a grant (GNT #), and identify the PCI device 111 that is performing the current bus cycle. As described above, the CPU 141 performs measurement processing and the like, so that the image processing apparatus 100 can effectively use the PCI bus 110 regardless of which PCI device 111 is connected.

  In the latency value setting process described with reference to the flowchart of FIG. 10 and the measurement process described with reference to the flowcharts of FIGS. 11 to 13, the measurement processing unit 131 of the initiator 113 first sets the away timer value 285 ( The initial away value 211 which is the maximum value of the latency value 283) is set as the initial value of the away timer value 285, and the processing related to measurement is repeated while decrementing a predetermined value therefrom. The initial away value 211, which is the initial value of the away timer value 285, is set to the minimum value of the away timer value 285 (latency value 283), and the initiator 113 repeats the processing related to the measurement from that state, Increments the specified amount, and a retry is detected after waiting It may be repeated until is no longer.

  In addition, the value by which the measurement processing unit 131 of the initiator 113 decrements (or increments) the away timer value 285 is variable (for example, the value changes every time the increment (or increment) is performed). Of course.

  In the above description, the image processing apparatus which is a video device has been described. However, any apparatus having a bus system as described above may be used. For example, an information processing apparatus such as a personal computer or a server may be used. Of course, it may be a mobile device such as a PDA or a mobile phone, or a home appliance such as a television receiver or a hard disk recorder.

  The series of processes described above can be executed by hardware or can be executed by software. In this case, for example, the master device reads out from the removable medium 174 via the drive 173, and the master device described with reference to the flowchart of FIG. 10 and the latency value setting process described with reference to the flowchart of FIG. A program and data necessary for executing the described measurement processing and the like may be supplied to each master device (part of the PCI device 111) via the PCI bus 110 and installed.

  At that time, when each master device acquires the program and data supplied in such a manner, the master device stores them in a storage unit such as a non-volatile memory in which they are built, and executes those programs as necessary. You may make it perform a process.

  By doing so, for example, an existing master device that does not support the above-described processing can also install necessary programs and data by the CPU 141 by connecting to the PCI bus 110. Therefore, the image processing apparatus 100 can effectively utilize the PCI bus 110 regardless of what PCI device 111 is connected.

  When the above-described series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  For example, as shown in FIG. 4, the recording medium is distributed to distribute the program to the user separately from the apparatus main body, and includes a magnetic disk (including a flexible disk) on which the program is recorded, an optical disk ( Removable media 174 composed of CD-ROM (compact disk-read only memory), DVD (digital versatile disk), magneto-optical disk (including MD (mini-disk) (registered trademark)), or semiconductor memory In addition to being configured, it is configured by a ROM 171 in which a program is recorded and a flash memory included in the storage unit 172, which are distributed to the user in a state of being pre-installed in the apparatus main body.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  Further, in this specification, the system represents the entire apparatus composed of a plurality of devices (apparatuses).

It is a block diagram explaining the conventional PCI bus system. It is a schematic diagram explaining the flow of the conventional PCI data transfer process. It is a figure explaining burst transfer. It is a block diagram which shows the structural example of the image processing apparatus 100 to which this invention is applied. FIG. 5 is a block diagram illustrating a detailed configuration example of a CPU in FIG. 4. FIG. 5 is a block diagram illustrating a detailed configuration example of the initiator in FIG. 4. It is a flowchart explaining the example of a reset process. It is a schematic diagram which shows the structural example of the memory space allocated to a target. It is a flowchart explaining the example of a latency value setting control process. It is a flowchart explaining the example of a latency value setting process. It is a flowchart explaining the example of a measurement process. It is a flowchart following FIG. 11 explaining the example of a measurement process. It is a flowchart following FIG. 12 explaining the example of a measurement process. It is a figure explaining the example of the flow of the measurement process with respect to one address. It is a figure explaining the example of the state transition of the signal in a read cycle. It is a figure explaining the example of the state transition of the signal in retry. It is a figure explaining the other example of the flow of the measurement process with respect to one address. It is a figure explaining the other example of the flow of the measurement process with respect to one address. It is a figure explaining the other example of the flow of the measurement process with respect to one address. It is a flowchart explaining the example of a memory read process. FIG. 5 is a block diagram illustrating another detailed configuration example of the CPU in FIG. 4. It is a flowchart explaining the example of a retry monitoring process. It is a block diagram which shows the other structural example of the image processing apparatus 100 to which this invention is applied.

Explanation of symbols

  100 image processing apparatus, 110 PCI bus, 111 PCI device, 112 PCI data transfer, 113 initiator, 114 target, 120 local bus, 121 local memory, 122 cache memory, 131 measurement processing unit, 141 CPU, 151 host PCI bridge, 152 latency Value setting control unit, 160 host bus, 161 main memory, 171 ROM, 172 storage unit, 173 drive, 174 removable media, 201 PCI configuration processing unit, 202 address setting unit, 203 master specifying unit, 204 initial away value setting unit , 205 Address set processing unit, 206 Measurement processing execution control unit, 211 Initial away value, 212 Completion flag, 213 Latency value setting action Destination address, 221 address A, 222 address B, 251 PCI interface processing unit, 252 device control unit, 253 initial away value set processing unit, 254 address set processing unit, 255 away timer, 261 target space, 271 latency value Setting access destination address register A, 272 Latency value setting access destination address register B, 273 Latency value register, 274 Initial away value register, 275 Away timer value register, 283 Latency value, 284 Initial away value, 285 Away timer value, 421 retry monitoring unit, 431 host PCI bridge, 440 host bus

Claims (21)

In an information processing apparatus having a system bus to which a plurality of devices are connected, wherein the plurality of devices transfer data to each other via the system bus.
The master device, which is a device that controls the data transfer and performs the data transfer, controls a waiting time until the command is reissued after issuing a command requesting the start of the data transfer. Measuring means for measuring the master device standby time set as the standby time;
An information processing apparatus comprising: latency value setting means for setting a value corresponding to the master device standby time measured by the measuring means as a latency value used by the master device in the data transfer. The measuring means controls the standby time, and as the master device standby time, a target that is a device to which the data transfer of the master device is a target until the preparation of the data transfer is completed after acquiring the command. The information processing apparatus according to claim 1, wherein time is measured. The measuring means controls the standby time, and the master device is longer than the time from when the target of the data transfer partner device of the master device acquires the command to prepare for the data transfer The information processing apparatus according to claim 1, wherein the waiting time is measured. The said measurement means controls the said waiting time, and measures the optimal waiting time which is the waiting time optimized so that it may become the shortest time as the said master device waiting time. Information processing device. The information processing apparatus according to claim 3, wherein the measuring unit controls the standby time and measures the optimum standby time on a control unit of the standby time. The information processing apparatus according to claim 5, wherein the control unit is a time unit based on a system clock of the information processing apparatus. The measuring means measures the master device standby time by causing the master device to repeatedly execute the data transfer while controlling the standby time to change the length of the standby time. The information processing apparatus according to claim 1. It further comprises a counting means for counting the clock,
The measuring means sets the waiting time as a period during which the clock counting process is being performed by the counting means, and changes the length of the waiting time by changing the number of the clocks to be counted by the counting means. The information processing apparatus according to claim 7, wherein the master device standby time is measured by causing the master device to repeatedly execute the data transfer. An initial waiting time setting means for setting an initial value of the waiting time in the data transfer repeatedly executed by the master device in the measurement processing by the measuring means;
8. The information according to claim 7, wherein the measurement unit causes the master device to execute an initial data transfer using the initial value set by the initial standby time setting unit in the measurement process. Processing equipment. In the data transfer repeatedly executed in the measurement process, the measurement unit sets the initial value set by the initial standby time setting unit as the maximum value of the standby time, and the master device repeats the data transfer. The information processing apparatus according to claim 9, wherein the waiting time is reset so that the waiting time is shortened. The measurement means resets the waiting time so that the waiting time is shortened, and the target corresponding to the data transfer issued to the master device is not ready for the data transfer. The information processing apparatus according to claim 10, wherein the master device is configured to repeatedly execute the data transfer until a retry that is a response indicating that is detected. 12. The measurement unit according to claim 11, wherein when the retry is detected, the repetition of the data transfer is stopped and the standby time in the previous data transfer is set as the master device standby time. Information processing device. The measuring means measures the master device standby time for each target with respect to one master device,
The said latency value setting means sets the value corresponding to the said master device waiting time for every said target measured by the said measurement means as said latency value for every said target. Information processing device. In the measurement process by the measurement unit, the measurement unit further includes an address setting unit that sets an access destination address accessed by the master device,
The measuring unit sets a waiting time until the master device reissues the command after issuing a command requesting the start of the data transfer to the access destination address set by the address setting unit. The information processing apparatus according to claim 1, wherein the information processing apparatus controls and measures the master device standby time. The address setting means sets two different access destination addresses corresponding to one target,
The measuring unit measures the master device standby time based on both of the two data transfers executed alternately by the master device with respect to the two access destination addresses set by the address setting unit. The information processing apparatus according to claim 14. Master device specifying means for specifying a master device for performing the data transfer for measuring the master device waiting time by the measuring means from among the plurality of devices connected to the system bus,
The information processing apparatus according to claim 1, wherein the measuring unit measures the master device standby time corresponding to the master device specified as the master device. The information processing apparatus according to claim 1, further comprising a measurement process execution control unit that controls execution of the measurement process by the measurement unit. The control means includes
A device selection means for selecting a device for performing the data transfer in which the measurement means measures the master device standby time;
The information processing apparatus according to claim 17, further comprising start control means for controlling start of the measurement process by the measurement means. In the data transfer performed by the plurality of devices through the system bus, a retry issued by the target to the master device and indicating a response indicating that the preparation for the data transfer is not completed is detected. Further comprising retry monitoring means for monitoring the number of retries,
The start control means starts the measurement processing by the measurement means when the retry monitoring means detects more retries than a predetermined number in one data transfer. The information processing apparatus according to claim 18. An information processing method of an information processing apparatus having a system bus to which a plurality of devices are connected, wherein the plurality of devices transfer data to each other via the system bus,
The master device, which is a device that controls the data transfer and performs the data transfer, controls a waiting time until the command is reissued after issuing a command requesting the start of the data transfer. A measurement step for measuring the master device standby time to be set as the standby time;
A latency value setting step of setting a value corresponding to the master device standby time measured by the measurement step as a latency value used by the master device in the data transfer. . In a program having a system bus to which a plurality of devices are connected, and causing the plurality of devices to perform data transfer with each other via the system bus.
The master device, which is a device that controls the data transfer and performs the data transfer, controls a waiting time until the command is reissued after issuing a command requesting the start of the data transfer. A measurement step for measuring the master device standby time to be set as the standby time;
A latency value setting step of setting a value corresponding to the master device standby time measured by the measurement step as a latency value used by the master device in the data transfer.

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