JP2005242414A - Information processor and information processing method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable each device in a system bus or a local bus to validly utilize the bus. <P>SOLUTION: A master-categorized transfer length investigating part 71 controls a data transfer processing part 75, and when a transfer length initial value 61 is supplied, the supplied transfer length initial value 61 is set in a predetermined register. When a memory read request is acquired by an initiator, the master-categorized transfer investigating part 71 controls a master discriminating part 72 to discriminate a master which has issued the request. The master-categorized transfer length investigating part 71 controls the data transfer processing part 75 to return retry to a memory read request, and reads data for a transfer length initial value from a local memory, and makes a cash memory 22 store the data. Then, when the memory read request is acquired after the completion of data storage, a transfer length measuring part 73 performs the transfer length measurement processing. This invention may be applied to, for example, a PCI bus system. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus and method, and a program, and in particular, each device of a system bus or a local bus uses the bus more effectively by, for example, reducing bus traffic by suppressing unnecessary data transfer. The present invention relates to an information processing apparatus and method that can be used effectively, and a program.

  Conventionally, in an information processing apparatus such as a personal computer, an ISA bus (Industry Standard Architecture bus), a PCI bus (Peripheral Components Interconnect bus), or the like is used as a system bus for connecting each device in the apparatus.

  The PCI bus is a bus standard established by PCI SIG (PCI Special Interest Group), and is rapidly spreading as a standard that replaces the ISA bus, which has long been an industry standard. In the first PCI standard, the bus width (the amount of data that can be sent in one transfer) is 32 bits, the operating frequency (number of transfers per second) is 33 MHz (megahertz), and the maximum data transfer rate is 133 MB / s ( Megabyte second). The latest PCI standard also defines a high-speed specification with a bus width of 64 bits, an operating frequency of 66 MHz, and a maximum data transfer rate of 533 MB / s.

  In a PCI bus system using the PCI bus, a plurality of PCI devices are connected to the PCI bus, and communicate with each other via the PCI bus to perform data transfer and the like. In the case of a PCI bus system, one of the PCI devices that performs data transfer (PCI data transfer) controls PCI data transfer. This PCI device is called a master. In PCI data transfer, a PCI device that is a master communication partner is referred to as a target. The target is controlled by the master to communicate with the master and transfer data.

  These PCI devices are controlled by a PCI bus controller, and the right to use the bus is assigned based on a request from the master. The master having the right to use the bus controls the target and performs data transfer and the like. For example, when the master wants to obtain data from the local memory connected to the target local bus, the master makes a read request to the target via the PCI bus and uses the address where the target data is recorded as the target. Notice.

  The target that has acquired the read request accesses the local memory according to the address acquired at the same time, and acquires the requested data. However, generally, the PCI bus, which is a system bus, and the local bus have different operating frequencies and transfer rates. Also, the response time of the local memory, which is the time from when the local memory is requested to read data by the target to when the data is output, is not always constant in some cases. Further, other local devices are connected to the local bus, and communication is performed between them. Therefore, the traffic of the local bus changes and the transfer speed is not always constant.

  Therefore, the target temporarily stores the data read from the local memory in the cache memory, etc., until all the requested data is stored in the cache memory and is ready to be immediately supplied to the master via the PCI bus. Waits for no data transfer via the PCI bus. Meanwhile, the target returns a retry to the master, causing the master to open the PCI bus to other devices.

  When the master detects a retry, it once releases the PCI bus to another device. In practice, however, the right to use the PCI bus is secured again in consideration of the efficiency of data transfer of the master. When the right to use the bus is secured, the master again supplies a memory read request to the target. When the target is ready for data transfer, it starts data transfer. If the data transfer is not ready, the target returns a retry to the master again.

  As described above, the PCI data transfer performed by each PCI device is a data transfer in which the real-time property (immediateness) that may cause a waiting time may occur in the data transfer process.

  By the way, for this waiting time, for example, there is a method (burst transfer) in which the master transfers data of a plurality of words by one access (one command issuance). By using such burst transfer, the master can reduce the bus traffic due to command issuance and increase the utilization efficiency of the PCI bus system. Note that a word is a memory read unit, and one word is, for example, 2 bytes.

  In addition, there is a method of reducing transactions due to retries by using a target prepared in advance with information on the standby time of the master (see, for example, Patent Document 1). In this case, the predetermined register of the target holds in advance latency information, that is, information on the time from when the request is received until the target is ready for data transfer, in response to an access request from the master, Supply that information to the master. When the master obtains the information, when requesting PCI data transfer to the target, the master waits for the time specified by the latency information supplied from the target after making a retry, and then makes a transfer request. That is, in this case, the initiator does not repeat the request until the target is ready.

JP-A-10-293744

  However, for example, in the case of a bus system in a video device or a broadcast station server, it is necessary to frequently transfer a large amount of data such as video data and audio data. In such a video device, for example, video data captured from the outside is recorded on a recording medium, video data recorded on the recording medium is reproduced, displayed on a monitor, or output to the outside. Is mainly performed. Therefore, each data transfer in the bus system often requires immediacy, and when the bus traffic increases, the waiting time becomes too long, and there is a possibility that the recording process, the reproduction process, etc. will fail. Therefore, in the case of such a bus system in a video device, a broadcast station server, etc., real-time performance is required for data transfer.

  However, when a general-purpose PCI bus such as that described above is used as a system bus for such video equipment or broadcasting station servers, the manufacturing cost can be reduced. (Immediateness) is not guaranteed. Therefore, it is important to reduce traffic as much as possible, to effectively use the bus, and to reduce waiting time and the like.

  Therefore, as in Patent Document 1 described above, a method for adjusting the latency time of the master and reducing the retry processing has been proposed. However, traffic on the local bus to which the target local memory to which the master requests data is connected is proposed. Is not considered.

  In the conventional PCI bus system, for example, as described above, when the master reads data from the local memory connected to the target via the local bus, the target stores the data requested by the master in the cache memory. At this time, as described above, since the master may request data using burst transfer, the target stores the amount of data required by the master in the cache memory so that unnecessary processing does not occur. Then supply to the master.

  However, the amount of data (number of words) requested by the master at a time differs depending on each master. Since the target does not know which master continuously reads how much data amount, a large amount of data (for example, 23 words) is read from the local memory and accumulated in the cache so that unnecessary processing does not occur.

  In some cases, the master may continuously read multiple words of data (burst transfer) while issuing a single word read command (single read), and the target is always in large quantities so that unnecessary processing does not occur. Must be read from local memory and stored in the cache.

  Thus, for example, some masters can only perform a single read, but a target that has requested data from that master reads a large amount of data including unnecessary data from the local memory, accumulates it in the cache, and unnecessarily local There was a risk of increasing bus traffic. Normally, local devices other than the local memory are also connected to the local bus, and these local devices also transfer data to each other and use the local bus.

  Even in such a local bus, as described above, for example, in video equipment and broadcast station servers, data transfer that requires real-time performance (immediateness) is often performed. There is a problem that the target that has acquired the read request from the master occupies the local bus unnecessarily, so that the recording process and the reproduction process may fail.

  In addition, by accumulating unnecessary data in the cache memory, there is a problem that the time for the target to prepare for data transfer becomes unnecessarily long and the standby time of the master increases.

  On the other hand, there is also a method of reducing the amount of data that the target reads from the local memory at one time, and reducing the local bus occupancy rate and the time required for preparation of data transfer. When a data amount larger than the data amount prepared by the target is continuously read, a disconnection occurs, and the data transfer processing time becomes unnecessarily long, which may reduce the transfer efficiency.

  The present invention has been made in view of such a situation, and enables each device of the system bus or the local bus to more effectively utilize the bus.

  The first information processing apparatus according to the present invention has a first data amount that is a predetermined data amount predetermined by a predetermined memory device based on a request of a master device that controls data transfer and performs data transfer. After acquiring the amount of data and holding it in the built-in cache memory, a transfer means for executing a first transfer process for transferring the data to the master device via the system bus, and a first executed by the transfer means In the transfer process, the master device measures the second data amount that is the data amount acquired by one access, and reads from the memory device based on the second data amount measured by the measuring device. A setting unit that sets a third data amount that is a data amount; and a storage unit that stores the third data amount set by the setting unit. After the third data amount is stored by the storage unit, the unit acquires the data corresponding to the third data amount stored by the storage unit from the memory device based on the request of the master device, and incorporates the data. After the data is held in the cache memory, a second transfer process is executed in which the data is transferred to the master device via the system bus.

  The first data amount may be larger than the maximum second data amount measured by the measuring unit.

  The setting means may set the third data amount so that the third data amount approximates the second data amount.

  A first control unit for controlling the master device to issue a memory read request; and a first transfer process by controlling a transfer unit for a memory read request controlled and issued by the first control unit. , The second data amount is measured by controlling the measuring means, the third data amount is set by controlling the setting means, and the third data amount is stored by controlling the storage means. The control means may be further provided.

  The first control unit controls the master device to issue a memory read request a plurality of times, and the second control unit controls the transfer unit to control and issue a plurality of issued by the first control unit The first transfer process is executed for each of the memory read requests, the measurement unit is controlled, and the second data amount is measured for each of the first transfer processes executed a plurality of times by the transfer unit, The setting means is controlled to set a third data amount based on a plurality of second data amounts obtained by a plurality of measurements by the measuring means, and the storage means is controlled and set by the setting means. The third data amount can be stored.

  The setting unit may set an average value, a maximum value, or a minimum value of a plurality of second data amounts obtained by a plurality of measurements by the measuring unit as a third data amount.

  The first control unit controls each of the plurality of master devices and issues a memory read request for each master device, and the second control unit controls the transfer unit, the measurement unit, the setting unit, and the storage unit. Thus, the third data amount can be set and stored for each master device.

  The first control unit controls each of the master devices having a plurality of functions, and issues a memory read request for each function of the master device. The second control unit includes a transfer unit, a measurement unit, a setting unit, In addition, the third data amount can be set and stored for each function of the master device by controlling the storage means.

  Target device specifying means for specifying a target device to be controlled so that the second control means sets and stores the third data amount from among a plurality of target devices that are devices to which the master device is to transfer data. Can be further provided.

  Master device determination means for determining a master device that has issued a request in the first transfer process or the second transfer process executed by the transfer means may be further provided.

  Disconnection monitoring means for monitoring occurrence of disconnection processing in the second transfer processing executed by the transfer means can be further provided.

  According to a first information processing method of the present invention, a first data amount that is a predetermined data amount predetermined from a predetermined memory device based on a request of a master device that is a device that controls data transfer and performs data transfer. A first transfer step for executing a first transfer process for acquiring data of an amount of data and holding the data in a built-in cache memory and then transferring the data to the master device via the system bus; and a first transfer step In the first transfer process executed by the process, the measurement step for measuring the second data amount, which is the data amount acquired by the master device by one access, and the second measured by the process of the measurement step Based on the data amount, a setting step for setting a third data amount, which is a data amount read from the memory device, and a process of the setting step A storage control step for controlling to store the determined third data amount, and a memory based on a request from the master device after the third data amount is stored by being controlled by the processing of the storage control step. A third amount of data controlled and stored by the process of the storage control step is acquired from the device, held in the built-in cache memory, and then transferred to the master device via the system bus. And a second transfer step for executing the second transfer process.

  The first program of the present invention controls a first data amount that is a predetermined data amount predetermined by a predetermined memory device based on a request from a master device that is a device that controls data transfer and performs data transfer. A first transfer step for executing a first transfer process for transferring the data to the master device via the system bus after the data is acquired and held in the built-in cache memory, and a process of the first transfer step In the first transfer processing executed by the above, a measurement step for measuring a second data amount that is a data amount acquired by the master device by one access, and a second data amount measured by the processing of the measurement step On the basis of the setting step for setting the third data amount, which is the amount of data read from the memory device, and the setting step process. A storage control step for controlling the stored third data amount to be stored, and the memory device based on the request of the master device after the third data amount is stored by being controlled by the processing of the storage control step. Thus, after acquiring the data for the third data amount controlled and stored by the processing of the storage control step and holding it in the built-in cache memory, the data is transferred to the master device via the system bus. And causing the computer to execute the second transfer step of executing the transfer process.

  The second information processing apparatus of the present invention is a device that controls data transfer and transfers data in data transfer between devices connected to two system buses and connected to different system buses of the two system buses. Based on the request from the master device, the first data amount, which is a predetermined data amount, is acquired from the target device that is the data transfer partner of the master device, and stored in the built-in cache memory Thereafter, in the relay unit that executes the first relay process for transferring data to the master device and the first relay process that is executed by the relay unit, the amount of data that the master device acquires from the cache memory by one access Measuring means for measuring a certain second amount of data, and second data measured by the measuring means And setting means for setting a third data amount, which is a data amount read from the target device, and storage means for storing the third data amount set by the setting means, and the relay means includes storage means After the third data amount is stored by the above, based on the request of the master device, the third data amount stored by the storage unit is obtained from the target device and stored in the built-in cache memory. Then, a second relay process for transferring data to the master device via the system bus is executed.

  The second information processing method of the present invention performs processing for connecting two system buses, and controls data transfer in data transfer between devices connected to different system buses of the two system buses. Based on a request from a master device that is a device that performs data transfer, a first data amount that is a predetermined data amount is acquired from a target device that is a data transfer partner of the master device, and the cache memory is controlled. In the relay step for executing the first relay process for transferring data to the master device and the first relay process executed by the process of the relay step, the master device caches by one access. A measurement step for measuring a second data amount, which is the amount of data acquired from the memory, and a measurement step A setting step for setting a third data amount, which is a data amount read from the target device, on the basis of the second data amount controlled and measured by the processing of the second step, and a third set by the processing of the setting step Storage control step for controlling to store the amount of data, and after the third data amount is stored by being controlled by the processing of the storage control step, the storage control is performed by the target device based on the request of the master device. The second relay that acquires the data for the third amount of data controlled and stored by the processing of the step, controls and holds the cache memory, and then transfers the data to the master device via the system bus And a second relay step for executing the process.

  The second program of the present invention performs processing for connecting two system buses, and controls data transfer and transfers data in data transfer between devices connected to different system buses of the two system buses. Based on the request of the master device, which is a device, obtains data of a first data amount, which is a predetermined data amount, from a target device that is a data transfer partner of the master device, and controls the cache memory In the relay step for executing the first relay process for transferring the data to the master device after being held, and in the first relay process executed by the process of the relay step, the master device is accessed from the cache memory by one access. A measurement step for measuring a second data amount, which is a data amount to be acquired, and a measurement step A setting step for setting a third data amount, which is a data amount read from the target device, on the basis of the second data amount controlled and measured by the processing of the step, and a third set by the processing of the setting step A storage control step for controlling the amount of data to be stored, and a storage control step from the target device based on a request of the master device after the third data amount is stored by being controlled by the processing of the storage control step. The second relay process for acquiring the data for the third data amount controlled and stored by the above process, transferring the data to the master device via the system bus after controlling and holding the cache memory And causing the computer to execute a second relay step for executing.

  In the first information processing apparatus and method and the first program of the present invention, the predetermined information is predetermined from a predetermined memory device based on a request from a master device that controls data transfer and performs data transfer. After a first data amount of data, which is a predetermined data amount, is acquired and held in a built-in cache memory, a first transfer process is executed in which the data is transferred to the master device via the system bus, In the first transfer process, the second data amount that is the data amount acquired by the master device by one access is measured, and the data amount is read from the memory device based on the measured second data amount. After the third data amount is set, the set third data amount is stored, and after the third data amount is stored, the master device A second transfer process in which data corresponding to the third data amount is acquired from the memory device based on the request, held in the built-in cache memory, and then transferred to the master device via the system bus Is executed.

  In the second information processing apparatus and method and the second program of the present invention, data transfer is performed in data transfer between devices connected to two system buses and connected to different system buses of the two system buses. Based on a request from a master device that is a device that performs data transfer by controlling the data, a first data amount that is a predetermined data amount is acquired from a target device that is a data transfer partner of the master device. The first relay process in which data is transferred to the master device after being held in the built-in cache memory is executed, and in the first relay process, the data acquired by the master device from the cache memory by one access A second data amount that is a quantity is measured, and based on the measured second data amount The third data amount that is the amount of data read from the target device is set, the set third data amount is stored, and after the third data amount is stored, based on the request of the master device, After the third data amount stored from the target device is acquired and held in the built-in cache memory, the second relay process is executed in which the data is transferred to the master device via the system bus. Is done.

  According to the present invention, data transfer can be controlled. In particular, for example, each device of the system bus or the local bus can use the bus more effectively by reducing bus traffic by suppressing unnecessary data transfer.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

  In the present invention, a system bus (for example, PCI bus 10 in FIG. 1) to which a plurality of devices (for example, PCI devices 11-1 to 11-N in FIG. 1) are connected is provided. An information processing apparatus (for example, the image processing apparatus 1 of FIG. 1) that performs data transfer (for example, the PCI data transfer 12 of FIG. 1) to each other via the system bus is provided. In this information processing apparatus, based on a request from a master device (for example, the initiator 13 in FIG. 1) that controls data transfer and performs data transfer, a predetermined memory device (for example, the local memory 21 in FIG. 1). The data of the first data amount (for example, the transfer length initial value 61 in FIG. 2) which is a predetermined predetermined data amount is acquired and held in the built-in cache memory (for example, the cache memory 22 in FIG. 1). After that, transfer means (for example, the data transfer processing unit 75 in FIG. 3) for executing a first transfer process for transferring data (for example, the transfer data 91 in FIG. 3) to the master device via the system bus; In the first transfer process executed by the transfer means, a second data amount (for example, FIG. Measurement unit (for example, the transfer length measurement unit 73 in FIG. 3 that executes the process of step S63 in FIG. 10) and the second measured by the measurement unit. FIG. 10 is a diagram for executing a process of step S67 in FIG. 10 for setting a third data amount (for example, the optimum transfer length 82 in FIG. 3) that is a data amount read from the memory device based on the data amount in FIG. 3 and a storage means (for example, the cache memory 22 in FIG. 1) for storing the third data amount set by the setting means. After the data amount is stored, the third data amount stored by the storage means is acquired from the memory device based on the request of the master device, and the built-in cache memory is acquired. After holding the Li, data, performs a second transfer process of transferring to the master device via the system bus (e.g., data transfer process of FIG. 14).

  First control means for controlling the master device to issue a memory read request (for example, master-specific transfer length investigation control unit 56 in FIG. 2), and memory read request issued under the control of the first control means In contrast, the transfer unit is controlled to execute the first transfer process, the measurement unit is controlled to measure the second data amount, the setting unit is controlled to set the third data amount, and the storage is performed. It is possible to further include second control means (for example, master-specific transfer length checking unit 71 in FIG. 3) for controlling the means and storing the third data amount.

  The first control unit controls the master device to issue a memory read request a plurality of times (for example, step S22 in FIG. 7), and the second control unit controls the transfer unit to perform the first control. The first transfer process is executed for each of the plurality of memory read requests that are controlled and issued by the means, the measuring means is controlled, and each of the first transfer processes executed a plurality of times by the transfer means The second data amount is measured, the setting unit is controlled, the third data amount is set based on a plurality of second data amounts obtained by a plurality of measurements by the measuring unit, and the storage unit is controlled. Thus, the third data amount set by the setting means can be stored.

  The setting unit sets an average value, a maximum value, or a minimum value of a plurality of second data amounts obtained by a plurality of measurements by the measuring unit as a third data amount (for example, step S67 in FIG. 10). )

  Control is performed so that the second control means sets and stores a third data amount from among a plurality of target devices (for example, the target 14 in FIG. 1) which are devices to which the master device is to transfer data. A target device specifying unit (for example, the survey target target specifying unit 53 in FIG. 2) for specifying the target device may be further provided.

  A master device determining unit (for example, master determining unit 75 in FIG. 3) that determines a master device that has issued a request in the first transfer process or the second transfer process executed by the transfer unit is further provided. Can do.

  A disconnect monitoring unit (for example, the disconnect monitoring unit 401 in FIG. 21) for monitoring the occurrence of a disconnect process in the second transfer process executed by the transfer unit may be further provided.

  In the present invention, a system bus (for example, PCI bus 10 in FIG. 1) to which a plurality of devices (for example, PCI devices 11-1 to 11-N in FIG. 1) are connected is provided. An information processing method of an information processing apparatus (for example, the image processing apparatus 1 of FIG. 1) that transfers data to each other (for example, the PCI data transfer 12 of FIG. 1) via a system bus is provided. In this information processing method, based on a request from a master device (for example, the initiator 13 in FIG. 1) that controls data transfer and performs data transfer, a predetermined memory device (for example, the local memory 21 in FIG. 1). ) Is obtained from the first data amount (for example, the transfer length initial value 61 in FIG. 2) which is a predetermined data amount determined in advance, and stored in the built-in cache memory (for example, the cache memory 22 in FIG. 1). After the holding, a first transfer step (for example, step S62 and step of FIG. 10) that executes a first transfer process of transferring data (for example, transfer data 91 of FIG. 3) to the master device via the system bus. S65) and the first transfer process executed by the process of the first transfer step, the master device is accessed once A measurement step (for example, step S63 in FIG. 10) for measuring a second data amount (for example, a transfer length measured by the transfer length measurement unit 73 in FIG. 3), which is the amount of data to be obtained, and a measurement step process. A setting step (for example, step S67 in FIG. 10) for setting a third data amount (for example, the optimum transfer length 82 in FIG. 3), which is the amount of data read from the memory device, based on the second data amount A storage control step (for example, step S69 in FIG. 10) for controlling to store the third data amount set by the setting step process, and a third data amount controlled by the storage control step process. After being stored, the third stored in the memory device is controlled and stored by the memory control step based on the request of the master device. A second transfer step (for example, FIG. 14) of acquiring a data amount and storing the data in a built-in cache memory and then executing a second transfer process for transferring the data to the master device via the system bus. Data transfer processing).

  In the present invention, a process having a system bus to which a plurality of devices are connected, and the plurality of devices transferring data to each other via the system bus is performed on a computer (for example, the image processing apparatus 100 in FIG. 4). A program to be performed is provided. This program is preliminarily stored in a predetermined memory device (for example, the local memory 21 in FIG. 1) based on a request from a master device (for example, the initiator 13 in FIG. 1) that controls data transfer and performs data transfer. After acquiring a first data amount (for example, transfer length initial value 61 in FIG. 2) that is a predetermined predetermined data amount and holding it in a built-in cache memory (for example, cache memory 22 in FIG. 1) A first transfer step (for example, step S62 and step S65 in FIG. 10) for executing a first transfer process for transferring data (for example, transfer data 91 in FIG. 3) to the master device via the system bus; In the first transfer process executed by the process of the first transfer step, the master device obtains the data acquired by one access. A measurement step (for example, step S63 in FIG. 10) for measuring a second data amount (for example, a transfer length measured by the transfer length measurement unit 73 in FIG. 3), and a measurement step process. A setting step (for example, step S67 in FIG. 10) for setting a third data amount (for example, the optimum transfer length 82 in FIG. 3) that is a data amount to be read from the memory device based on the second data amount; A storage control step (for example, step S69 in FIG. 10) for controlling to store the third data amount set by the setting step processing, and the third data amount stored by being controlled by the storage control step processing. Thereafter, based on the request of the master device, the memory device controls the third data amount stored by being controlled by the processing of the storage control step. A second transfer step (for example, the data transfer process of FIG. 14) for executing a second transfer process for acquiring the data and holding it in the built-in cache memory and then transferring the data to the master device via the system bus Including.

  In the present invention, a plurality of system buses (for example, FIG. 1) to which a plurality of devices (for example, PCI devices 11-1 to 11-N and PCI devices 211-1 to 211-K in FIG. 16) are connected. An information processing apparatus (for example, the image processing apparatus 200 in FIG. 16) having the PCI bus 10 and the PCI bus 210) in which the plurality of devices transfer data to each other via the system bus is provided. In this information processing apparatus, in data transfer between devices connected to two system buses and connected to different system buses of the two system buses, a master device (device that controls data transfer and performs data transfer) For example, based on the request of the initiator 13) in FIG. 16, the first data amount that is a predetermined data amount predetermined by the target device (for example, the target 214 in FIG. 16) that is the data transfer partner of the master device. After the data of (for example, the transfer length initial value 61 in FIG. 2) is acquired and held in the built-in cache memory (for example, the cache memory 202 in FIG. 16), the first relay processing for transferring the data to the master device is performed. The relay means to be executed (for example, the PCI-PCI bridge 201 in FIG. 16) and the relay means In the first relay process, the second data amount (for example, the transfer length measured by the transfer length measuring unit 73 in FIG. 17) that is the amount of data that the master device acquires from the cache memory by one access is measured. This is the amount of data read from the target device based on the measurement means (for example, the transfer length measurement unit 73 in FIG. 3 that executes the processing of step S63 in FIG. 10) and the second data amount measured by the measurement means. Setting means for setting a third data amount (for example, the optimum transfer length 82 in FIG. 17) (for example, the transfer length measuring unit 73 in FIG. 17 for executing the processing in step S67 in FIG. 10) and the setting means. Storage means (for example, optimum transfer length 82 in FIG. 17) for storing the third data amount, and the relay means after the third data amount is stored by the storage means Then, based on the request of the master device, the data corresponding to the third amount of data stored in the storage means is obtained from the target device, held in the built-in cache memory, and then the data is transferred to the master via the system bus. A second relay process to be transferred to the device is executed (for example, the data transfer process in FIG. 14).

  In the present invention, a plurality of system buses (for example, FIG. 1) to which a plurality of devices (for example, PCI devices 11-1 to 11-N and PCI devices 211-1 to 211-K in FIG. 16) are connected. There is provided an information processing method of an information processing apparatus (for example, the image processing apparatus 200 in FIG. 16) having the PCI bus 10 and the PCI bus 210), in which the plurality of devices transfer data to each other via the system bus. . In this information processing method, a device that performs processing for connecting two system buses and performs data transfer by controlling data transfer in data transfer between devices connected to different system buses of the two system buses. Based on a request of a certain master device (for example, the initiator 13 in FIG. 16), a predetermined data amount that is predetermined by a target device (for example, the target 13 in FIG. 16) that is a partner of data transfer of the master device. 1 is acquired (for example, the transfer length initial value 61 in FIG. 2), the cache memory (for example, the cache memory 202 in FIG. 16) is controlled and held, and then the data is transferred to the master device. A relay step (for example, step S126 in FIG. 20) for executing the first relay process; In the first relay process executed by the step process, the second data amount (for example, measured by the transfer length measuring unit 73 in FIG. 16) is the data amount that the master device acquires from the cache memory by one access. And a third data amount that is read from the target device based on a measurement step (for example, step S63 in FIG. 10) and a second data amount that is controlled and measured by the processing of the measurement step. And a storage control step for controlling to store the third data amount set by the processing of the setting step (for example, the optimum transfer length 82 of FIG. 17) (for example, FIG. 10). Step S69) and after the third data amount is stored under the control of the storage control step, the master device On the basis of the request from the target device, the data corresponding to the third data amount controlled and stored by the processing of the storage control step is acquired from the target device, and the cache memory is controlled and held, and then the data is transferred to the system bus. And a second relay step (for example, the data transfer process of FIG. 14) for executing a second relay process of transferring to the master device via

  In the present invention, a process including a plurality of system buses to which a plurality of devices are connected, and the plurality of devices transferring data to each other via the system bus is performed by a computer (for example, the image processing apparatus 100 in FIG. 4). ) Is provided. This program performs processing for connecting two system buses, and in a data transfer between devices connected to different system buses of the two system buses, a master device which is a device that controls data transfer and performs data transfer First data having a predetermined data amount determined in advance by a target device (for example, the target 13 in FIG. 16) that is a partner of data transfer of the master device based on a request from the master device (for example, the initiator 13 in FIG. 16). A first amount of data (for example, transfer length initial value 61 in FIG. 2) is acquired, and the cache memory (for example, cache memory 202 in FIG. 16) is controlled and held, and then transferred to the master device. A relay step (for example, step S126 in FIG. 20) for executing the relay process, and a relay step In the first relay process executed by the process, a second data amount (for example, transfer measured by the transfer length measuring unit 73 in FIG. 16) that is the amount of data that the master device acquires from the cache memory by one access. 3rd data which is the data amount read from the target device based on the measurement step (for example, step S63 in FIG. 10) and the second data amount measured and measured by the processing of the measurement step. A setting step for setting the amount, and a storage control step for controlling to store the third data amount (for example, the optimum transfer length 82 in FIG. 17) set by the processing in the setting step (for example, step S69 in FIG. 10). ), And after the third data amount is stored under the control of the storage control step, Therefore, after acquiring the data for the third data amount controlled and stored by the processing of the storage control step from the target device and controlling and holding the cache memory, the data is transferred via the system bus. And a second relay step (for example, the data transfer process of FIG. 14) for executing a second relay process for transferring to the master device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a main configuration example of an image processing apparatus to which the present invention is applied.

  An image processing apparatus 1 shown in FIG. 1 is a video device such as a video data recording / reproducing apparatus, for example, and a PCI bus (Peripheral Components Interconnect bus) 10 is applied as a system bus.

  For example, the PCI bus 10 has a bus width (the amount of data that can be sent in one transfer) of 32 bits, an operating frequency (number of transfers per second) of 33 MHz (megahertz), and a maximum data transfer rate of 133 MB / s (megabyte par) This is the second bus.

  The PCI device 11-1 to PCI device 11 -N are connected to the PCI bus 10. Hereinafter, the PCI devices 11-1 to 11-N are referred to as PCI devices 11 when it is not necessary to distinguish between the PCI devices 11-1 to 11-N. In FIG. 1, the PCI device 11 is connected to the PCI bus 10 by a double-headed arrow, but is actually connected by a plurality of signal lines, a power source, a ground, and the like. As the PCI device 11, various devices that can mutually transfer data via the PCI bus 10 are applied. For example, a SCSI (Small Computer System Interface) interface, an IDE (Integrated Drive Electronics) interface, a mass storage controller such as a flexible disk drive, a network controller such as an Ethernet (registered trademark) interface or an ATM (Asynchronous Transfer Mode) interface, Multimedia controllers such as video controllers and audio controllers, memory controllers such as SDRAM (Synchronous Dynamic Random Access Memory) and flash memory, ISA (Industry Standard Architecture) bridge, PCI-PCI bridge, PCMCIA (Personal Computer Memory Card International Association) bridge Bridges, input interfaces such as keyboard and mouse, processors such as CPU, IEEE (Institute of Electrical and Electronic Engineers) 1394 and USB (Universal Serial Bus) Controller or the like is included in the serial bus and the like. Of course, other devices may be connected to the PCI bus 10 as the PCI device 11.

  Hereinafter, a PCI device that controls data transfer (PCI data transfer) performed via the PCI bus 10 is referred to as a master, and a PCI device that is a communication partner of the master is referred to as a target. The PCI device 11 that can operate as a master is called a master device, and a device that operates only as a target is called a target device.

  In one PCI data transfer, there is only one PCI device 11 operating as a master, and the master at this time is called an initiator. That is, in one PCI data transfer, the initiator controls data transfer as a master, communicates with other targets, and exchanges data. Note that the master device may operate as a target and perform PCI data transfer with other master devices. The initiator in the PCI data transfer at this time is another master device.

  In FIG. 1, an initiator 13 is one of PCI devices 11, and accesses a target 14 that is also one of PCI devices to perform PCI data transfer 12. That is, the initiator 13 controls the PCI data transfer 12 to the target 14. In the following, the PCI data transfer 12 by the initiator 13 and the target 14 will be described, but the PCI data transfer 12 does not indicate data transfer between specific PCI devices, but all data transfer in the PCI bus system of the PCI bus 110. Can be adapted to. That is, the initiator 13 indicates an arbitrary master device included in the PCI device 11, and the target 14 indicates all PCI devices 11 that perform PCI data transfer with the initiator 13.

  The target 14 is connected to the PCI bus 10 and is connected to the local memory 21 via the local bus 20, and is a device that controls data input / output of the local memory 21. The target 14 has a cache memory 22 inside. The cache memory 22 is used for data transfer or the like, for example, to absorb a difference in data transfer speed between the PCI bus 10 and the local bus 20. For example, when the initiator 13 requests the target 14 to read data in the local memory 21 by the PCI data transfer 12, the target 14 first accesses the local memory 21 via the local bus 20 and is requested. Data is read and stored in the cache memory 22. As will be described later, the target 14 measures in advance information on the amount of data (number of words) acquired by the initiator 13 by one access, and the initiator 13 acquires by one access based on the information. Data of the amount of data (number of words) is acquired from the local memory 21 and stored in the cache memory 22.

  Hereinafter, the data amount (number of words) acquired by the initiator 13 by one access is referred to as a transfer length for the initiator 13. Note that a word is a memory read unit, and one word is, for example, 2 bytes. The target 14 holds the data to be transferred (transfer data corresponding to the transfer length for the initiator 13) in the cache memory 22, and when the target 14 is ready for data transfer, the target 14 sends it to the initiator 13 via the PCI bus 10. To supply.

  Also connected to the PCI bus 10 is a host PCI bridge 15 which is a bridge connecting the PCI bus 10 and the host bus 30. The host PCI bridge 15 not only operates as a bridge between the PCI bus 10 and the host bus 30, but also controls the PCI bus 10 based on control of a CPU (Central Processing Unit) 31 connected via the host bus 30. It also works as a PCI bus controller.

  Further, an arbiter 16 is also connected to the PCI bus 10. The arbiter 16 executes arbitration processing (arbitration) of the right to use the PCI bus 10. In other words, the arbiter 16 accepts requests from each master device, and when receiving a bus request from two or more master devices at the same time, selects which master device is given the right to use the PCI bus 10 Then, the right to use the PCI bus 10 is given to the selected master device, and the permission is notified (grant).

  The local bus 20 to which the target 14 and the local memory 21 are connected is a local bus with respect to the PCI bus 10 serving as a main system bus, and a bus that connects some devices of the image processing apparatus 1 to each other. It is. In addition to the target 14 and the local memory 21, local devices 23-1 to 23 -M are connected to the local bus 20. That is, in the local bus 20, the target 14 and the local memory 21 are also local devices, and between the target 14 and the local memory 21 and each of the local devices 23-1 to 23 -M, PCI As in the case of the bus 10, data transfer is performed.

  In addition to the CPU 31 that controls the entire image processing apparatus 1, a main memory 32 is also connected to the host bus 30. The CPU 31 accesses the main memory 32 via the host bus 30, executes various processes according to a program loaded in the main memory 32, and controls the operations of each unit of the image processing apparatus 1. The main memory 32 also appropriately stores data necessary for the CPU 31 to execute various processes.

  The CPU 31 further includes a ROM (Read Only Memory) 41 in which programs and data executed by the CPU 31 are stored in advance, a rewritable flash memory, and the like, and a storage unit 42 in which programs and data executed by the CPU 31 are stored. A drive 43 is connected to read out programs and data stored in the mounted removable medium 44 and supply them to the CPU 31 under the control of the CPU 31. Furthermore, other devices than those described above may be connected to the CPU 31 such as an input device such as a keyboard and an output device such as a monitor (both not shown).

  In the image processing apparatus 1 configured as described above, when the PCI bus 10 is reset, for example, when the power is turned on, the CPU 31 performs reset processing of the PCI bus 10. , The initiator 13 and the target 14 are controlled, and the transfer length for the initiator 13 is checked. Specifically, the CPU 31 controls the initiator 13 to issue a memory read request (for example, a request to read data from the local memory 21) to the target 14. Further, the CPU 31 causes the target 14 that performs processing for the memory read request to measure the transfer length of data that the initiator 13 acquires in one memory read request.

  Based on such control of the CPU 31, the initiator 13 issues a memory read request to the target 14, and the target 14 performs processing for the read request. At this time, the target 14 reads data having a sufficiently large data amount as the transfer length from the local memory 21 and accumulates it in the cache memory 22. When the target 14 accumulates a sufficient amount of data in the cache memory 22, the initiator 13 starts acquiring the data from the target 14. The target 14 measures the amount of acquisition (number of words).

  The target 14 that has measured the acquisition amount of the initiator 13 holds the acquisition amount as a transfer length for the initiator 13 and ends the investigation process. When normal data transfer is started on the PCI bus 10 and the target 14 issues a memory read request from the initiator 13, the target 14 stores the data for the transfer length for the initiator 13 held in the local memory 21. Read from.

  As each unit operates in this manner, the image processing apparatus 1 suppresses an increase in local memory traffic due to PCI data transfer, and suppresses the occurrence of unnecessary transactions or a decrease in transfer efficiency in PCI data transfer. Thus, the PCI bus 10 and the local bus 20 can be used effectively.

  FIG. 2 is a block diagram showing an example of a detailed configuration inside the CPU 31 of FIG. In FIG. 2, the CPU 31 is shown only for a processing unit related to setting of a transfer length for the initiator 13 by the target 14 described later.

  The CPU 31 includes a reset processing unit 51, a PCI configuration processing unit 52, a check target target specifying unit 53, a transfer length initial value supply unit 54, a transfer length initial value storage unit 55, a master transfer length check control unit 56, and interface processing. A portion 57 is provided.

  The reset processing unit 51 controls the PCI configuration processing unit 52 to the master-specific transfer length investigation control unit 56 to perform processing related to initialization of the PCI bus 10 at the time of reset.

  The PCI configuration processing unit 52 is controlled by the reset processing unit 51 to access each PCI device 11 via the host PCI bridge 15, and to each PCI device 11, a memory address, an I / O address, an interrupt level And configuration processing for assigning system resources such as DMA (Direct Memory Access transfer) channels, loading / unloading drivers, and setting various parameters.

  The investigation target target specifying unit 53 is a device (target device) that is controlled by the reset processing unit 51 and performs processing for setting the transfer length for the master device based on the configuration processing result by the PCI configuration processing unit 52. Is identified. The investigation target target specifying unit 53 determines whether or not the transfer length can be set for each PCI device 11, and specifies a target for executing the investigation processing.

  The transfer length initial value supply unit 54 is controlled by the reset processing unit 51 to read the transfer length initial value 61 stored in the transfer length initial value storage unit 55 and use it as a target device for performing transfer length setting processing. It is supplied to the (target device specified by the survey target target specifying unit 53) via the interface processing unit 57. The transfer length initial value 61 is an initial value of the transfer length for the initiator 13 in the target 14 and is a predetermined value. This transfer length initial value 61 is sufficiently larger than the data amount (number of words) expected as the transfer length for the initiator 13 so that unnecessary processing such as disconnection does not occur in the transfer length checking process described later. Is set to be larger than the maximum transfer length for the initiator 13 to be measured.

  The master-specific transfer length investigation control unit 56 controls the reset processing unit 51 to issue a read request to each master device for the investigation target 14 so that each target 14 can conduct the investigation process. Issue. The master-specific transfer length investigation control unit 56 is controlled by the reset processing unit 51 to cause each target 14 to execute master-specific transfer length investigation processing.

  The interface processing unit 57 executes interface processing with respect to the host bus 30 such as the PCI configuration processing unit 52, the investigation target target specifying unit 53, the transfer length initial value supply unit 54, and the master-specific transfer length investigation control unit 56. The interface processing unit 57 supplies the commands and data issued by each of the above-described units to the host PCI bridge 15 via the host bus 30 and the commands and data supplied from the host PCI bridge 15 in the CPU 31. Or supply to each part.

  FIG. 3 is a block diagram showing a detailed internal configuration example of the target 14 of FIG.

  In FIG. 3, in addition to the cache memory 22 described above, the target 14 includes a master-specific transfer length checking unit 71, a master discriminating unit 72, a transfer length measuring unit 73, a master-specific transfer length storage unit 74, and a data transfer processing unit 75. have.

  The master-specific transfer length checking unit 71 is controlled by the master-specific transfer length checking control unit 56 of the CPU 31 and controls the master discriminating unit 72, the transfer length measuring unit 73, or the data transfer processing unit 75, and the initiator 13 (target 14 And all master devices that perform data transfer) are investigated, and a process for setting each master device is performed.

  As described above, when each master device issues a memory read request to the target 14, the target 14 responds to the request with the amount of data (number of words) that each master device acquires in one access. Data for a certain transfer length is temporarily stored in the cache memory 22, but the transfer length of each master device may be different from each other, and the amount of data (number of words) stored in the cache memory 22 by the target 14, that is, When the transfer length of the master device assumed by the target 14 is larger than the transfer length of the actual master device (that is, when the target 14 accumulates unnecessary data in the cache memory 22), the traffic on the local bus 20 Will increase unnecessarily. On the other hand, when the transfer length of the master device assumed by the target 14 is smaller than the transfer length of the actual master device (that is, the amount of data stored in the cache memory 22 by the target 14 is insufficient for the data transfer processing) If this is the case, unnecessary transactions occur, and traffic on the local bus 20 increases unnecessarily.

  Therefore, the master-specific transfer length check unit 71 is controlled by the master-specific transfer length check control unit 56 of the CPU 31 when the PCI bus 10 is reset, for example, before the actual data transfer, in advance for each master device. Investigate the optimal transfer length. The optimum transfer length is a transfer length that most suppresses an increase in unnecessary traffic and an increase in unnecessary transactions as described above. In other words, the optimum transfer length is the amount of data set so as to approximate (including the case of equality) the amount of data (number of words) that the master device acquires by one access (request) in normal data transfer processing. That is.

  The master determination unit 72 is connected to the PCI bus 10 and the arbiter 16 as will be described later, and executes processing for determining the master device (initiator 13) that issued the read request based on the value of each signal. That is, the master discriminating unit 72 specifies a master device (initiator 13) that is a target for measuring the transfer length when measuring the transfer length.

  The transfer length measurement unit 73 measures the number of continuous transfer words of data for one access of the master device, which is performed by the data transfer processing unit 75 as processing for the memory read processing from the master device, and optimal transfer to the master device. Find the length (optimum transfer length).

  The master-specific optimum transfer length storage unit 74 stores the optimum transfer length 82 for each master device measured by the transfer length measuring unit 73 in a corresponding register. For example, in the case of FIG. 3, the master-specific optimum transfer length storage unit 74 includes a master A optimum transfer length register 81-1, a master B optimum transfer length register 81-2, and a master C optimum transfer length register 81. -3 etc., and the optimum transfer length 82 of the master to which each register corresponds is stored in each register.

  The data transfer processing unit 75 performs bus command / byte enable (C / BE [3: 0] #), device selection (DEVSEL #), target ready (TRDY #), stop (STOP #), and the like of the PCI bus 10. It is connected to various signal buses including the initiator 13 and controls the PCI data transfer processing 12 and the initiator 13 (that is, the master device which is another PCI device 11). The data transfer processing unit 75 is also connected to the local bus 20, and controls data transfer via the local bus 21 and the local devices 23-1 to 23 -M and the local bus 20.

  For example, the data transfer processing unit 75 accepts a memory read request from the initiator 13, accesses the local memory 21 via the bus 20 based on the request, reads data from the address requested to be read, and caches it. The memory 22 is controlled to hold, or the cache memory 22 is controlled to output the held data to the PCI bus 22 word by word.

  At this time, the data transfer processing unit 75 reads the optimum transfer length 82 corresponding to the initiator 13 from the register from the optimum transfer length storage unit 74 for each master based on the determination process of the master determination unit 72, and based on the information, The amount of data (number of words) read from the local memory 21 is controlled.

  The data transfer processing unit 75 is also controlled by the master-specific transfer length checking unit 71 to perform data transfer processing when the initiator 13 checks the transfer length. At this time, the data transfer processing unit 75 reads the data for the transfer length initial value supplied from the CPU 31 from the local memory 21 and stores the data in the cache memory 22. In this data transfer, the transfer length measuring unit 73 monitors the number of words that the cache memory 22 outputs to the PCI bus 20 under the control of the data transfer processing unit 75.

  The cache memory 22 is connected to a signal bus such as an address / data bus (AD [31: 0]) of the PCI bus 20, and is controlled by the data transfer processing unit 75 to transfer the held transfer data 91 to the PCI bus. 20 (address / data bus (AD [31: 0])). The output transfer data 91 is supplied to the initiator 13 via the PCI bus 20.

  Next, connection with the PCI bus 20 of the master discrimination | determination part 72 mentioned above is demonstrated. FIG. 4 is a diagram illustrating a connection relationship between the master determination unit 72 and the arbiter 16.

  As shown in FIG. 4, the master discriminating unit 72 has a request (REQ #) state asserted and deasserted by the L master devices 101-1 to 101-L, which are the PCI devices 11, and the arbiter 16 asserts. And monitor the status of the deasserting grant (GNT #).

  The use right of the PCI bus 10 is occupied by one master device at a certain timing. That is, in the PCI bus 10, a plurality of master devices do not control data transfer at the same time. The right to use the bus is managed by the arbiter 16, and as described above, the arbiter 16 assigns to any one of them based on the request from each master device.

  For example, as shown in FIG. 4, each of the L master devices 101-1 to 101-L (hereinafter referred to as master device 101 if it is not necessary to distinguish) is a signal line that requests the right to use the bus. Are connected to the arbiter 16 by the requests (REQ #) 111-1 to 111-L (hereinafter referred to as the request (REQ #) 111 when there is no need to distinguish them). Each master device requests the arbiter 16 to use the PCI bus 10 by asserting this request (REQ #) 111.

  Each master device 101 also has grants (GNT #) 112-1 to 112-L, which are signal lines for notifying that the arbiter 16 has assigned the right to use the bus (hereinafter, there is no need to distinguish them). (Referred to as a grant (GNT #) 112). The arbiter 16 selects one of the master devices 101 that has asserted the request (REQ #) 111, asserts a grant (GNT #) 112 to the master device 101, and assigns the right to use the PCI bus 10 Notify that.

  As shown in FIG. 4, the master discriminating unit 72 and each of these requests (REQ #) 111 and requests (REQ #) 121-1 to 121 -L (hereinafter referred to as request (REQ #) REQ #) 121), the master device 101 requests the right to use the PCI bus 10 by identifying the status of each request (REQ #) 111.

  Further, as shown in FIG. 4, each of the grants (GNT #) 112 is assigned to each of the grants (GNT #) 122-1 to 122-L. GNT #) 122), and the master device 101 to which the arbiter 16 has assigned the right to use the bus is specified.

  In this way, the master determination unit 72 can determine the master device 101 that is currently performing PCI data transfer by monitoring these signals.

  However, to be exact, the arbiter 16 can be changed when the master device 101 that has given the right to use the PCI bus 10 performs processing such as command issuance and the processing is completed (in the middle of the transaction). Therefore, depending on the timing, the master device 101 that is actually processing may differ from the master device 101 determined from the request (REQ #) 121 and the grant (GNT #) 122.

  Therefore, as shown in FIG. 5, the master discriminating unit 72 also monitors the states of the frame (FRAME #) 131 and the initiator ready (IRDY #) 132 of the PCI bus 10, and based on their signal values, It is determined which master device is the initiator 13.

  The frame (FRAME #) 131 is a signal that is asserted when the initiator starts a transaction. The frame (FRAME #) 131 is continuously asserted during the burst transfer and is deasserted immediately before the last data transfer. The initiator ready (IRDY #) 132 is a signal that is asserted when the initiator is in a data transfer enabled state. That is, when the initiator transfers data, the initiator ready (IRDY #) 132 is always asserted.

  Therefore, while either the frame (FRAME #) 131 or the initiator ready (IRDY #) 132 is asserted, the transaction has not ended and the right to use the bus has not been transferred to another master device. It shows that. The master discriminating unit 72 of the target 14 discriminates the master device 101 (initiator 13) having the right to use the bus by making such judgment from the state of these signals.

  In FIG. 5, the master devices 101-1 to 101-L are connected to the frame (FRAME #) 131 of the PCI bus 10 as signal lines 131-1 to 131-L. The master devices 101-1 to 101-L are also connected to the initiator ready (IRDY #) 132 of the PCI bus 10 as signal lines 132-1 to 132-L.

  Each master device 101 asserts and deasserts the frame (FRAME #) 131 and the initiator ready (IRDY #) 132 of the PCI bus 10 via these signal lines. The master discriminating unit 72 of the target 14 is connected to the frame (FRAME #) 131 via the signal line 141, and is connected to the initiator ready (IRDY #) 132 via the signal line 142, via these signal lines. Thus, the status of the frame (FRAME #) 131 and the initiator ready (IRDY #) 132 of the PCI bus 10 is acquired.

  Next, a processing flow in the image processing apparatus 1 will be described.

  For example, when the PCI bus 10 (and the PCI device 11) is reset, such as when the power is turned on, the reset processing unit 51 of the CPU 31 starts the reset process.

  First, in step S1, the PCI configuration processing unit 52 of the CPU 31 is controlled by the reset processing unit 51 to execute configuration processing, initialize the PCI bus 10 and the PCI device 11, and perform various settings and assignments. Do. Specifically, the PCI configuration processing unit 52 acquires information about the PCI device 111 such as a vendor ID, a device ID, and a class code from the configuration register of each PCI device 11 via the PCI bus 10. The PCI configuration processing unit 52 identifies each PCI device 11 based on the ID and code, and system resources such as a memory address, an I / O address, an interrupt level, and a DMA channel for each device. Assignment, driver loading / unloading, and various parameter settings.

  When the configuration processing as described above is performed, the PCI configuration processing unit 52 of the CPU 31 is controlled by the reset processing unit 51 to end the configuration processing in step S1 and advance the processing to step S2.

  In step S <b> 2, the investigation target target specifying unit 53 is controlled by the reset processing unit 51 to specify a target (survey target) for measuring the optimum transfer length of the master device. When the process of step S2 ends, the investigation target target specifying unit 53 advances the process to step S3.

  In step S <b> 3, the transfer length initial value supply unit 54 of the CPU 141 is controlled by the reset processing unit 51 to read the transfer length initial value 61 stored in advance in the transfer length initial value storage unit 55. Then, it supplies it to the target specified by the survey target target specifying unit 53. When the transfer length initial value is supplied, the transfer length initial value supply unit 54 is controlled by the reset processing unit 51 to advance the process to step S4.

  In step S4, the master-specific transfer length investigation control unit 56 of the CPU 31 is controlled by the reset processing unit 51 to execute the master-specific transfer length investigation control process and control the master-specific transfer length investigation process. Details of the master-specific transfer length investigation control process will be described later with reference to the flowchart of FIG.

  The master-by-master transfer length investigation control unit 56 that has finished the master-by-master transfer length investigation control process that has finished the process of step S4 is controlled by the reset processing unit 51 to end the reset process.

  Next, details of the master-specific transfer length investigation control process executed in step S4 of FIG. 6 will be described with reference to the flowchart of FIG.

  First, in step S21, the master-specific transfer length investigation control unit 56 sets the value of the variable i to “1”.

  In step S22, the master-specific transfer length investigation control unit 56 causes each master device (initiator 13) to execute a memory read process for the i-th investigation target target a predetermined number of times. In other words, each master device issues a memory read request a predetermined number of times in order to the target that is the current investigation target under this control. At this time, the transfer length check process for each master is executed in the target 14. Therefore, by controlling the master device and performing memory read access in this manner, the target to be investigated can measure the transfer lengths of all the master devices that can communicate with the target by a predetermined number of times.

  The master-specific transfer length investigation control processing unit 56 that has finished the process of step S22 advances the process to step S23, increments the variable i, and in step S24, all the investigation target targets (specified by the investigation target target specifying unit 53). For all the targets). If it is determined that there is an unprocessed target, the master-specific transfer length investigation control processing unit 56 returns the process to step S22 and repeats the subsequent processes.

  If it is determined in step S24 that processing has been performed for all the targets to be investigated, the master-specific transfer length survey control processing unit 56 ends the master-specific transfer length survey control processing, and the process proceeds to step S4 in FIG. return.

  As described above, the master-by-master transfer length investigation control unit 56 performs the above-described processing on all investigation target targets to measure the transfer length for each master device.

  Next, the master-specific transfer length check process executed in the target 14 will be described with reference to the flowchart of FIG.

  In step S41, the master-specific transfer length checking unit 71 controls the data transfer processing unit 75 to determine whether or not the transfer length initial value 61 has been supplied. If it is determined that the transfer length initial value 61 has been supplied, the master-specific transfer length checking unit 71 advances the processing to step S42, and sets the supplied transfer length initial value 61 in a predetermined register (not shown).

  When the transfer length initial value 61 is set in the register, the master-specific transfer length checking unit 71 advances the process to step S43. If it is determined in step S41 that the transfer length initial value 61 is not supplied, the master-specific transfer length checking unit 71 omits the process of step S42 and advances the process to step S43.

  In step S43, the master-specific transfer length checking unit 71 controls the data transfer processing unit 75 to determine whether or not a memory read request has been acquired from the initiator 13. If it is determined that the memory read request has been acquired, the master-specific transfer length examining unit 71 advances the process to step S44. In step S44, the master discriminating unit 72 is controlled by the master-specific transfer length examining unit 71 to acquire the state of each signal at this time, discriminate the master that issued the memory read request, and proceed to step S45. .

  In step S <b> 45, the data transfer processing unit 75 returns a retry to the memory read request, accesses the local memory 21, reads data for the transfer length initial value from the local memory 21, and stores it in the cache memory 22. Let

  FIG. 9 is a diagram illustrating an example of the state transition in each signal when the data transfer processing unit 75 returns the retry process.

  When returning the retry process, the data transfer processing unit 75 asserts a stop (STOP #) while asserting the device selection (DEVSEL #). When the assertion of the stop (STOP #) is confirmed, the initiator 13 deasserts the frame (FRAME #), further deasserts the request (REQ #), and temporarily releases the PCI bus 10. When confirming that the frame (FRAME #) is deasserted, the data transfer processing unit 75 deasserts the stop (STOP #) and the device selection (DEVSEL #). Accordingly, the initiator 13 also deasserts initiator ready (IRDY #).

  When the retry is returned, the initiator 13 once releases the PCI bus 10 as described above, and then issues a memory read request having the same contents again. The target 14 returns a retry to the memory read request until it is ready for data transfer. That is, the above processing is repeated until the target 14 is ready for data transfer.

  When the process of step S45 ends, the data transfer processing unit 75 advances the process to step S46, determines whether or not a memory read request has been acquired after completion of data accumulation, and determines that it has been acquired, the process proceeds to step S47. Proceed. In step S47, the transfer length measurement unit 73 executes transfer length measurement processing. Details of the transfer length measurement processing will be described with reference to the flowchart of FIG.

  When the transfer length measurement process ends, the master-specific transfer length examining unit 71 advances the process to step S48. If it is determined in step S43 that the memory read request has not been acquired, the data transfer processing unit 75 advances the process to step S48. Furthermore, if it is determined in step S46 that a memory read request has not been acquired after the completion of data accumulation, the data transfer processing unit 75 advances the process to step S48.

  In step S48, the master-by-master transfer length checking unit 71 determines whether or not to end the master-by-master transfer length check process. . If it is determined that the master-specific transfer length investigation process is to be terminated, the master-specific transfer length investigation unit 71 terminates the master-specific transfer length investigation process.

  Next, transfer length measurement processing will be described with reference to the flowchart of FIG.

  In step S61, the transfer length measuring unit 73 initializes the value of a built-in transfer length counter (not shown), and proceeds to step S62. In step S 62, the data transfer processing unit 75 causes the PCI bus 10 to output the first one word of the transfer data 91 stored in the cache memory 22.

  In step S63, the transfer length measurement unit 73 increments the transfer length counter once to measure the number of words output from the cache memory 22. In step S64, the data transfer processing unit 75 determines whether or not the data transfer end is notified from the master (initiator 13).

  In the memory read cycle (transaction by memory read request), as shown in FIG. 11, the initiator 13 deasserts the frame (FRAME #) immediately before the last data (data 3) is acquired (clock 9). And the transaction ends with the next data. That is, when the initiator 13 acquires data in a state where the frame (FRAME #) is deasserted, the initiator 13 deasserts the initiator ready (IRDY #) and releases the bus. Further, when this frame (FRAME #) is deasserted, the target 14 (data transfer processing unit 75) stops supplying data at the next word.

  That is, in step S64 of FIG. 10, the data transfer processing unit 75 monitors the state of the frame (FRAME #) and determines whether or not the end of data transfer has been notified by deasserting. When it is determined that the frame (FRAME #) has not been deasserted and the data transfer end has not been notified, the data transfer processing unit 75 advances the process to step S65 and continues to the next of the transfer data 91 in the cache memory 22. One word is output to the PCI bus 10. The data transfer processing unit 75 that has finished the process of step S65 returns the process to step S63 and repeats the subsequent processes.

  If it is determined in step S64 that the frame (FRAME #) has been deasserted and the end of data transfer has been notified, the data transfer processing unit 75 proceeds to step S66 and controls the cache memory 22 to control the data transfer. Stop output. When the data output stops, the transfer length measuring unit 73 obtains an optimum transfer length based on the value of the transfer length counter in step S67. For example, when the data transfer process is performed a plurality of times and the transfer length is measured a plurality of times, the transfer length measurement unit 73 sets the average value of the transfer lengths as the measurement results as the optimum transfer length. Note that the transfer length measurement unit 73 may set a value other than the average value, such as the maximum value or the minimum value of the measured transfer length group, as the optimal transfer length as the optimal transfer length.

  The transfer length measuring unit 73 that has calculated the optimum transfer length advances the process to step S68, determines whether or not to end the transfer length measurement process, and returns to step S61 if determined not to end, and thereafter. Repeat the process.

  If it is determined in step S68 that the transfer length measurement process is to be terminated, the transfer length measurement unit 73 advances the process to step 69, and sets the optimum transfer length obtained in step S67 to the initiator 13 that has performed the current data transfer. It is set (stored) in the corresponding optimum transfer length register, the transfer length measurement process is terminated, and the process returns to step S47 in FIG.

  By performing the transfer length measurement process as described above, the transfer length measurement unit 73 can obtain the transfer length for the initiator 13.

  Next, a master determination process executed to determine which master device is performing the data transfer performed in the above transfer length measurement process will be described with reference to the flowchart of FIG. In step S69 in FIG. 10, when the obtained optimum transfer length is set in the register, the transfer length measuring unit 73 uses the processing result of the master discrimination process to set the register corresponding to which master device. Judge whether to do.

  In step S81, the master determination unit 72 determines whether any of the grants (GNT #) for each master device is asserted, and waits until it is determined that it is asserted. At this time, the PCI bus 10 is in an idle state in which no master device has acquired the right to use the PCI bus 10 (that is, no data transfer is performed). If it is determined that any of the grants (GNT #) has been asserted, the master determination unit 72 advances the processing to step S82.

  In step S82, the master determination unit 72 sets the master for which the grant (GNT #) is asserted as a specific master. At this time, the master device whose grant is asserted asserts the frame FRAME #. As a result, a transaction occurs on the PCI bus 10 and processing related to data transfer is started.

  When the process of step S82 is completed, the master determination unit 72 proceeds to the process of step S83, determines whether or not the master for which the grant (GNT #) is asserted has been changed, and determines that the master has been changed, the process proceeds to step S84. The process is advanced, and it is determined whether or not the transaction is finished and a bus idle state has occurred, and waits until it is determined that a bus idle state has occurred.

  The PCI bus 10 is in a waiting state (bus idle state) period of at least one clock (for example, clock 2 in FIG. 13) between the end of the previous transaction and the start of the next transaction for driver switching or the like. , Clock 5, clock 9 and clock 11). FIG. 13 shows how the right to use the bus is switched between master a and master b.

  Therefore, even if the arbiter 16 changes the device that asserts the grant (GNT #) during the transaction (the arbiter 16 next assigns the master device to which the bus is given the right to use the bus) If the master device that becomes the initiator 13 is not immediately changed, the process waits until the transaction ends.

  If it is determined in step S84 that the bus idle state has occurred, the master determination unit 72 determines that the transaction has ended, proceeds to step S85, and asserts the specific master as the current grant (GNT #). Change to the master that has been set.

  After completing the process in step S85, the master determination unit 72 advances the process to step S86. If it is determined in step S83 that the master whose grant has been asserted has not been changed, the master determination unit 72 skips steps S84 and S85 and proceeds to step S86.

  In step S86, the master determination unit 72 determines whether or not the grant (GNT #) is deasserted. If it is determined that the grant (GNT #) is deasserted, the process proceeds to step S87, and the bus idle state is reached. It is determined whether a bus idle state has occurred or not.

  Even when the grant (GNT #) is deasserted during the transaction and the arbiter 16 does not assign the right to use the bus to any device, the master discriminator 72 determines that the bus idle Wait until it occurs (until the transaction ends).

  In step S87, when it is determined that a bus idle state has occurred and the transaction has ended, the master determination unit 72 proceeds to step S88 to empty the setting of the specific master.

  When the process proceeds to step S89, the master determination unit 72 determines whether or not to end the master determination process. If it is determined not to end the master determination unit 72, the master determination unit 72 returns the process to step S81, and the subsequent steps. Repeat the process. In step S89, the master discriminating unit 72 that has decided to end the master discrimination processing ends the master discrimination processing.

  If it is determined in step S86 that the grant has not been deasserted, the master determination unit 72 proceeds to step S90, determines whether or not to end the master determination process, and determines that it does not end. The process returns to step S83, and the subsequent processes are repeated. If it is determined in step S90 that the master determination process is to be terminated, the master determination unit 72 ends the master determination process.

  As described above, the master determination unit 72 specifies the master device that becomes the initiator 13. Thereby, the transfer length measuring unit 73 can manage the measured optimum transfer length for each master device (store it in the master-specific optimum transfer length storage unit 74).

  Thus, when the optimum transfer length for each master device is prepared, each PCI device 11 starts a normal PCI data transfer process. At that time, in response to one memory read request, the target PCI device (that is, the target 14) reads the data for the optimum transfer length of the initiator 13 prepared as described above from the local memory 21, and caches it. Stored in the memory 22.

  Next, data transfer processing using the optimum transfer length for each master device prepared as described above will be described with reference to the flowchart of FIG.

  First, in step S101, the data transfer processing unit 75 determines whether or not a memory read request has been acquired. If it is determined that the memory read request has been acquired, the process proceeds to step S102. In step S102, the master discriminating unit 72 is controlled by the data transfer processing unit 75 and discriminates the master that issued the memory read request based on each signal (as the initiator 13) as in the case of the transfer length measurement described above. Identify the working master device).

  In step S103, the data transfer processing unit 75 returns a retry to the memory read request, acquires the master optimum transfer length determined by the master discriminating unit 72 from the master optimum transfer length storage unit 74, and stores the local memory. The data corresponding to the optimum transfer length is read from 21 and stored in the cache memory 22. If the initiator 13 repeatedly issues a memory read request having the same content, the data transfer processing unit 75 returns a retry to each request until data is accumulated.

  When the data accumulation is completed, the data transfer processing unit 75 advances the process to step S104, determines whether or not a memory read request has been acquired after the data storage is completed, and waits until it is determined that the data has been acquired. If it is determined that the data has been acquired, the data transfer processing unit 75 advances the processing to step S105, controls the cache memory 22, causes the data stored in the cache memory 22 to be output to the PCI bus 10, and causes the master (initiator 13) to Forward.

  The data transfer processing unit 75 that has transferred the data proceeds to step S106. If it is determined in step S101 that a memory read request has not been acquired from the master device, the data transfer processing unit 101 omits steps S102 to S105 and proceeds to step S106.

  In step S106, the data transfer processing unit 75 determines whether or not to end the data transfer process. If it determines not to end the process, the process returns to step S101, and the subsequent processes are repeated. If it is determined in step S106 that the data transfer process is to be terminated, the data transfer processing unit 75 ends the data transfer process.

  As described above, the data transfer processing unit 75 acquires the optimum transfer length corresponding to the initiator 13 held in the optimum transfer length storage unit 74 for each master, and performs data transfer using the optimum transfer length. By performing the transfer process in this way, the target 14 can prepare the minimum necessary data for any master device.

  FIG. 15 is a diagram illustrating a case where the transfer length of data transfer by the target 14 differs for each master.

  In FIG. 15, the target 14 is a master which is data corresponding to the master A optimum transfer length 161 stored in the master optimum transfer length storage unit 74 in response to a memory read request from the master device A 151. A transfer data 171 is acquired from the local memory 21, and in response to a memory read request from the master B 152 as a master device, the master B optimum transfer length 162 stored in the master optimum transfer length storage unit 74 Master B transfer data 172 is acquired from the local memory 21, and in response to a memory read request from the master C 153 that is the master device, the master C transfer data 172 stored in the master optimum transfer length storage unit 74 is obtained. Transfer data 173 for master C, which is data for the optimal transfer length 163, is acquired from the local memory 21. That.

  In this way, the target 14 prepares data of the optimum transfer length for each master device, so that the unnecessary occupancy of the local bus 20 is suppressed without increasing the standby time of the master, and the PCI bus 10 or Each device of the local bus 20 can use the bus more effectively.

  In the above description, the case where the initiator 13 and the target 14 are connected to the same PCI bus 10 as the host PCI controller 15 has been described. However, one or both of the initiator 13 and the target 14 is, for example, a PCI−. Of course, other PCI bus PCI devices connected to the PCI bus 10 via a PCI bridge may be used.

  FIG. 16 is a diagram showing another configuration example of the image processing apparatus to which the present invention is applied.

  As shown in FIG. 16, the image processing apparatus 200 has a configuration similar to that of the image processing apparatus 1, and further, a PCI bus 210 is connected to the PCI bus 10 via a PCI-PCI bridge 201. It is connected.

  The PCI-PCI bridge 201 is a device (bridge device) that connects the PCI bus 10 and the PCI bus 210 and relays data transfer between devices on each other's buses.

  The PCI bus 210 is the same bus as the PCI bus 10, and is connected to K PCI devices 211 of PCI devices 211-1 to 211-K (hereinafter referred to as PCI devices 211 when it is not necessary to distinguish them). Has been. The PCI bus 210 is also connected with an arbiter 216 for the PCI bus 210.

  The PCI-PCI bridge 201 operates as both PCI devices of the PCI bus 10 and the PCI bus 210. For example, when the initiator 13 of the PCI bus 10 makes a memory read request to the target 214 of the PCI bus 210, the initiator 10 makes a memory read request to the PCI-PCI bridge 201. That is, the PCI-PCI bridge 201 operates as a target in the PCI bus 10 at this time.

  When the PCI-PCI bridge 201 receives the memory read request, it next operates as an initiator in the PCI bus 210 and makes a memory read request to the target 214 instead of the initiator 13. In response to this request, the target 214 reads the data requested from the local memory 221 via the local bus 220, holds the data in the cache memory 222, and prepares for data transfer. When preparation for data transfer is completed, the target 214 supplies the prepared data to the PCI-PCI bridge.

  In the PCI bus 210, the PCI-PCI bridge 201 operates like an initiator with respect to the PCI bus 210, acquires the data, operates as a target with respect to the PCI bus 10, and incorporates the acquired data. The data is held in the cache memory 202 to be prepared, and preparation for data transfer to the initiator 13 is performed. When the data holding is completed, the PCI-PCI bridge 201 outputs the data to the PCI bus 10 and supplies it to the initiator 13.

  That is, when the PCI bus 210 is considered as a local bus of the PCI-PCI bridge 201, the PCI-PCI bridge 201 has the same configuration as the target 14 in FIG. Accordingly, the PCI-PCI bridge 201 operates basically in the same manner as in the case of the target 14 in FIG. 1 in such data transfer. Then, the CPU 31 performs the control process as described above for the PCI-PCI bridge 201 and the target 214. In this case, since the PCI-PCI bridge 201 operates as an initiator for the PCI bus 210, the target 214 also performs an optimum transfer length measurement process for the PCI-PCI bridge 201.

  In the above description, the case where the initiator exists on the PCI bus 10 side and the target exists on the PCI bus 210 side has been described. However, the image processing apparatus 200 has a target on the PCI bus 10 side and PCI Data transfer such that an initiator exists on the bus 210 side can also be performed.

  In that case, the PCI-PCI bridge 201 operates as a target for the PCI bus 210 and operates as an initiator for the PCI bus 10 side. That is, the PCI-PCI bridge 201 operates on the PCI bus 10 in the same manner as the target 14 in FIG. 1 as described above, but conversely operates on the PCI bus 210 in the same manner as the target 14 in FIG. You can also

  FIG. 17 is a block diagram illustrating an internal configuration example of the PCI-PCI bridge 201. As described above, the PCI-PCI bridge 201 has basically the same configuration as that of the PCI bus 10, but as a master determination unit, the first PCI bus master determination unit 272-1 for the PCI bus 10, There are two master discriminating units, a second PCI bus master discriminating unit 272-2 for the PCI bus 210. In addition, a switching unit 271 is newly provided in order to switch the operations of the master determination units. The switching unit 271 includes a first PCI bus master determination unit 272-1 and a second PCI bus master determination unit 272-2 depending on which side the PCI-PCI bridge 201 performs data transfer with the PCI bus 10 or the PCI bus 210. Either one of them is operated. Further, the data transfer processing unit 75 and the cache memory 22 are connected to the PCI bus 210 in the same manner as the PCI bus 10 described above.

  As shown in FIG. 18, each of the first PCI bus master discriminating unit 272-1 and the second PCI bus master discriminating unit 272-2 is similar to the case of the master discriminating unit 72 shown in FIG. Or it is connected to the arbiter 216, and monitors the request (REQ #) state asserted by each PCI bus master device and the grant (GNT #) state asserted by each arbiter.

  Specifically, the first PCI bus master determination unit 272-1 receives requests (REQ #) 111-1 to 111-L, which are signal buses to which the master devices 101-1 to 101-L and the arbiter 16 are connected. Each is connected by a request (REQ #) 121-1 to 121-L which is a signal bus. Similarly, the second PCI bus master determination unit 272-2 is connected to the master devices 301-1 to 301-L. And request (REQ #) 311-1 to 311-L which are signal buses to which the arbiter 216 is connected, and requests (REQ #) 321-1 to 321-L which are signal buses.

  Further, as shown in FIG. 19, the first PCI bus master discriminator 272-1 and the second PCI bus master discriminator 272-2 are respectively similar to the master discriminator 72 of FIG. It is connected to the frame (FRAME #) 131 or 331 and the initiator ready (IRDY #) 132 and 332, and the state of the frame (FRAME #) asserted by the master device of each PCI bus and the initiator ready (IRDY #) ) Status.

  Specifically, the first PCI bus master determination unit 272-1 is connected to the frame (FRAME #) 131 and the initiator ready (IRDY #) 132, which are signal buses of the first PCI bus 10, by signal lines 141 or 142. Similarly, the second PCI bus master determination unit 272-2 is connected to a frame (FRAME #) 331 and an initiator ready (IRDY #) 332, which are signal buses of the second PCI bus 210, by a signal line 341 or 342. Has been.

  In the image processing apparatus 200 having such a PCI-PCI bridge 201, the processing of each unit basically operates in the same manner as the image processing apparatus 1 in FIG. With reference to the flowchart of FIG. 20, the master-by-master transfer length check process by the PCI-PCI bridge 201 will be described. Also in this case, the processing is basically performed in the same manner as the master-specific transfer length check process by the target 14 shown in FIG. 1 described with reference to the flowchart of FIG.

  That is, in FIG. 20, Steps S121 through S123 correspond to Steps S41 through S43 in FIG. 8, respectively, and Steps S125 through S129 correspond to Steps S44 through S48 in FIG. Is done.

  That is, when the data transfer processing unit 75 of the PCI-PCI bridge 201 acquires a memory read request in step S123 of FIG. 20, the process proceeds to step S124. At this time, the switching unit 271 identifies the side that issued the memory read request in step S124, performs switching processing so that the PCI bus master determination unit on that side operates, and advances the processing to step S125.

  That is, the master discriminating unit that is controlled to operate executes the process of step S125.

  As described above, by performing the switching process, the PCI-PCI bridge 201 operates like the target 14 described above, and can suppress an increase in traffic on both the PCI bus 10 and the PCI bus 210. .

  That is, the image processing apparatus 200 having a plurality of PCI buses not only suppresses the occupancy of unnecessary local buses, but also suppresses the unnecessary occupancy of each PCI bus, and further improves the transfer efficiency of data transfer in each PCI bus. The decrease can also be suppressed. Accordingly, even when the image processing apparatus 200 has a plurality of system buses, each device of the system bus or the local bus can use the bus more effectively.

  In the above description, the image processing apparatus 200 has two PCI buses and one PCI-PCI bridge. However, the present invention is not limited to this. For example, the image processing apparatus has three or more PCI buses. Of course, the PCI buses may be connected to each other via a PCI-PCI bridge. That is, the initiator and the target may perform data transfer via a plurality of PCI-PCI bridges.

  In the above description, the transfer length is investigated when the PCI bus is reset. However, the present invention is not limited to this, and for example, in normal data transfer, each target performs monitoring processing on the initiator, When inconvenience occurs, the value of the optimum transfer length may be readjusted.

  FIG. 21 is a block diagram showing another example of the internal configuration of the target 14 shown in FIG.

  In FIG. 21, the target 14 has a disconnect monitoring unit 401 in addition to the configuration shown in FIG. 3.

  The disconnect monitoring unit 401 monitors the occurrence of disconnect processing in the data transfer by the data transfer processing unit 75 while monitoring the master determination unit 72 and the data transfer processing unit 75. When the disconnection process occurs, the transfer length measuring unit 73 and the data transfer processing unit 75 are controlled to perform the optimum transfer length resetting process.

  The disconnect monitoring process executed by the disconnect monitoring unit 401 will be described with reference to the flowchart of FIG.

  In step S141, the disconnect monitoring unit 401 determines whether a memory read request has been received. If it is determined that the memory read request has been received, the disconnect monitor 401 proceeds to step S142 and monitors the occurrence of a disconnect. Then, the disconnect monitoring unit 401 determines whether or not a disconnection has occurred in step S143. If it is determined that a disconnection has occurred, the disconnect monitoring unit 401 controls the master determination unit 72 to issue a memory read request in step S144. The issued master is determined, and in step S145, the determined master is requested to issue a read request, and the transfer length measurement unit 73 and the data transfer processing unit 75 are controlled to check the transfer length for the determined master. Execute the process. Details of the transfer length check process will be described with reference to the flowchart of FIG.

  When the transfer length check process for the determined master is completed, the disconnect monitoring unit 401 advances the process to step S146. If it is determined in step S141 that the memory read request has not been received, the disconnect monitoring unit 401 skips steps S142 to S145 and proceeds to step S146. Further, when the disconnect monitoring unit 401 determines in step S143 that no disconnection has occurred, the disconnect monitoring unit 401 omits the processes in steps S144 and S145, and proceeds to step S146.

  In step S146, the disconnect monitoring unit 401 determines whether or not to end the disconnect monitoring process. If it is determined not to end the process, the disconnect monitoring unit 401 returns the process to step S141 and repeats the subsequent processes. If it is determined in step S146 that the disconnect monitoring process is to be terminated, the disconnect monitoring unit 401 ends the disconnect monitoring process.

  Next, details of the transfer length checking process executed in step S145 of FIG. 22 will be described with reference to the flowchart of FIG. This process is basically the same as the master-specific transfer length check process described with reference to the flowchart of FIG.

  However, since the transfer length initial value has already been set in the process at the time of resetting, the processes corresponding to steps S41 and S42 in FIG. 8 are omitted.

  In step S161, the data transfer processing unit 75 determines whether a memory read request has been acquired from the master that measures the transfer length. This process corresponds to step S43 in FIG. If it is determined in step S161 that the memory read request has been acquired, the data transfer processing unit 75 proceeds to step S162, returns a retry to the memory read request, and transfers the data from the local memory 21 to the initial transfer length. Minutes are read out and stored in the cache memory 22. This process corresponds to step S45 in FIG. In the transfer length check process of FIG. 23, since the master for measuring the transfer length is specified in advance, the process corresponding to step S44 of FIG. 8 is omitted.

  When the process of step S162 is completed, the data transfer processing unit 75 advances the process to step S163, determines whether or not a memory read request has been accepted after the completion of data accumulation, and determines that the memory read request has been accepted, the process proceeds to step S164. Proceed. In step S164, the transfer length measurement unit 73 executes a transfer length measurement process as described with reference to FIG. When the transfer length measurement process ends, the transfer length measurement unit 73 advances the process to step S165.

  If it is determined in step S161 that a memory read request has not been acquired, or if it is determined in step S163 that a memory read request has not been accepted after completion of data storage, the data transfer processing unit 75 performs step The process proceeds to S165.

  In step S165, the data transfer processing unit 75 determines whether or not to end the transfer length investigation process. If it is determined not to end, the data transfer processing unit 75 returns the process to step S161, repeats the subsequent processes, and determines to end. In this case, the transfer length check process is terminated, and the process returns to step S145 in FIG.

  As described above, the occurrence of a disconnection is monitored in normal data transfer, and when a disconnection occurs, the target 14 always obtains the optimum transfer length for the initiator 13 by resetting the transfer length. be able to. By doing so, the image processing apparatus 1 can make each system bus or each device of the local bus more effectively use the bus even when the optimum transfer length changes with time. it can.

  As described above, the initiator 13 and the target 14 are the arbitrary PCI devices 11 connected to the PCI bus 10 (or arbitrary PCI devices connected to all the buses when there are a plurality of PCI buses). Thus, the PCI data transfer 12 by them can be applied to data transfer between any PCI devices 11.

  In the above description, the bus system using the PCI bus 110 has been described. However, the system bus may be a bus other than this. In such a bus, the initiator and the target may be connected to different types of buses connected to each other by a bridge.

  Further, when the initiator 13 has a function as a plurality of devices (when it is a multi-function device), the target 14 may set an optimum transfer length for each function of the initiator 13 or the same. One optimum transfer length for the initiator 13 may be shared within one PCI device 11. Conversely, when the target 14 has functions as a plurality of devices, the target 14 may measure the optimum transfer length for the initiator 13 for each function, or measure only one function, and the result Of course, the obtained optimum transfer length may be shared by all the functions of the target.

  In the above description, when the PCI bus 10 is reset, the measurement process of the optimum transfer length for each master device is performed in each target. However, the present invention is not limited to this. For example, a part of the target device Or, in all cases, the optimal transfer length for each master device that was used before resetting is held in a non-volatile memory, etc., and the setting process is omitted after resetting, and the held optimal transfer length is diverted. Of course it is good. By doing so, each target device can omit the setting process and the measurement process as described above, and thus the load of the reset process can be reduced.

  In the above description, the image processing apparatus which is a video device has been described. However, any apparatus having a bus system as described above may be used. For example, an information processing apparatus such as a personal computer or a server may be used. Of course, it may be a mobile device such as a PDA or a mobile phone, or a home appliance such as a television receiver or a hard disk recorder.

  The series of processes described above can be executed by hardware or can be executed by software. In this case, for example, a program and data required for each target device to execute the processing described above, read from the removable medium 44 via the drive 43, are transferred via the PCI bus 10 to each master device ( It may be supplied to a part of the PCI device 11 and installed.

  At that time, when each master device acquires the program and data supplied in such a manner, the master device stores them in a storage unit such as a non-volatile memory in which they are built, and executes those programs as necessary. You may make it perform a process.

  By doing so, for example, an existing master device that does not support the above-described processing can also install necessary programs and data by the CPU 31 by connecting to the PCI bus 10. Accordingly, the image processing apparatus 1 can effectively utilize the PCI bus 10 regardless of what PCI device 11 is connected.

  When the above-described series of processing is executed by software, a program constituting the software is installed from a network or a recording medium.

  For example, as shown in FIG. 1, the recording medium is distributed to distribute a program to a user separately from the apparatus main body, and includes a magnetic disk (including a flexible disk) on which a program is recorded, an optical disk ( Removable media 44 such as CD-ROM (compact disk-read only memory), DVD (including digital versatile disk), magneto-optical disk (including MD (mini-disk) (registered trademark)), or semiconductor memory In addition to being configured, it is configured by a ROM 41 on which a program is recorded, a flash memory included in the storage unit 42, and the like that are distributed to the user in a state of being incorporated in the apparatus main body in advance.

  In the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. It also includes processes that are executed individually.

  Further, in this specification, the system represents the entire apparatus composed of a plurality of devices (apparatuses).

It is a block diagram which shows the structural example of the image processing apparatus to which this invention is applied. FIG. 2 is a block diagram illustrating a detailed configuration example of a CPU in FIG. 1. It is a block diagram which shows the detailed structural example of the target of FIG. It is a figure which shows the example of a connection of the master discrimination | determination part of FIG. It is a figure which shows the example of a connection of the master discrimination | determination part of FIG. It is a flowchart explaining the example of a reset process. It is a flowchart explaining the example of the transfer length investigation control process according to master. It is a flowchart explaining the example of the transfer length investigation process according to master. It is a figure explaining the example of the state transition of the signal in retry. It is a flowchart explaining the example of a transfer length measurement process. It is a figure explaining the example of the state transition of the signal in a memory read cycle. It is a flowchart explaining the example of a master discrimination | determination process. It is a figure explaining the example of the mode of arbitration. It is a flowchart explaining the example of a data transfer process. It is a figure explaining the mode of the data transfer with respect to a memory read request. It is a block diagram which shows the other structural example of the image processing apparatus to which this invention is applied. It is a block diagram which shows the detailed structural example of the PCI-PCI bridge of FIG. It is a figure which shows the example of a connection of the master discrimination | determination part of FIG. It is a figure which shows the example of a connection of the master discrimination | determination part of FIG. It is a flowchart explaining the example of the transfer length investigation process according to master. It is a block diagram which shows the other example of a detailed structure of the target of FIG. It is a flowchart explaining the example of a disconnection monitoring process. It is a flowchart explaining the example of a transfer length investigation process.

Explanation of symbols

  1 image processing device, 10 PCI bus, 11 PCI device, 12 PCI data transfer, 13 initiator, 14 target, 15 host PCI bridge, 16 arbiter, 20 local bus, 21 local memory, 22 cache memory, 31 CPU, 32 main memory, 41 ROM, 42 storage unit, 43 drive, 44 removable media, 51 reset processing unit, 52 PCI configuration processing unit, 53 target target specifying unit, 54 transfer length initial value supply unit, 55 transfer length initial value storage unit, 56 Transfer length check control unit by master, 57 interface processing unit, 61 transfer length initial value, 71 transfer length check unit by master, 72 master discriminating unit, 73 transfer length measurement unit, 74 optimum transfer length storage unit by master, 75 data transfer Transmission processing unit, 82 optimum transfer length, 91 transfer data, 200 image processing device, 201 PCI-PCI bridge, 202 cache memory, 210 PCI bus, 211-1 to 211-K PCI device, 214 target, 216 arbiter, 220 local Bus, 221 local memory, 222 cache memory, 271 switching unit, 272-1 first PCI bus master determining unit, 272-2 second PCI bus master determining unit, 401 disconnect monitoring unit,

Claims (16)

In an information processing apparatus having a system bus to which a plurality of devices are connected, wherein the plurality of devices transfer data to each other via the system bus.
Based on a request of a master device that is a device that controls the data transfer and performs the data transfer, a predetermined data amount of a predetermined data amount is acquired from a predetermined memory device, and is incorporated. Transfer means for executing a first transfer process for transferring the data to the master device via the system bus after being held in the cache memory
In the first transfer process executed by the transfer unit, a measurement unit that measures a second data amount that is the data amount that the master device acquires by one access;
Setting means for setting a third data amount, which is a data amount read from the memory device, based on the second data amount measured by the measuring means;
Storage means for storing the third data amount set by the setting means,
After the third data amount is stored by the storage unit, the transfer unit receives the third data amount stored by the storage unit from the memory device based on a request from the master device. After the data is acquired and held in a built-in cache memory, a second transfer process is performed in which the data is transferred to the master device via the system bus. The information processing apparatus according to claim 1, wherein the first data amount is larger than the maximum second data amount measured by the measuring unit. The information processing apparatus according to claim 2, wherein the setting unit sets the third data amount so that the third data amount approximates the second data amount. First control means for controlling the master device to issue a memory read request;
In response to the memory read request issued under the control of the first control unit, the transfer unit is controlled to execute the first transfer process, and the measurement unit is controlled to control the second data. A second control unit that measures the amount, controls the setting unit to set the third data amount, and controls the storage unit to store the third data amount. The information processing apparatus according to claim 1. The first control means controls the master device to issue the memory read request a plurality of times,
The second control means controls the transfer means to execute the first transfer processing for each of the plurality of memory read requests that are controlled and issued by the first control means, The measurement means is controlled to cause the second data amount to be measured for each of the first transfer processes executed a plurality of times by the transfer means, and the setting means is controlled to perform a plurality of times by the measurement means. The third data amount is set based on a plurality of the second data amounts obtained by the measurement, and the storage unit is controlled to store the third data amount set by the setting unit. The information processing apparatus according to claim 4, wherein: The setting means sets, as the third data amount, an average value, a maximum value, or a minimum value of the plurality of second data amounts obtained by a plurality of measurements by the measuring unit. The information processing apparatus according to claim 5. The first control means controls each of the plurality of master devices, causes the memory read request to be issued for each master device,
The second control unit controls the transfer unit, the measurement unit, the setting unit, and the storage unit to set and store the third data amount for each master device. The information processing apparatus according to claim 4. The first control means controls each of the master devices having a plurality of functions, causes the memory read request to be issued for each function of the master device,
The second control unit controls the transfer unit, the measurement unit, the setting unit, and the storage unit to set and store the third data amount for each function of the master device. The information processing apparatus according to claim 4. Target that specifies a target device to be controlled so that the second control means sets and stores the third data amount from among a plurality of target devices that are counterpart devices of the data transfer of the master device The information processing apparatus according to claim 4, further comprising device specifying means. The information processing according to claim 1, further comprising: a master device determining unit that determines a master device that has issued a request in the first transfer process or the second transfer process executed by the transfer unit. apparatus. The information processing apparatus according to claim 1, further comprising a disconnect monitoring unit that monitors occurrence of disconnect processing in the second transfer processing executed by the transfer unit. An information processing method of an information processing apparatus having a system bus to which a plurality of devices are connected, wherein the plurality of devices transfer data to each other via the system bus,
Based on a request of a master device that is a device that controls the data transfer and performs the data transfer, a predetermined data amount of a predetermined data amount is acquired from a predetermined memory device, and is incorporated. A first transfer step of executing a first transfer process for transferring the data to the master device via the system bus after being held in the cache memory
In the first transfer process executed by the process of the first transfer step, a measurement step of measuring a second data amount that is the data amount acquired by the master device by one access;
A setting step of setting a third data amount, which is a data amount read from the memory device, based on the second data amount measured by the processing of the measuring step;
A storage control step for controlling to store the third data amount set by the setting step;
After the third data amount is stored by being controlled by the process of the storage control step, the memory device is controlled and stored by the process of the storage control step based on the request of the master device. Second transfer for executing second transfer processing for acquiring the third data amount of data and holding it in a built-in cache memory, and then transferring the data to the master device via the system bus An information processing method comprising: steps. In a program having a system bus to which a plurality of devices are connected, and causing the plurality of devices to perform data transfer with each other via the system bus.
Based on a request of a master device that is a device that controls the data transfer and performs the data transfer, a predetermined data amount of a predetermined data amount is acquired from a predetermined memory device, and is incorporated. A first transfer step of executing a first transfer process for transferring the data to the master device via the system bus after being held in the cache memory
In the first transfer process executed by the process of the first transfer step, a measurement step of measuring a second data amount that is the data amount acquired by the master device by one access;
A setting step of setting a third data amount, which is a data amount read from the memory device, based on the second data amount measured by the processing of the measuring step;
A storage control step for controlling to store the third data amount set by the processing of the setting step;
After the third data amount is stored by the process of the storage control step, the third data controlled and stored by the process of the storage control step from the memory device based on the request of the master device. A second transfer step of executing a second transfer process of acquiring the amount of data corresponding to the amount of data and holding the data in a built-in cache memory, and then transferring the data to the master device via the system bus; A program characterized by including. In an information processing apparatus having a plurality of system buses connected to a plurality of devices, wherein the plurality of devices transfer data to each other via the system bus,
In data transfer between devices connected to two system buses and connected to different system buses of the two system buses, based on a request of a master device that is a device that controls the data transfer and performs the data transfer A first data amount that is a predetermined data amount determined in advance from the target device that is the data transfer partner of the master device, and holds the data in a built-in cache memory; Relay means for executing a first relay process for transferring the data;
In the first relay process executed by the relay unit, a measuring unit that measures a second data amount that is a data amount that the master device acquires from the cache memory by one access;
Setting means for setting a third data amount, which is a data amount read from the target device, based on the second data amount measured by the measuring means;
Storage means for storing the third data amount set by the setting means,
After the third data amount is stored by the storage unit, the relay unit receives the third data amount stored by the storage unit from the target device based on a request from the master device. An information processing apparatus that executes a second relay process for transferring the data to the master device via the system bus after the data is acquired and stored in a built-in cache memory. An information processing method of an information processing apparatus having a plurality of system buses to which a plurality of devices are connected, wherein the plurality of devices transfer data to each other via the system bus,
A process of connecting two system buses, and in data transfer between devices connected to different system buses of the two system buses, a master device that is a device that controls the data transfer and performs the data transfer After acquiring a first data amount of a predetermined data amount from a target device that is a partner of the data transfer of the master device based on the request and controlling and holding the cache memory A relay step for executing a first relay process for transferring the data to the master device;
In the first relay process executed by the process of the relay step, a measurement step of measuring a second data amount that is a data amount that the master device acquires from the cache memory by one access;
A setting step for setting a third data amount, which is a data amount read from the target device, based on the second data amount controlled and measured by the process of the measurement step;
A storage control step for controlling to store the third data amount set by the processing of the setting step;
After the third data amount is stored by being controlled by the process of the storage control step, the target device is controlled and stored by the process of the storage control step based on the request of the master device. A second relay process is executed to acquire data for the third data amount, control and hold the cache memory, and then transfer the data to the master device via the system bus. An information processing method comprising: a relay step. In a program having a plurality of system buses to which a plurality of devices are connected, and causing the plurality of devices to perform data transfer with each other via the system bus.
A process of connecting two system buses, and in data transfer between devices connected to different system buses of the two system buses, a master device which is a device that controls the data transfer and performs the data transfer After acquiring a first data amount of a predetermined data amount from a target device that is a partner of the data transfer of the master device based on the request and controlling and holding the cache memory A relay step for executing a first relay process for transferring the data to the master device;
In the first relay process executed by the process of the relay step, a measurement step of measuring a second data amount that is a data amount that the master device acquires from the cache memory by one access;
A setting step for setting a third data amount, which is a data amount read from the target device, based on the second data amount controlled and measured by the process of the measurement step;
A storage control step for controlling to store the third data amount set by the processing of the setting step;
After the third data amount is stored by being controlled by the process of the storage control step, the target device is controlled and stored by the process of the storage control step based on the request of the master device. A second relay process is executed to acquire data for the third data amount, control and hold the cache memory, and then transfer the data to the master device via the system bus. A relay program comprising:

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