JP2004213255A - Controlling method for pci bus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PCI bus controlling method having high usage efficiency for connecting a plurality of devices to a mother board by using a PCI bus efficiently. <P>SOLUTION: A CPU 1 and a main storage memory 2 are arranged on the mother board, the PCI bus is formed via a host bridge 3, and PCI slots 0-2 are connected to the PCI bus. A PCI device A is connected to the PCI slot 0, while a waiting counter 5 and waiting counter values F.F6 are mounted to the PCI device A. When the PCI device A accesses the mother board, the waiting counter 5 counts a time to re-access for controlling the PCI bus efficiently. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a control method for a PCI bus that uses a PCI (peripheral component interconnect bus) to connect a plurality of devices to a motherboard to exchange data.
[0002]
[Prior art]
When a plurality of devices are connected to a motherboard using PCI slots to access a memory or the like on the motherboard, it is necessary to use a PCI bus efficiently.
[0003]
For example, when a printer device is used as a device, the printer device is connected to a PCI slot, and a storage device is accessed via a PCI bus. In this case, the device connected to the PCI bus becomes the master and accesses the storage device on the motherboard.
[0004]
Conventionally, when a host bridge built on a host device (motherboard) supports a delayed transaction, if a device has a data read access (REQ), a retry response is received from the motherboard (GNT), and a request is made on the motherboard. The PCI bus is released until the data with the error can be prepared. Therefore, no specific device basically occupies the PCI bus.
[0005]
Also disclosed is an invention that, when there is an access request from a plurality of devices connected to the PCI bus, sets a mask time based on the correspondence between the request source device and the request destination device, and responds to access from a specific request source device. (Patent Document 1).
[0006]
[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-207354
[Problems to be solved by the invention]
However, in the above-described PCI bus release control, a device that has made a read access to the storage device performs a read access again after a certain period of time, and by repeating this process, the processing efficiency of the PCI bus decreases. That is, the processing efficiency is lower than when the PCI bus is completely released.
[0008]
In view of the above problems, the present invention provides a method for controlling a PCI bus that uses a PCI bus efficiently and has excellent utilization efficiency.
[0009]
[Means for Solving the Problems]
According to the first aspect of the present invention, there is provided a first process for repeatedly performing re-access in response to a retry request from a target, and counting by a counting means provided in a master after the retry request. Performing a second process of storing the count value in the storage means when there is a response from the target, and performing a re-access using the count value stored in the storage means at the time of re-access from the master. This can be achieved by providing a method of controlling a PCI bus that performs a third process of setting a timing and a fourth process of re-accessing a target according to the timing.
[0010]
With this configuration, the next access request can be made based on the time from the previous access request to the retry, and a device such as a printer can efficiently make an access request to the target. .
According to a second aspect of the present invention, in the first aspect of the invention, the fourth processing is executed based on a count value smaller than the count value stored in the storage means.
[0011]
With this configuration, the access request can be made by subtracting the time from the previous access request to the retry for the target. Therefore, an access request can be made more efficiently.
According to a third aspect of the present invention, in the configuration of the second aspect, when the next access is performed based on a count value smaller than the count value stored in the storage unit, a time of a retry performed by the target is calculated. .
[0012]
With this configuration, the time from the access request to the retry to the target can be accurately known, and the access request can be made efficiently immediately after the previous retry and immediately before the next retry.
According to a fourth aspect of the present invention, there is provided a method as set forth in the first, second, or third aspect, further comprising: a process of storing the number of bursts of the target; This is a configuration for performing.
[0013]
With this configuration, the interruption request can be efficiently executed even for the burst request for the target.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<First embodiment>
FIG. 1 is a system configuration diagram including a PCI bus used in this example. In FIG. 1, a CPU 1 is a central processing unit, and performs processing according to a program stored in a main memory 2 constructed on a motherboard.
[0015]
The host bridge 3 is an interface (I / F) between the host device and a device connected to the PCI bus. A plurality of slots are connected to the host bridge 3 via the PCI bus. The PCI device A is connected, the PCI device B is connected to the PCI slot 1, and the PCI device C is connected to the PCI slot 2.
[0016]
Here, the PCI device has a master function and can access the main storage memory 2 on the motherboard. The host bridge 3 on the motherboard responds as a target to the access requests of the PCI devices A to C, and exchanges data with the main memory 2.
[0017]
The host bridge 3 also arbitrates the PCI bus, issues a retry to a memory access request from the PCI devices A to C, and releases the PCI bus. In the meantime, the CPU 1 accesses the main storage memory 2 to prepare, for example, read data. Further, while accessing the main storage memory 2, the host bridge 3 reissues a retry when there is an access request to the main storage memory 2 again.
[0018]
On the other hand, a sequencer 4 is provided in the PCI device A, and a standby counter 5 and a standby counter value F. F6 is connected. The standby counter 5 is a counter that performs a counting process after a FRAME output described later is issued from the host bridge 3 until a TRDY signal is output. The standby counter value F. F6 records a count value corresponding to the count value of the standby counter 5 and is used for a request request from the PCI device A thereafter.
[0019]
In the above configuration, the processing of this example will be described below. FIG. 2 is a time chart for explaining the processing of this example, and FIGS. 3 and 4 are flowcharts for explaining the processing of this example.
First, the PCI device A issues a read access request to the host bridge 3 via the PCI bus in order to read data stored in the main memory 2 on the motherboard (step (hereinafter referred to as S) 1). ). For example, this timing is (1) shown in FIG.
[0020]
When the request is asserted, the host bridge 3 determines whether the PCI bus can be used and asserts GNT (YES in ST2, (2) shown in FIG. 2). After this GNT is asserted, the use of the PCI bus is enabled, and the bus cycle is executed by the drive of the PCI device A (S3, FRAME output (3) shown in FIG. 2). That is, the timing of the address phase (AD [31: 0] shown in FIG. 2) for presenting the address of the read data to the main memory 2 ((4) shown in FIG. 2), and the data phase in which data transfer is possible ( The timing of (C / BE [3: 0] shown in FIG. 2) ((5) shown in FIG. 2) is secured (S4), and the output of DEVSEL from the host bridge 3 is waited.
[0021]
Here, the host bridge 3 outputs DEVSEL and STOP (request) in order to suspend the bus cycle until the requested data is prepared in the main storage memory 2 (YES in S5, YES in S6). ). Therefore, at this timing, the bus cycle is temporarily ended (S7, (6) shown in FIG. 2).
[0022]
On the other hand, the standby counter 5 in the PCI device A starts the counting process at the output timing of the FRAME (S8) and continues the counting process. During this time, the PCI device A issues a read access request to the host bridge 3 at a predetermined cycle to read data stored in the main memory 2 on the motherboard (S1), and repeats the above processing (S2 to S7, (7) shown in FIG. 2).
[0023]
Thereafter, when the designated data is ready to be output from the main storage memory 2 to the PCI device A, TRDY is output from the host bridge 3 to the PCI bus, and the PCI device A is notified that the data transfer is ready. (YES in S9, timing (8) shown in FIG. 2).
[0024]
When TRDY is output from the host bridge 3 (YES in S9), the PCI device A inputs data transferred from the host bridge 3 via the PCI slot 0 based on the output of IRDY. Then, the bus cycle ends (S10). At the same time, the counting process of the standby counter 5 ends (S11). In this example, the count value of the standby counter 5 at this time is set to "32" ([9] shown in FIG. 2).
[0025]
Thereafter, the PCI device A issues a read access request to the host bridge 3 via the PCI bus to read data from the main storage memory 2 again. FIG. 4 is a flowchart illustrating processing when a second memory read is performed from the PCI device A.
[0026]
In this case, it is determined whether the PCI bus can be used as described above, and the GNT signal is asserted (YES in S13, (2) 'shown in FIG. 2). Then, the counting process of the standby counter 5 is started simultaneously with the output of the FRAME (S14, S15, (3) 'timing shown in FIG. 2).
[0027]
Further, the PCI bus secures the timing of the address phase for presenting the address of the data read to the main memory 2 and the timing of the data phase of the data transfer (S16), and waits for the output of the DEVSEL from the host bridge 3.
Here, similarly to the above, the host bridge 3 outputs DEVSEL and STOP to stop the bus cycle until the requested data is prepared in the main storage memory 2 (YES in S17, YES in S18). ). Therefore, the bus cycle is temporarily terminated at this timing (S19, (6) 'shown in FIG. 2).
[0028]
Thereafter, the standby counter 5 which has started the counting process by the above process continues the counting process, and during this time, the request request as in the case of the first data read is not performed. That is, during this time, the data read request request is not issued from the PCI device A. Therefore, at the time of the second data read, there is no request from the PCI device A, no GNT output from the host bridge 3, etc. on the PCI bus, as indicated by the timing {circle around (7)} ′ in FIG. The bus can be used effectively.
[0029]
Thereafter, when the standby counter 5 counts up (S20: YES), the PCI device A issues a request request. At this time, the count value of the standby counter 5 is equal to the standby counter value F. The count value of the standby counter 5 is compared with the count value stored in the standby counter value F.F6. When the count value recorded in F6 has been reached, the counting process ends.
[0030]
Here, the standby counter value F. In F6, a count value obtained by subtracting 4 counts from the count value "32" of the standby counter 5 is recorded. The four counts are for removing the count values up to the FRAME output from the second time.
Therefore, the count value "28" is based on the history of the previous request, and when the request is output from the PCI device A, TRDY is immediately output from the host bridge 3 (S21, ▲ shown in FIG. 2). 8) ′), the PCI device A inputs data transferred from the host bridge 3 via the PCI slot 0 based on the output of IRDY. Then, the bus cycle ends (S22).
[0031]
Thereafter, the processing for the third data read, the fourth data read,... Is repeated according to the flowchart shown in FIG. 4, and the PCI bus can be effectively used.
As described above, according to the present embodiment, the processing is performed according to the time chart shown in FIG. 2, and it can be seen that the PCI bus release time is longer than, for example, the time chart of FIG. 5 which is the conventional processing.
[0032]
In this example, the count value of the standby counter 5 is not limited to “32”, but may be another count value. Further, the present invention can be similarly executed not only for the PCI device A but also for a device connected to another PCI slot.
<Second embodiment>
Next, a second embodiment of the present invention will be described.
[0033]
This example corresponds to the standby counter value F. described in the above embodiment. In this configuration, the count value stored in F6 is subtracted by one for each output of a request. This will be specifically described below.
FIG. 6 is a flowchart for explaining this example. As in the above-described embodiment, the output of the request from the PCI device A, the output of the GNT from the host bridge 3, and the output of the FRAME and the output of the IRDY are performed. It is performed sequentially. In this example, the count value obtained by the same processing as described above is sequentially subtracted, and the PCI bus is used more efficiently.
[0034]
For example, in the figure, the count value counted by the standby counter 5 first is “32”, and the standby counter value F. In F6, the count value of "28" is recorded as the initial value as described above ((1) shown in FIG. 6).
Thereafter, the standby time for the next request from the PCI device A is set to the count value of “27” ((2) shown in FIG. 9). When the standby counter 5 counts 27, data transfer from the host bridge 3 starts. Is Therefore, data can be transferred earlier by one count, and data can be transferred quickly.
[0035]
Further, the standby time for the next request from the PCI device A is set to the count value of “26” ((3) shown in FIG. 9). When the standby counter 5 counts 26, data transfer from the host bridge 3 starts. Is Therefore, data can be transferred one count earlier, and data can be transferred quickly.
[0036]
Hereinafter, by performing the same processing, data transfer processing can be performed at high speed.
If the host bridge 3 is not ready for data transfer at the time when the count processing is completed and the request is made again, the count value is incremented ((4) shown in FIG. 6). Configure to make the next data request.
[0037]
Thereafter, when the PCI device A reads data as shown in FIG. The count value of F6 is set to “27” and is maintained for a certain period.
With this configuration, the data transfer can be performed at high speed, the data transfer can be performed with flexibility, and the PCI bus can be efficiently controlled.
<Third embodiment>
Next, a third embodiment of the present invention will be described.
[0038]
This embodiment provides a PCI bus control method that performs the same processing as described above even in the burst mode and performs burst access efficiently. This will be specifically described below.
FIG. 8 is a system configuration diagram including a PCI bus used in this example. 1 is basically the same as that of FIG. 1 described above, except that the counter connected to the sequencer 7 in the PCI device A is different. In other words, the burst number counter 8 is connected to the sequencer 7 so as to efficiently perform burst transfer.
[0039]
The host bridge 3 can cope with burst memory access from the PCI bus, and the host bridge 3 has a fixed number of burst accesses to the main memory 2. For example, in this example, this fixed value is “4”. Note that this fixed value “4” means that when data is read, if data is output only four times in response to a read access request from the PCI device A, a disconnect is issued and the burst access processing is interrupted. Used for
[0040]
FIG. 9 is a flowchart for explaining the processing of this example. When there is a memory read request as described above, it is first determined whether or not the PCI bus can be used, and the GNT signal is asserted (ST1, ST2 are YES, (1) and (2) shown in FIG. 9).
Thereafter, a burst read bus cycle is started as a master device (ST3 to ST6), and at the same time, the number of TRDYs output by the host bridge 3 is counted by the burst number counter 8. As described above, the target host bridge 3 outputs TRDY only four times in response to the burst request from the PCI device A, and finally issues a disconnect.
[0041]
When this disconnect is issued, the PCI device A deasserts FRAME and ends the access cycle. Also, the counting process by the burst number counter 8 ends (ST8, ST9).
Next, the number of burst accesses of the PCI device A for the second and subsequent times is terminated by the count value counted by the burst number counter 8. At this time, the number of clocks required for the access cycle is set one count smaller than the first time as shown in FIG.
[0042]
With this configuration, the number of bursts can be reduced to just before the disconnect is issued and the interruption request is output, and the access time for data transfer can be reduced.
[0043]
【The invention's effect】
As described above in detail, according to the present invention, the PCI bus can be used efficiently, and data transfer can be performed at high speed.
Further, the PCI bus can be used efficiently for burst transfer requests.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram including a PCI bus used in a first embodiment.
FIG. 2 is a time chart illustrating a process according to the first embodiment.
FIG. 3 is a flowchart illustrating a process according to the first embodiment.
FIG. 4 is a flowchart illustrating a process according to the first embodiment.
FIG. 5 is a time chart illustrating a conventional process.
FIG. 6 is a time chart illustrating a process according to a second embodiment.
FIG. 7 is a time chart illustrating a process according to the second embodiment.
FIG. 8 is a system configuration diagram including a PCI bus used in a third embodiment.
FIG. 9 is a flowchart illustrating a process according to a third embodiment.
FIG. 10 is a time chart illustrating a process according to the third embodiment.
[Explanation of symbols]
1 CPU
2 Main memory 3 Host bridge 4 Sequencer 5 Standby counter 6 Standby counter value F
7 Sequencer 8 Burst count counter

Claims (4)

A first process of repeatedly performing re-access in response to a retry request from the target;
After the retry request, counting is performed by counting means provided in the master, and when there is a response from the target, a second process of storing the counted value in the storage means,
A third process of setting a re-access timing using the count value stored in the storage unit at the time of re-access from the master;
A fourth process of re-accessing the target according to the timing;
And controlling the PCI bus. 2. The method according to claim 1, wherein the fourth processing is performed based on a count value smaller than the count value stored in the storage unit. 3. The PCI bus control method according to claim 2, wherein when the next access is performed based on a count value smaller than the count value stored in the storage unit, a time of a retry performed by the target is calculated. 4. The PCI bus according to claim 1, wherein a process of storing the number of bursts of the target and a process of interrupting the burst at a number of times smaller than the number of times stored when the access is performed again are performed. Control method.

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