JP6094320B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and relates to, for example, prevention of a short circuit when forming a rewiring structure.

  In recent years, along with demands for downsizing, high performance, and low prices for electronic devices, along with miniaturization and multi-terminals of semiconductor chips, miniaturization and multilayering of circuit boards on which semiconductor chips are mounted, and the circuit boards High-density mounting of electronic components is being promoted. For this reason, with the increase in the number of terminals of semiconductor chips and the narrowing of the pitch of these terminals, fine wiring is also required for multilayer circuit boards.

  In order to meet such demands, pseudo SOC (System On Chip) in which a plurality of types of semiconductor chips are integrated with a mold resin has attracted attention (for example, see Patent Document 1). When forming such a pseudo SOC, it is necessary to form a rewiring structure on the surface thereof.

  When such a rewiring structure is formed, it has been studied to form a buried Cu wiring by using a damascene method. However, when Cu wiring is formed by the damascene method, the erosion (erosion) proceeds in the dense wiring area and the height of the wiring or via decreases, but the wiring or via height increases in the sparse wiring area. There is a problem that becomes high.

  Therefore, in order to solve such a problem, it has been proposed to provide a polishing stopper film in a portion where wiring is dense (see, for example, Patent Document 2). Here, with reference to FIG. 9, a conventional wiring forming method by the improved damascene method will be described. First, as shown in FIG. 9A, wirings 82 and 83 are provided on a silicon substrate (not shown) through a resin layer 81 and covered again with the resin layer 84. Next, a polishing stopper film 85 such as SiN is provided on the surface.

  Next, as shown in FIG. 9B, the polishing stopper film 85 other than the region where the wiring is dense is removed by selective etching. Next, as shown in FIG. 9C, wiring trenches 86 or via holes 87 reaching the wirings 82 and 83 are formed.

  Next, as shown in FIG. 9D, a barrier film and a plating seed layer (both not shown) are provided on the entire surface, and then a Cu plating film is deposited by an electrolytic plating method. Next, the excess Cu plating film is removed by a CMP (Chemical Mechanical Polishing) method, and the via 88 or the embedded wiring 89 is formed. The polishing may be stopped at the polishing stopper film 85, and the polishing stopper film 85 may be removed by etching, or the polishing stopper film 85 itself may be removed by polishing.

  In this way, by providing the polishing stopper film in a region where the wiring is dense, the height of the Cu wiring or via can be made uniform.

JP 2009-064954 A JP 2001-230251 A

  However, when the polishing stopper film is provided in a region where the wiring is dense as described above, the metal may remain in the region where the wiring is sparse after the CMP process. And it is difficult to predict this remaining pattern, and this residue may short-circuit between the wirings.

  In other words, in conventional LSI rewiring, wafer level package, or pseudo SOC, when a damascene wiring is formed by filling Cu in a trench formed in an interlayer insulating film made of resin, a barrier metal and plating is formed on the resin. Ti / Cu is formed as a seed.

  However, since the spacing between the trenches is wide in a region where the wiring is sparse, the Ti film is not sufficiently polished and a residue may be generated. This residue causes a short circuit between the wires and deterioration of the breakdown voltage. . Here, this situation will be described with reference to FIG.

  FIG. 10 is an explanatory diagram of problems in the conventional improved damascene method, FIG. 10 (a) is a conceptual plan view, and FIG. 10 (b) is a point connecting AB in FIG. 10 (a). It is a conceptual sectional view along a chain line. In a region where the embedded wiring 95 is sparse, the polishing rate is low, and thus a barrier film residue 96 is generated between the embedded wiring 95. Reference numerals 91, 92, and 93 in the figure are a connection post, a resin layer, and a permanent insulating film, respectively, and FIG. 9 shows a more realistic configuration.

  Accordingly, it is an object of the semiconductor device and the manufacturing method thereof to prevent a short circuit between wirings and a decrease in breakdown voltage due to a metal residue accompanying rewiring formation.

From one aspect disclosed, a semiconductor substrate on which an element is formed, an embedded wiring formed on a surface of the semiconductor substrate, and a recess pattern in which a barrier film is formed on a surface in a region where the embedded wiring is sparse Yes, and the semiconductor device, wherein a metal other than the barrier layer in the recess pattern is not embedded are provided.

  From another viewpoint to be disclosed, a step of forming an insulating film on a semiconductor substrate on which an element and an external connection land are formed, a trench for forming at least embedded wiring in the insulating film, and a density of the trench Forming a recess pattern in a sparse region, forming a barrier film and a plating seed layer on the exposed surface including the trench and the recess pattern, and at least Cu in the region excluding the recess pattern. A process of selectively depositing a Cu-based conductor by plating to completely fill the trench, and removing unnecessary portions of the Cu-based conductor, plating seed layer and barrier film by polishing to form a buried wiring There is provided a method of manufacturing a semiconductor device characterized by comprising the steps of:

According to the disclosed semiconductor device and the manufacturing method thereof, it is possible to prevent a short circuit between wirings and a decrease in breakdown voltage due to a metal residue accompanying rewiring formation.

It is explanatory drawing of the semiconductor device of embodiment of this invention. It is explanatory drawing of the density of a recessed part pattern. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 1 of this invention. FIG. 4 is an explanatory view up to the middle of FIG. 3 and subsequent steps of the manufacturing process of the semiconductor device of Example 1 of the present invention. FIG. 5 is an explanatory view up to the middle of FIG. 4 and subsequent steps of the manufacturing process of the semiconductor device of Example 1 of the present invention. FIG. 6 is an explanatory diagram of the semiconductor device manufacturing process of Example 1 of the present invention after FIG. It is explanatory drawing immediately after CMP of the semiconductor device of Example 1 of this invention. It is a conceptual sectional view of pseudo SOC of Example 2 of the present invention. It is explanatory drawing of the wiring formation method by the conventional improved damascene method. It is explanatory drawing of the problem in the conventional improved damascene method.

  Here, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention, FIG. 1 (a) is a conceptual plan view, and FIG. 1 (b) is a point connecting AB in FIG. 1 (a). It is a schematic sectional drawing in alignment with the dashed line. As shown in FIG. 1, a barrier film 8 serving as a polishing promotion pattern is formed on the surface in a region where the embedded wiring 9 embedded in the insulating layer 5 formed on the surface of the semiconductor substrate 1 on which the element is formed is sparse. A concave pattern 7 is provided. Reference numerals 2, 3, 4, and 6 in FIG. 1 denote an external connection land, a cover film, a connection post, and a trench, respectively.

  In this case, the planar shape of the concave pattern 7 is either a rectangle or a circle, and the short side of the rectangle or the short axis length of the circle is three times or more the minimum wiring width W of the embedded wiring 9. It is desirable. Therefore, when the minimum wiring width W of the embedded wiring 9 is 5 μm, the shortest portion length L of the concave pattern 7 is set to 15 μm or more. Typically, a square with a side of 15 μm to 50 μm or a circle with a diameter of 15 μm × 50 μm is used, but it may be rectangular, trapezoidal, elliptical, or any shape.

  Further, the distance d between the concave pattern 7 and the embedded wiring 9 is preferably set to be twice or more the height of the embedded wiring 9. That is, when the insulating layer 5 is a resin layer, in the curing step when the trench 6 and the recess pattern 7 are formed in the resin layer, if the distance d between the two is narrow, the trench is caused by the stress due to the shrinkage of the insulating film during the curing. As the depth of 6 increases, the sidewall of the trench 6 is inclined and the shape of the embedded wiring 9 is distorted. Therefore, in order to form the buried wiring 9 as designed, the distance d between them needs to be at least twice the height of the trench 6.

  The density of the concave pattern 7 is preferably 10% to 100%, more preferably 40% to 100% of the maximum density portion of the embedded wiring 9 formed with the minimum wiring width. Here, the density of the concave pattern 7 will be described with reference to FIG. If the maximum density is when the embedded wiring 9 is formed with a 1: 1 L & S pattern, the area occupation ratio of the embedded wiring is 50%.

As described above, when the minimum wiring width W of the embedded wiring 9 is 5 μm, the shortest portion length L of the concave pattern 7 is 15 μm or more. When the distance D ′ between the centers of the recess patterns 7 adjacent to each other is 21.3 μm, the area occupation ratio of the recess patterns 7 is about 50%, and the maximum density of the embedded wiring 9 formed with the minimum wiring width. It corresponds to 100% of the part. Further, when the distance D ′ between the centers of the recess patterns 7 adjacent to each other is set to 67.1 μm, the area occupation ratio of the recess pattern 7 is about 5%, and the embedded wiring 9 formed with the minimum wiring width is formed. It corresponds to 10% of the maximum density part. In order to obtain 40% of the maximum density portion of the embedded wiring 9 formed with the minimum wiring width, the distance D ′ between the centers of the recess patterns 7 adjacent to each other may be set to 33.6 μm.

  By providing such a concave pattern 7 serving as a polishing promoting pattern, no residue of the barrier film 8 is generated in a flat portion in a region where the embedded wiring 9 is sparse, thereby preventing a short circuit between the wirings. There is no reduction in breakdown voltage.

  Thus, in order to form the concave pattern 7 having the barrier film 8 on the surface, in the step of embedding the trench 6 with a Cu-based conductor having Cu as the maximum component, the concave pattern is covered with a plating prevention film and electrolytic plating is performed. Just do it. In addition, it is desirable that a Cu-based conductor is formed in the region between the concave patterns 7 adjacent to each other without providing a plating prevention film, thereby improving the uniformity of the plating film thickness.

  The application of the recess pattern for promoting polishing accompanying the rewiring structure is not limited to a single semiconductor device, but a pseudo-chip in which a plurality of semiconductor chips having at least one characteristic different from others are integrated by a resin mold. It is also applicable to SOC. Furthermore, it is also provided on a multilayer circuit board.

  Next, with reference to FIGS. 3 to 7, the manufacturing process of the semiconductor device of Example 1 of the present invention will be described. First, as shown in FIG. 3A, an external connection land 22 is provided on the surface of an LSI chip 21 in which elements are formed, and is covered with a cover film 23 made of SiN.

  Next, as shown in FIG. 3B, after the Cu post 24 is formed by selective plating, a resin insulating film 25 made of polyimide resin is provided, and the top surface of the Cu post 24 is exposed. Next, as shown in FIG. 4 (c), a photosensitive insulating resin WPR-1201 (product model number manufactured by JSR) is applied over the entire surface so that the thickness after post-baking is 6 to 7 μm. A film 26 is formed.

  Next, as shown in FIG. 4D, the trench 27 is formed by exposure and development so that the minimum line width is 5 μm. At this time, a recess pattern 28 for promoting polishing is simultaneously formed in a region where wiring is sparse. Here, a gap of 15 μm is provided so that the distance between the trench 27 and the recess pattern 28 is at least twice the depth of the trench 27. The planar shape of the concave pattern 28 is a square of 15 μm × 15 μm, and the interval between the concave patterns 28 adjacent to each other is 30 μm.

  Next, curing is performed at 200 ° C. for 1 hour to make the photosensitive resin insulating film 26 into a permanent insulating film 29. At this time, since the interval between the trench 27 and the recess pattern 28 is 15 μm, the shape of the trench 27 is not pulled and distorted by the recess pattern 28, and the width is 5 μm and the height is 5.5 to 6.5 μm. A trench 27 is formed.

  Next, as shown in FIG. 5E, by using a sputtering method, a Ti film 30 having a thickness of 30 nm to 200 nm is used as an adhesion layer / barrier film, and a Cu film 31 having a thickness of 30 nm to 200 nm is used as a plating seed layer. Are sequentially formed. Here, the thickness of the Ti film 30 and the Cu film 31 is 50 nm and 100 nm.

  Next, as shown in FIG. 5 (f), a plating prevention film 32 is formed using a resist so as to cover the concave pattern 28. At this time, in order to make the thickness of the plating layer to be formed uniform, the Cu film 31 is exposed without providing the plating prevention film 32 between the adjacent recess patterns 28.

  Next, as shown in FIG. 6G, a Cu plating film 33 having a thickness of 10 μm or more is deposited by electrolytic plating to completely fill the trench 27.

  Next, as shown in FIG. 6 (h), after removing the plating prevention film 32, CMP is performed using only Cu slurry HS-3C935 (Hitachi Chemical Co., Ltd. product model number) until the thickness of the permanent insulating film 29 becomes 5 μm. As a result, the embedded wiring 34 having a rectangular cross section with a minimum wiring interval of 5 μm and a wiring height of 5 μm is formed. FIG. 7 is an explanatory diagram of the semiconductor device immediately after the CMP, FIG. 7A is a conceptual plan view, and FIG. 7B is along the alternate long and short dash line connecting AA ′ in FIG. It is a conceptual sectional view. At this time, since the recess pattern 28 becomes a polishing promoting pattern, no barrier film residue remains on the surface of the flat portion in the region where the embedded wiring 34 is sparse.

  As described above, in the first embodiment of the present invention, since the concave pattern for promoting polishing is provided in a region where wiring is sparse, the polishing is sufficiently performed in the region where wiring is sparse, and the barrier film residue Does not occur, thereby preventing a short circuit between wires and a decrease in breakdown voltage.

  Next, the pseudo SOC of the second embodiment of the present invention will be described with reference to FIG. 8. Since the process of forming the wiring and the polishing promoting pattern is the same as that of the first embodiment, here, after the rewiring is formed. Only the sectional view of the pseudo SOC is shown.

Figure 8 is a schematic cross-sectional view of a pseudo-SOC according to the second embodiment of the present invention, first, on the support substrate (not shown), a plurality of different types of semiconductor chips which form a connection land 42 _{1-42 3} 41 _{1 to} 41 ₃ are attached and molded with the mold resin 43. Here, the semiconductor chips 41 _{1 to} 41 ₃ are assumed to be a CPU, a sensor, and a memory, respectively.

After peeling from the support substrate, Cu posts 44 are formed on the connecting lands 42 _{1 to} 42 ₃ , and then covered with a resin insulating film 45 from polyimide resin, and the top surfaces of the Cu posts 44 are exposed. Thereafter, similarly to the first embodiment, after applying a photosensitive insulating film that will eventually become the permanent insulating film 51, exposure and development are performed to form a trench and a recess pattern 52 for promoting polishing. Next, after being embedded with a Cu plating film via the adhesion layer 53 and the plating seed layer 54, the embedded wiring 55 is formed by planarization by a CMP method.

  Next, a photosensitive insulating film that will eventually become a permanent insulating film 56 is applied again, and then exposed and developed to form a via hole. Next, after filling with a Cu plating film via the adhesion layer 58 and the plating seed layer 59, the plug 60 is formed by planarization by CMP. At this time, a recess pattern 57 for promoting polishing may be provided in a region where the plug is sparse.

  Next, after a photosensitive insulating film that will eventually become a permanent insulating film 61 is applied, exposure and development are performed to form trenches and a recess pattern 62 for promoting polishing. Next, after embedding with a Cu plating film via the adhesion layer 63 and the plating seed layer 64, the buried wiring 65 is formed by flattening by a CMP method. Such a process is repeated as many times as necessary.

  Next, a photosensitive insulating film that will eventually become a permanent insulating film 66 is applied, and then exposed and developed to form via holes. Next, after filling with a Cu plating film through the adhesion layer 67 and the plating seed layer 68, the plug 69 is formed by flattening by a CMP method. Finally, a pad 70 is formed, and a solder resist 71 is provided around the pad 70 to complete the pseudo SOC.

  As described above, in the second embodiment of the present invention, when the pseudo-SOC rewiring structure is formed, the concave pattern for promoting polishing is provided, so that a short circuit between the embedded wirings can be prevented. Further, it is not necessary to provide a polishing stopper.

Here, the following supplementary notes are attached to the embodiments of the present invention including Example 1 and Example 2.
It possesses (Supplementary Note 1) and the semiconductor substrate in which elements are formed, and the buried wiring formed on the surface of the semiconductor substrate, the recess pattern barrier film on the buried wiring surface sparse regions are formed, A semiconductor device , wherein a metal other than the barrier film is not embedded in the recess pattern .
(Additional remark 2) The planar shape of the said recessed part pattern is either a rectangle or circular shape, and the short side of the said rectangle or the short axis length of a circular shape is 3 times or more of the minimum wiring width of the said embedded wiring. The semiconductor device according to appendix 1, wherein:
(Additional remark 3) The semiconductor device of Additional remark 1 or Additional remark 2 characterized by the density of the said recessed part pattern being 10% thru | or 100% of the maximum density part of the wiring formed with the said minimum wiring width. (Additional remark 4) The insulating layer which provides the recessed part which forms the said recessed part pattern and the said embedded wiring is a resin layer, and the space | interval of the said recessed pattern and the said embedded wiring is more than twice the height of the said embedded wiring. 4. The semiconductor device according to any one of appendix 1 to appendix 3, wherein the semiconductor device is provided.
(Supplementary Note 5 ) A plurality of semiconductor chips of at least one type in which elements are formed, a resin layer that molds and integrates the plurality of semiconductor chips, and the plurality of semiconductors formed on the surface of the semiconductor chip A semiconductor device comprising: embedded wiring for electrically connecting chips; and a recess pattern having a barrier film formed on a surface in a region where the embedded wiring is sparse.
(Appendix 6 ) A step of forming an insulating layer on a semiconductor substrate on which an element and an external connection land are formed, a trench for forming an embedded wiring at least in the insulating layer, and a recess in a region where the density of the trench is low A step of forming a pattern, a step of forming a barrier film and a plating seed layer on the exposed surface including the trench and the recess pattern, and plating a Cu-based conductor having Cu as a maximum component at least in a region excluding the recess pattern And selectively embedding the trench to form a buried wiring by removing unnecessary portions of the Cu-based conductor, plating seed layer, and barrier film by polishing. A method of manufacturing a semiconductor device.
(Supplementary note 7 ) The method for manufacturing a semiconductor device according to supplementary note 6 , wherein in the step of filling the trench, the Cu-based conductor is formed between the recess patterns adjacent to each other.
(Supplementary note 8 ) The method of manufacturing a semiconductor device according to supplementary note 6 or appendix 7 , wherein an interval between the concave pattern and the embedded wiring is at least twice the height of the embedded wiring.
(Supplementary Note 9 ) A step of molding a plurality of semiconductor chips of at least one different type formed with an element with resin, a step of forming an insulating film on the surface of the plurality of semiconductor chips and resin, and the insulating film A trench for forming an embedded wiring that electrically connects at least the plurality of semiconductor chips, a step of forming a concave pattern in a region where the density of the trench is low, and an exposed surface including the trench and the concave pattern A step of forming a barrier film and a plating seed layer, and a step of selectively depositing a Cu-based conductor containing Cu as a maximum component in a region excluding at least the recess pattern by a plating method to completely fill the trench. And a step of forming an embedded wiring by removing unnecessary portions of the Cu-based conductor, plating seed layer and barrier film by polishing. A method for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 External connection land 3 Cover film 4 Connection post 5 Insulation layer 6 Trench 7 Recess pattern 8 Barrier film 9 Embedded wiring 21 LSI chip 22 External connection land 23 Cover film 24 Cu post 25 Resin insulation film 26 Photosensitivity Resin insulation film 27 Trench 28 Recess pattern 29 Permanent insulation film 30 Ti film 31 Cu film 32 Plating prevention film 33 Cu plating film 34 Embedded wiring 41 _{1 to} 41 ₃ Semiconductor chip 42 _{1 to} 42 ₃ Connection land 43 Mold resin 44 Cu Post 45 Resin insulating film 51, 56, 61, 66 Permanent insulating film 52, 57, 62 Recess pattern 53, 58, 63, 67 Adhesion layer 54, 59, 64, 68 Plating seed layer 55, 65 Embedded wiring 60, 69 Plug 70 Pad 71 Solder resist 81 Resin layer 82, 83 Wiring 84 Resin layer 85 Polishing stopper film 86 Wrench 87 hole 88 via 89 embedded wiring 91 connecting post 92 resin layer 93 permanent insulating film 94 barrier film 95 buried wiring 96 barrier Makuzan渣

Claims (5)

A semiconductor substrate on which an element is formed;
Embedded wiring formed on the surface of the semiconductor substrate;
Wherein a said barrier layer on the surface the buried wiring sparse areas have a concave pattern is formed, a metal other than the barrier layer in the recess pattern is not embedded. The planar shape of the concave pattern is either rectangular or circular,
2. The semiconductor device according to claim 1, wherein the short side of the rectangle or the short axis of the circular shape is at least three times the minimum wiring width of the embedded wiring.   3. The semiconductor device according to claim 1, wherein a density of the recess pattern is 10% to 100% of a maximum density portion of a wiring formed with the minimum wiring width. The insulating layer for providing the recess pattern and the recess for forming the embedded wiring is a resin layer, and the interval between the recess pattern and the embedded wiring is at least twice the height of the embedded wiring. The semiconductor device according to any one of claims 1 to 3. Forming an insulating film on the semiconductor substrate on which the element and the external connection land are formed;
Forming at least a trench for forming an embedded wiring in the insulating film, and forming a recess pattern in a region where the density of the trench is low;
Forming a barrier film and a plating seed layer on an exposed surface including the trench and the recess pattern;
A step of selectively embedding a Cu-based conductor having Cu as a maximum component in a region excluding at least the concave pattern by a plating method to completely fill the trench;
And a step of removing unnecessary portions of the Cu-based conductor, plating seed layer and barrier film by polishing to form a buried wiring.

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