JP6364762B2 - Manufacturing method of electronic device - Google Patents

Description

  The present invention relates to a method for manufacturing an electronic device.

  2. Description of the Related Art A semiconductor device is used in which a semiconductor element such as a logic circuit IC or a memory element is connected through a TSV chip having a via penetrating a silicon substrate, that is, a TSV (Through Silicon Via).

  As a method of forming a TSV chip, it is known that a via hole is formed in a silicon substrate, a metal is formed therein, the metal on the silicon wafer is removed, and the metal remaining in the via hole is used as a via. It has been. Also, a structure is known in which a cavity is provided around one end of each of a plurality of vias (through plugs). Also known is a structure that reinforces the via by filling the cavity with resin.

  As another method for forming a TSV chip, for example, the following method is known. First, a recess is provided in a silicon substrate, and after an insulating film is embedded in the recess, a plurality of through holes are formed in the insulating film. Thereafter, the conductive film is embedded in the plurality of through holes, and the conductive film formed on the insulating film protruding from the plurality of holes is removed by polishing or the like, whereby the conductive film left in the plurality of holes Is a columnar through plug. Furthermore, a method of polishing the back surface of the silicon substrate to expose the lower end of the through plug and adjusting the thickness thereof is known.

JP 2013-138088 A JP 2010-267805 A JP 2012-209449 A

  Since the silicon substrate that penetrates the through plug is in contact with the through plug through the conductive and thin oxide film, the high-speed transmission characteristic of the signal flowing through the through plug is poor. Further, in the structure in which a cavity is formed around one end of each of the plurality of through plugs as described above, since the silicon substrate exists between the through plugs, it is necessary to further improve the high-speed transmission characteristics. Further, by forming through plugs in the mold resin instead of the silicon substrate, it is possible to lower the conductivity between the through plugs. It is also conceivable to use an insulating glass substrate instead of the semiconductor-containing substrate.

  However, an insulating substrate such as mold resin or glass is not sufficiently matured, so it is difficult to increase the density of the through plugs compared to a silicon substrate. In addition, since these insulating substrates are more fragile than silicon substrates, they may be damaged by stress applied when both surfaces of the substrate are polished, leading to a decrease in yield.

  An object of the present invention is to provide a method for manufacturing an electronic device having high transmission characteristics and high density vias.

According to one aspect of this embodiment, by etching the first surface side of the semiconductor substrate which is formed through a plurality of vias is in the thickness direction, you hollowing between the plurality of vias each other first a step that form a recess, said burying the first buried insulating film before Symbol first recess formed in the semiconductor substrate, and grinding the exposed surface of the first buried insulating layer of the plurality via Forming a second recess that cavitates the plurality of vias on the side opposite to the first recess by exposing the first end surface of the semiconductor substrate and etching the second surface side of the semiconductor substrate. Leaving the semiconductor substrate in a shape surrounding the first recess and the second recess, embedding a second buried insulating film in the second recess, and grinding an exposed surface of the second buried insulating film. have a, a step of exposing the second end surface of said plurality of vias Te The method of manufacturing an electronic device, characterized in Rukoto is provided.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to this embodiment, vias having high-speed transmission characteristics can be formed with high density.

FIG. 1 is a plan view illustrating an example of a semiconductor wafer used in the method for manufacturing an electronic device according to the embodiment, FIG. 1B is a partially enlarged plan view of FIG. 1A, and FIG. FIG. 2 is a partially enlarged plan view of FIG. 2A to 2D are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the first embodiment. 3A to 3D are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the first embodiment. FIG. 4 is a cross-sectional view showing a modification of the electronic device manufacturing method according to the first embodiment. 5A and 5B are cross-sectional views illustrating another example of the electronic device manufacturing method according to the first embodiment. 6A to 6C are cross-sectional views illustrating a second modification of the method for manufacturing an electronic device according to the first embodiment. 7A to 7C are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the second embodiment. 8A to 8D are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the second embodiment. 9A to 9C are cross-sectional views illustrating another example of the electronic device manufacturing method according to the second embodiment. FIGS. 10A to 10D are cross-sectional views illustrating an example of an electronic device manufacturing method according to the third embodiment. 11A to 11D are cross-sectional views illustrating an example of an electronic device manufacturing method according to the third embodiment. 12A to 12D are cross-sectional views showing a modification of the electronic device manufacturing method according to the third embodiment. Figure 13 (a), (b) is a cross-sectional view showing another modification of the method of manufacturing an electronic device according to a third embodiment. FIG. 14 is a cross-sectional view showing another modification of the method for manufacturing an electronic device according to the second and third embodiments.

  Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
FIG. 1A is a plan view showing an example of a semiconductor wafer used for manufacturing an electronic device according to the first embodiment, FIG. 1B is a partially enlarged plan view of FIG. c) is a partially enlarged plan view of FIG. 2 and 3 are cross-sectional views illustrating the process for forming the semiconductor device according to this embodiment.

  First, as illustrated in FIG. 1A, a plurality of via formation regions 3 are partitioned vertically and horizontally through a dicing line 2 on the plane of a silicon wafer 1 that is a single crystal semiconductor wafer. For example, the plane of the via formation region 3 is set to a quadrangle whose side is about 1 cm.

  As shown in FIGS. 1B and 1C, a plurality of via holes 4 are formed vertically and horizontally in each via formation region 3 in the thickness direction. A conductive via (through plug) 5 formed of a material is embedded. Each via 5 has a diameter of, for example, about 50 μm and a pitch of, for example, about 50 μm to 200 μm. For example, a silicon oxide film 6 is formed as an insulating film between the inner surface of the via hole 4 and the via 5.

The formation method of the via hole 4, the via 5, and the silicon oxide film 6 is not particularly limited. For example, there is a method of forming a via hole 4 by forming a mask having a plurality of holes on the first surface (upper side in the drawing) of the silicon substrate 1 and then etching the silicon substrate 1 through the holes of the mask. Etching of the silicon substrate 1 is performed by, for example, a reactive ion etching (RIE) method using a Br-containing gas such as Br ₂ or HBr or a chlorine-based gas, and the via hole 4 formed thereby is formed at the beginning of the formation of silicon. The depth may be such that the substrate 1 does not penetrate.

The silicon oxide film 6 may be formed, for example, by thermally oxidizing the silicon substrate 1 from the inner surface of the via hole 4 or may be formed by CVD. In the space surrounded by the silicon oxide film 6 in the via hole 4, the conductive via 5 is formed by embedding a conductive material such as copper or tungsten. As a method for embedding the conductive material, a method using both sputtering and plating, a CVD method, or the like is employed. Further, unnecessary conductive material and the like formed on the first surface of the silicon substrate 1 are removed by, for example, a chemical mechanical polishing (CMP) method. Further, the second surface of the silicon substrate 1 is polished by the CMP method, thereby exposing the end surface of the via 6, and adjusting the silicon substrate 1 to have a target thickness, for example, about 400 μm to 600 μm. To do. Thus, a TSV structure is formed in each via formation region 3 of the silicon substrate 1.

Of the silicon substrate 1 through which a plurality of vias 5 are penetrated, the via formation region 3 and its periphery have a cross-sectional structure as illustrated in FIG. 2A, and silicon oxide is formed on the first and second surfaces of the silicon substrate 1. A film 11 is formed.

  Next, as illustrated in FIG. 2B, the silicon oxide film 11 on the first surface of the silicon substrate 1 and the first end surface of the via 5 are polished and planarized by the CMP method, and then the first surface is formed. Then, a silicon oxide film and a silicon nitride film are sequentially formed as the insulating film 12. The silicon oxide film and the silicon nitride film are formed by, for example, a CVD method. Thereafter, a photoresist is applied on the insulating film 12 and subjected to exposure, development, and the like to form a resist pattern 13. The resist pattern 13 has an opening 13 a that exposes the entire assembly region of the plurality of vias 5 in each of the via formation regions 3, and has a planar shape that covers the peripheral portion of the via formation region 3 and the surrounding dicing lines 2. Have.

  Next, as illustrated in FIG. 2C, the insulating film 12 exposed from the opening 13a of the resist pattern 13 is etched to form the opening 12a. In this case, the etching of the silicon nitride film is performed through, for example, hot phosphoric acid through the opening 13 a of the resist pattern 13. Thus, the silicon oxide film is further etched, for example, with buffered hydrofluoric acid through the opening formed in the silicon nitride film.

Next, as illustrated in FIG. 2D, the silicon substrate 1 is etched using the resist pattern 13 and the insulating film 12 as a mask to form a recess 1 u in the via formation region 3. Thereby, in the recess 1u, the silicon between the vias 5 is removed to form a cavity , and the first end portions of the plurality of vias 5 surrounded by the silicon oxide film 6 appear. Etching of the silicon substrate 1 is performed, for example, by dry etching such as RIE using a chlorine-based gas or wet etching using KOH, tetramethylammonium hydroxide (TMAH), or the like. The etching may be performed by a combination of dry etching and wet etching.

Next, the remaining resist pattern 13 on the silicon substrate 1 is removed. In this case, the silicon nitride film of the insulating film 12 may be removed by hot phosphoric acid or left. Further, as illustrated in FIG. 3A, a buried insulating film 14 is formed in the recess 1 u on the first surface side of the silicon substrate 1, thereby covering the via 5 and the silicon oxide film 6. As the buried insulating film 14, for example, a low-k organic insulating film such as polyimide or organic SOG, or an inorganic insulating film such as a silicon oxide film is formed. As a method for forming the insulating film 14, a coating method, a CVD method, or the like is employed.

Further, the buried insulating film 14 is polished by, for example, a CMP method and removed from the first surface of the silicon substrate 1, and the first end face of the via 5 is exposed, and the buried insulating film 14 is planarized. If on the silicon substrate 1 a silicon nitride film of the insulating film 12 is left also removed by polishing the silicon nitride film. At the time of polishing, the base of the via 5, that is, the second end portion is supported by the silicon substrate 1, so that the rigidity of the first end portion of the via 5 against the stress applied during polishing is increased. Thereby, the first surface side of the buried insulating film 14 between the vias 5 is hardly damaged by polishing. As the insulating film 6 on the inner surface of the hole 4, for example, when a silicon oxide film is formed by thermal oxidation of the silicon substrate 1, the mass density and hardness are higher than those of the silicon oxide film formed by the CVD method.

  Next, using a dicing saw (not shown), the silicon substrate 1 is cut along the dicing line 2, and the via forming region 3 is divided into chips as illustrated in FIG. 15 is formed.

  Thereafter, as illustrated in FIG. 3C, the side surface and the second surface excluding the first surface of the through via chip 15 are embedded in an insulating sealing resin film 16, for example, an epoxy resin. The insulating sealing resin film 16 seals the semiconductor chip together with the through via chip 15 as will be described later. The insulating sealing resin film 16 is molded using, for example, an injection molding apparatus.

  Further, as shown in FIG. 3D, the insulating sealing resin film 16 is ground from the back surface, that is, the second surface side by a CMP method or the like. Further, the silicon oxide film 11 on the exposed second surface of the silicon substrate 1 is ground, and then the silicon substrate 1, the via 5 and the like are ground from the lower surface to expose the second surface of the insulating sealing resin film 16. Let Thus, the electronic device 10 having a structure in which the silicon substrate 1 remains in a ring shape and the outer periphery thereof is covered with the insulating sealing resin film 16 is formed.

  In the above embodiment, after the plurality of vias 5 penetrating the silicon substrate 1 are formed, the recess 1u is formed in the via forming region 3 of the silicon substrate 1 while leaving the peripheral edge portion thereof. The first end face and the surrounding silicon oxide film 6 are exposed. Further, after the buried insulating film 14 is formed in the recess 1u, the first end face of the via 5 is exposed, and then the silicon substrate 1 is divided into the via formation regions 3 to form the through via chips 15. Further, after covering the second surface and the side surface of the through via chip 15 with the insulating sealing resin film 16, the insulating sealing resin film 16 is polished from the second surface side, and the silicon substrate 1 of the through via chip 15 is further polished. The electronic device 10 is formed by grinding and removing. The electronic device 10 has a structure in which the outer peripheral surface of the buried insulating film 14 filling between the plurality of vias 5 is annularly surrounded by the silicon substrate 1, and the plurality of vias 5 penetrating the buried insulating film 14. The first end face and the second end face are exposed from the buried insulating film 14.

  As a result, the vias 5 can be formed in the insulating film with the same density as the silicon substrate 1, and the high-speed transmission characteristics of signals passing through the vias 5 can be improved. Further, as shown in FIG. 3A, when the buried insulating film 14 formed of a resin material or the like more brittle than the silicon substrate 1 is ground from the outside, the root of the via 5, that is, the second end portion is silicon. Since it is firmly fixed to the substrate 1, it is resistant to impact during grinding and the embedded insulating film 14 is less likely to be damaged. Further, when the insulating sealing resin film 16, the silicon substrate 1, and the via 5 are polished to expose the second surface of the embedded insulating film 14, the via 5 is just before the embedded insulating film 14 is exposed. 1 is supported. Therefore, the buried insulating film 14 is not easily damaged during polishing. When the insulating sealing resin film 16 and the silicon substrate 1 are ground, as shown in FIG. 4, even if the silicon substrate 1 is left as thin as about several μm, for example, the high-speed transmission characteristics are hardly deteriorated. The annular silicon substrate 1 left around the buried insulating film 14 after grinding may be used as an electric shield by containing impurities.

  When the through via chip 15 is embedded in the insulating sealing resin film 16, the upper surfaces of the semiconductor chips 17a and 17b are exposed in the insulating sealing resin film 16 as illustrated in FIG. Alternatively, a pseudo wafer may be embedded. Then, as illustrated in FIG. 5B, the insulating sealing resin film 16 and the silicon substrate 1 are ground from the lower surface (second surface) side by, for example, a grinding method or a CMP method, and the buried insulating film 14 is Two surfaces are exposed and the electronic device 10 is very good. A semiconductor circuit is formed in the semiconductor chips 17a and 17b, and electrode pads 18a and 18b connected to the semiconductor circuit are formed on their upper surfaces.

  In this structure, the electrode pads 18a and 18b on the upper surfaces of the semiconductor chips 17a and 17b and the upper end surfaces of the vias 5 may be electrically connected by bonding with gold wires (not shown), or a photosensitive insulating film is used. A rewiring layer may be formed. As a result, the electrical connection of the semiconductor circuits in the semiconductor chips 17a and 17b can be drawn down via the via 5.

  By the way, the semiconductor device may be formed by mounting the semiconductor chips 17 a and 17 b on the through via chip 15. In this case, the electrode pads 18a and 18b of the semiconductor chips 17a and 17b are connected to the first end face of the via 5 of the through via chip 15 via solder bumps (not shown) or the like.

  Incidentally, in the step of forming the electronic device 10, as illustrated in FIG. 6A, the first surface and the side surface of the through via chip 15 may be covered with the insulating sealing resin film 16. In this case, as illustrated in FIG. 6B, the insulating sealing resin film 16 is ground on the first surface side, and the first end surface of the silicon substrate 1 and the via 5 at the peripheral portion of the through via chip 15. To expose. Thereafter, as illustrated in FIG. 6C, the second surface side of the silicon oxide film 11, the silicon substrate 1, and the via 5 is ground to form the same structure as that in FIG. Even in such a method, similarly to the above, the density of the plurality of vias 5 formed in the insulating film 14 can be increased, and the annular silicon substrate 1 and the insulating sealing resin are surrounded around the through via chip 15. It may be surrounded by a film 16.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing a method for forming an electronic device according to the second embodiment of the present invention. In FIG. 7, the second surface of the silicon substrate 1 is shown facing upward.
First, as shown in FIG. 2 above, after forming the recess 1u on the first surface side of the silicon substrate 1 through which the plurality of vias 5 are penetrated, the embedded insulating film 14 is embedded in the recess 1u and further embedded. The embedded insulating film 14 is ground to expose the first surface side of the silicon substrate 1. In the present embodiment, the buried insulating film 14 described in the first embodiment is used as a first buried insulating film.

  Next, as illustrated in FIG. 7A, the silicon oxide film 11 on the second surface of the silicon substrate 1 is removed by, for example, hydrofluoric acid. Thereafter, an insulating film 22 is formed on the second surface of the silicon substrate 1. As the insulating film 22, for example, a silicon oxide film and a silicon nitride film are sequentially formed by a CVD method. Further, a photoresist is applied on the insulating film 22, and a resist pattern 23 is formed by exposing and developing the photoresist. In the resist pattern 23, an opening 23a is formed at a position on the opposite side of the recess 1u in the silicon substrate 1.

  Next, as illustrated in FIG. 7B, the insulating film 22 is etched through the opening 23 a of the resist pattern 23 to form the opening 22 a. Of the insulating film 22, the silicon nitride film is etched by, for example, RIE, and the silicon oxide film is etched by, for example, buffered hydrofluoric acid. Thereafter, as illustrated in FIG. 7C, the patterned insulating film 22 and resist pattern 23 are used as a mask, and the silicon substrate 1 is etched from the second surface side through the openings 22a and 23a to form the bottom of the recess 1u. Silicon is removed to form a recess 1a that becomes an opening. As an etching method of the silicon substrate 1, the dry etching method and the wet etching method shown in the first embodiment are employed. Thereby, the first buried insulating film 14 is exposed from the second surface side of the silicon substrate 1. Thereafter, the resist pattern 23 and the insulating film 22 are sequentially removed.

  Next, the second buried insulating film 24 is buried in the cavity in the recess 1 a on the second surface side of the silicon substrate 1. The second buried insulating film 24 is formed by the same material and method as the buried insulating film 14 shown in the first embodiment. Thereafter, as illustrated in FIG. 8A, the second buried insulating film 24 is ground by CMP or the like to expose the second surface of the silicon substrate 1 and to expose the second end surface of the via 5. And further flatten their surfaces.

  Next, using a dicing saw (not shown), the silicon substrate 1 is cut along the dicing line 2 to divide the via formation region 3 into chips as illustrated in FIG. 25 is formed. 8B to 8D show the first surface of the silicon substrate 1 facing upward.

  Thereafter, as illustrated in FIG. 8C, the side surface and the second surface excluding the first surface of the through via chip 25 are embedded in the insulating sealing resin film 16. The insulating sealing resin film 16 is made of, for example, an epoxy resin.

  Further, as shown in FIG. 8D, the insulating sealing resin film 16 is ground from the second surface side by a CMP method or the like to expose the second buried insulating film 24. As a result, an electronic device having a structure in which the first and second buried insulating films 14 and 24 through which the plurality of vias 5 penetrate is surrounded by the silicon substrate 1 and the insulating sealing resin film 16 from the side surface is completed. The insulating sealing resin film 16 may be embedded with the semiconductor chips 17a and 17b shown in FIG.

  In the present embodiment, after forming a plurality of vias 5 penetrating the silicon substrate 1, a recess 1 u is formed on the first surface side of the via formation region 3 of the silicon substrate 1, whereby the first of the plurality of vias 5 is formed. The periphery of the edge is exposed. Further, after the first buried insulating film 14 is buried in the recess 1u and the first end face of the via 5 is exposed, the portion of the silicon substrate 1 remaining on the side opposite to the recess 1u is removed, and the silicon A recess 1 a serving as an opening is formed in the via formation region 3 of the substrate 1. Thereafter, the second embedded insulating film 24 is embedded in the space in the recess 1a from the second surface side of the silicon substrate 1, and the silicon substrate 1 is further divided into via formation regions 3 to form through via chips 25. Yes. Further, after embedding the second surface and the side periphery of the penetrating via chip 25 in the insulating sealing resin film 16, the insulating sealing resin film 16 is polished from the second surface side to form the electronic device 20. . The electronic device 20 has a structure in which the side surface is surrounded by the insulating sealing resin 16, and further has a structure in which the via 5 penetrates the first and second insulating films 14 and 24.

  Thus, in the through via chip 25 through which the plurality of vias 5 penetrate in the first and second buried insulating films 14 and 24, a plurality of density can be formed in the silicon substrate 1 as in the first embodiment. Vias 5 can be formed. Such high-density vias 5 are formed in the buried insulating films 14 and 24 having a dielectric constant lower than that of silicon, so that high-speed transmission characteristics of signals passing through the vias 5 can be improved. Further, it can be used as an electric shield surrounding the via 5 by the annular recon substrate 1.

  Moreover, the base of the via 5 is supported by the silicon substrate 1 when the exposed surface of the first buried insulating film 14 buried in the recess 1 u around the first end of the via 5 is polished. For this reason, when the first buried insulating film 14 is formed from a resin material or the like that is easily damaged by grinding, the first buried insulating film 14 is reinforced by the via 5. The buried insulating film 14 is less likely to be damaged during grinding.

  By the way, as shown in FIG. 3C of the first embodiment, a recess 1u is formed on the first surface of the silicon substrate 1 through which the via 5 penetrates, and the silicon substrate is filled with the first buried insulating film 14. 1 may be divided for each via formation region 3, and the second buried insulating film 24 may be buried by the method shown in FIG. 9 after the division.

  That is, after forming a structure similar to that shown in FIG. 3C, the insulating sealing resin film 16 and the silicon oxide film 11 on the second surface side of the silicon substrate 1 are removed by grinding, etching, etc. The silicon substrate 1 is exposed as shown in FIG. Thereafter, a mask 19 such as a photoresist is formed on the insulating sealing resin film 16 and the second surface side of the silicon substrate 1. The mask has an opening formed on the side opposite to the recess 1u. Further, as illustrated in FIG. 9B, the silicon substrate 1 in a region opposite to the concave portion 1u is removed by etching to form a concave portion 1a serving as an opening. After that, the second buried insulating film 24 is buried in the cavity of the concave portion 1a on the side opposite to the first buried insulating film 14 in the concave portion 1u on the first surface side, and further illustrated in FIG. 9C. As described above, the second embedded insulating film 24 is ground to expose the second end of the via 5, thereby forming the electronic device 20.

This method also makes it possible to increase the density of the vias 5 penetrating the substrate-like buried insulating films 14 and 24 as described above. 6A and 6B, after covering the first surface of the through via chip 15 with the insulating sealing resin 16, the insulating resin film 16 on the first surface side is ground, Furthermore, the structure shown in FIG. 9B may be formed by grinding and etching the silicon oxide film 11 and the silicon substrate 1 on the second surface side.

  In the present embodiment, the semiconductor device may be formed by embedding the semiconductor chips 17 a and 17 b in the insulating sealing resin film 16 around the through via substrate 25 as in the first embodiment. Alternatively, the semiconductor chips 17a and 17b may be mounted on the through via substrate 25 to form a semiconductor device.

(Third embodiment)
10 and 11 are cross-sectional views illustrating a method for forming an electronic device according to a third embodiment of the present invention. 10 (a), 10 (b), 11 (c), and 10 (d) show a state in which the first surface of the silicon substrate 1 faces upward, and FIGS. 11 (a), (b) shows a state in which the second surface is directed upward.

  First, the structure shown in FIG. 2D is formed according to the method described in the first embodiment. That is, the recess 1u is formed in the via formation region 3 of the silicon substrate 1 through which the plurality of vias 5 penetrate. Thereafter, as illustrated in FIG. 10A, for example, a silicon nitride film as a coating inorganic insulating film 31 on the first surface of the silicon substrate 1, the inner surface of the recess 1 u, the upper surface of the via 5, and the insulating film 6. Is formed to a thickness of about several tens of nm to several μm, for example.

  Next, the structure shown in FIG. 10B is formed. That is, the first buried insulating film 14 is formed on the covering inorganic insulating film 31, thereby filling the first buried insulating film 14 in the recess 1 u and covering the via 5. Thereafter, the first buried insulating film 14 and the covering inorganic insulating film 31 are polished by a CMP method or the like to expose the first surface of the silicon substrate 1 and the first end surface of the via 5.

  Next, as illustrated in FIG. 10C, after removing the silicon oxide film 11 on the second surface of the silicon substrate 1 with hydrofluoric acid or the like, an insulating film 32 is formed on the second surface. As the insulating film 32, for example, a silicon oxide film and a silicon nitride film are sequentially formed by a CVD method. Further, a photoresist is coated on the insulating film 32, and a resist pattern 33 is formed by exposing and developing the photoresist. The resist pattern 33 has an opening 33a on the second surface side of the silicon substrate 1 at a position opposite to the recess 1u.

  Next, steps required until a structure illustrated in FIG. First, the insulating film 32 is etched through the opening 33a of the resist pattern 33 to form the opening 32a. As a method of forming the opening 32a, for example, a method similar to the method of forming the opening 22a in the insulating film 22 shown in FIG. 7B of the second embodiment is employed.

  Thereafter, using the patterned insulating film 32 and the resist pattern 33 as a mask, the silicon substrate 1 is etched through the openings 32a and 33a to remove the bottom of the recess 1u, thereby forming the recess 1a serving as the opening, and coating inorganic The second surface of the insulating film 31 is exposed. As an etching method of the silicon substrate 1, the dry etching method and the wet etching method shown in the first embodiment are employed. In this case, the covering inorganic insulating film 31 exposed from the second surface side of the silicon substrate 1 may function as an etching stop layer. Thereafter, the resist pattern 33 and the insulating film 32 are sequentially removed.

  Next, as illustrated in FIG. 11A, a second buried insulating film 34 is formed on the second surface of the silicon substrate 1 and in the concave portion 1a on the second surface side, and the second buried insulating film 34 is formed. The via 5 is embedded by the insulating film 34. The second buried insulating film 34 is formed by the same material and method as the buried insulating film 14 shown in the first embodiment. Thereafter, the silicon substrate 1 is cut along the dicing line 2 shown in FIG. 1, and the via formation region 3 is divided into chips as illustrated in FIG. 11B, thereby forming the through via chip 35.

  Thereafter, as illustrated in FIG. 11C, the first embedded insulating film 14 of the through via chip 35 and the first end surface of the via 5 are exposed, and the side surface of the silicon substrate 1 and the second embedded insulating film are exposed. The exposed surface of the film 3 is embedded in the insulating sealing resin film 16.

  Next, as shown in FIG. 11D, the insulating sealing resin film 16 is ground from the second surface side by, for example, a CMP method to expose the second buried insulating film 34. Further, the second buried insulating film 34 is ground by a CMP method or the like to expose the second end face of the via 5, and the first and second buried insulating films 14 and 34, the silicon substrate 1, etc. are formed in a desired manner. Make it thick. As a result, the electronic device 30 having a structure in which the first and second buried insulating films 14 and 34 through which the plurality of vias 5 penetrate is surrounded by the annular silicon substrate 1 from the side surface is formed.

  By the way, as a method for forming the electronic device 30, the method illustrated in FIGS. First, after the structure shown in FIG. 10D is formed, the via formation region 3 is divided into chips as shown in FIG. 12A, and the through via chip 35 is formed.

  Thereafter, as illustrated in FIG. 12B, the side surface and the second surface excluding the first surface of the through via chip 35 are embedded in the insulating sealing resin film 16. Next, as shown in FIG. 12C, the insulating sealing resin film 16 is ground from its lower surface by a CMP method or the like, then the silicon oxide film 11 is ground, and the second end face of the via 5 is polished. .

  Next, the peripheral portion of the second surface of the chip-like silicon substrate 1 is covered with a mask (not shown) such as a resist, and a plurality of vias 5 are exposed from one opening of the mask. Further, the silicon oxide film 11 and the silicon substrate 1 exposed from the opening of the mask are removed by etching to form a recess 1a serving as an opening on the side opposite to the recess 1u8 on the first surface side. The silicon substrate 1 is etched by the etching method shown in the first embodiment, for example, a wet etching method. Thus, as shown in FIG. 12D, the covering inorganic insulating film 31 and the second end of the via 5 are exposed through the recess 1a. As a result, the silicon substrate 1 is left in an annular shape around the set of the plurality of vias 5.

  Next, as shown in FIG. 13A, a second embedded insulating film 34 is formed on the second surface of the silicon substrate 1, the covering inorganic insulating film 31 and the insulating sealing insulating film 16, The recess 1a on the second surface side is embedded. The second buried insulating film 34 is formed by the same material and the same method as the buried insulating film 14 shown in the first embodiment.

  Next, as shown in FIG. 13B, the second buried insulating film 34 is ground from the second surface side of the silicon substrate 1 by CMP or the like to expose the sealing insulating film 16 and the silicon substrate 1. The electronic device 30 is formed.

  In this embodiment, after a plurality of vias 5 penetrating the silicon substrate 1 are formed, a recess 1u is formed in the via formation region 3 of the silicon substrate 1 leaving the peripheral edge thereof, and a plurality of vias 5 are formed from one recess 1u. The first end and the periphery thereof are exposed. Further, before the first embedded insulating film 14 is embedded in the recess 1 u, the covering insulating film 31 is formed around the inner surface of the recess 1 u and the via 5. Further, by grinding the covering insulating film 31 and the first buried insulating film 14, the first end face of the via 5 is exposed and then left on the bottom of the recess 1 u on the first face side of the silicon substrate 1. Silicon is removed and a recess 1 a is formed on the second surface side of the silicon substrate 1. In the step of removing the silicon substrate 1 at the bottom of the recess 1u, the covering insulating film 31 may function as an etch stop layer, thereby preventing the first buried insulating film 14 from being damaged.

  Accordingly, in the structure in which the plurality of vias 5 penetrate through the first and second buried insulating films 14 and 34 that overlap each other, the plurality of vias 5 having a density that can be formed by the silicon substrate 1 can be formed. . Therefore, the high-speed transmission characteristic of the signal passing through the via 5 can be improved. Since the first and second buried insulating films 14 and 34 through which the via 5 penetrates and the covering insulating film 31 have a laminated structure, the dielectric constant can be adjusted by changing their insulating materials. .

  In addition, when the exposed surface of the first buried insulating film 14 buried around the first end portion of the via 5 is polished, the base of the via 5 is supported by the silicon substrate 1. The rigidity with respect to the stress received during polishing of the film 14 is increased and the film 14 is less likely to be damaged.

  In the present embodiment, as in the first embodiment, the electronic device 30 having a structure in which the semiconductor chips 17a and 17b are embedded in the insulating sealing resin film 16 may be formed. Similarly to the first embodiment, the semiconductor chip 17a, 17b may be mounted on the through via chip 35 to form a semiconductor device as the electronic device 30.

By the way, in the second and third embodiments, as illustrated in FIG. 14, when the silicon substrate 1 on the back side of the first embedded insulating film 14 embedded in the recess 1 u of the silicon substrate 1 is retracted. The recess 1a may be formed on the second surface side while leaving the silicon 1d thin. In this case, the second buried insulating films 24 and 34 are buried in the recess 1a .

  By the way, in said 1st-3rd embodiment, the silicon oxide film 6 which covers the outer peripheral surface of the via | veer 5 may be removed in the exposed state. The silicon substrate 1 may or may not contain n-type or p-type impurities. The buried insulating films 14, 24, and 34 may have a laminated structure of insulating films made of different materials.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, an embodiment of the present invention will be additionally described.
(Additional remark 1) By etching the semiconductor substrate in which a plurality of vias are formed penetrating in the thickness direction, the first concave portion on the first surface side and the second surface side on which the plurality of vias are hollowed out are etched. Forming at least one of the second recesses, embedding a buried insulating film in the first and second recesses formed on the semiconductor substrate, and exposing an exposed surface of the buried insulating film. And a step of grinding to expose end surfaces of the plurality of vias.
(Appendix 2) Step of exposing the end faces of the plurality of vias by grinding the buried insulating film after the buried insulating film is buried in the first recess of the semiconductor substrate, and the semiconductor substrate 2. The method of manufacturing an electronic device according to claim 1, further comprising: exposing a bottom surface of the buried insulating film by retreating the second insulating film from the second surface side.
(Supplementary note 3) The method of manufacturing an electronic device according to supplementary note 2, wherein the second surface of the semiconductor substrate is retracted together with the plurality of vias, and the second surface is flattened.
(Appendix 4) After exposing the end surfaces of the plurality of vias from the buried insulating film and before exposing the bottom surface of the buried insulating film, the semiconductor substrate ( 4. The method of manufacturing an electronic device according to appendix 3, which includes a step of converting 1) into a chip.
(Supplementary Note 5) A step of embedding any one of the second surface and the exposed surface of the embedded insulating film and a side surface of the semiconductor substrate formed into a chip into a sealing insulating film, and the second surface side of the semiconductor substrate And the step of exposing both the buried insulating film and the semiconductor substrate except for the side surfaces of the semiconductor substrate by grinding the sealing insulating film before grinding the sealing insulating film. 5. A method for producing an electronic device according to 4.
(Supplementary note 6) The manufacturing of an electronic device according to Supplementary note 2 or 5, wherein the semiconductor substrate in a region opposite to the first concave portion is retracted to form the second concave portion. Method.
(Additional remark 7) It has the process of forming the said semiconductor substrate into the shape which includes the said embedded insulating film after forming the said embedded insulating film in the said 2nd recessed part formed in the said semiconductor substrate. The manufacturing method of the electronic device of Claim 6.
(Supplementary Note 8) A step of embedding the buried insulating film on the periphery of the chip-shaped semiconductor substrate and on the second surface side in a sealing insulating film, and the buried insulating material on the sealing insulating film and the second surface side And a step of grinding the film continuously to expose the end face of the via and leaving the buried insulating film around the semiconductor substrate. Production method.
(Supplementary note 9) The method for manufacturing an electronic device according to any one of supplementary notes 1 to 8, wherein the embedded insulation is formed of at least one of an organic material and an inorganic material.
(Additional remark 10) Before forming the said embedded insulating film in an said 1st recessed part with an organic material, it has the process of forming an inorganic insulating film in the inner surface of the said 1st recessed part, The additional notes 1 thru | or 8 characterized by the above-mentioned. The manufacturing method of the electronic device as described in any one of these.
(Supplementary Note 11) The electronic device according to Supplementary Note 5 or 8, wherein a semiconductor circuit chip is embedded in the sealing insulating film.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Dicing line 3 Via formation area 4 Via hole 5 Via 6 Insulating film 9 Semiconductor device 10, 20, 30 TSV substrate 11 Silicon oxide film 12 Insulating film 13 Resist pattern 14, 24, 34 Embedded insulating film
15, 25, 35 Through-via chip 16 Insulating sealing resin film 17a, 17b Semiconductor chip 18a, 18b Electrode 22, 32 Insulating film 23, 33 Resist pattern 31 Covering insulating film

Claims (5)

Etching a first surface side of a semiconductor substrate formed with a plurality of vias penetrating in the thickness direction, thereby forming a first recess that cavitates the plurality of vias;
Burying a first buried insulating film in the first recess formed in the semiconductor substrate;
Grinding an exposed surface of the first buried insulating film to expose first end surfaces of the plurality of vias;
By etching the second surface side of the semiconductor substrate, a second recess that cavitates the plurality of vias is formed on the side opposite to the first recess, and the first recess and the second recess are formed. Leaving the semiconductor substrate in a surrounding shape;
Burying a second buried insulating film in the second recess;
Grinding an exposed surface of the second buried insulating film to expose second end surfaces of the plurality of vias;
A method for manufacturing an electronic device, comprising: Forming an insulating sealing resin film covering the side surface of the semiconductor substrate after forming the second embedded insulating film of the semiconductor substrate and before or after polishing the second embedded insulating film; The method of manufacturing an electronic device according to claim 1, comprising :   3. The method of manufacturing an electronic device according to claim 1, wherein in the step of forming the second recess, a part of the semiconductor substrate is left between the first recess and the second recess. . The semiconductor substrate manufacturing method of an electronic device according to any one of claims 1 to 3, characterized in that to leave the annular.   5. The method according to claim 1, further comprising: forming an inorganic insulating film on an inner surface of the first recess before forming the first embedded insulating film in the first recess using an organic material. The manufacturing method of the electronic device of any one of these.

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