JP6082243B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot gaming machine, and more particularly to control processing of a sound-related effect operation in the gaming machine.

Japanese Patent No. 4828491

  In pachinko machines, slot machines, etc., it is possible to play games by lighting / flashing operations using light emitting parts using LEDs (Light Emitting Diodes), sound output from speakers, and driving of movable objects on the game board. There are those that perform accompanying effects, or perform error notification, guidance display, etc. by lighting / flashing operation of the light emitting unit or sound output by a speaker.

  As for the sound-related production operation, for example, a microcomputer functioning as a production control unit instructs a sound source IC (Integrated Circuit) to reproduce a phrase, thereby realizing reproduction output of various sounds.

  Patent Document 1 discloses a configuration for performing sound-related effect control in a gaming machine.

In the gaming machine, various presentation control, error control, and the like are performed in addition to the control of the original game operation. For this reason, the control load of the microcomputer tends to increase.
Therefore, an object of the present invention is to reduce the control load of a production control microcomputer or the like.

The gaming machine of the present invention is a gaming machine that executes at least sound-related effect operations accompanying a game, and includes sound source playback means capable of simultaneously reproducing a phrase of a plurality of channels, and the progress of the effect operation to be performed. Production control means for controlling the reproduction operation of the sound source reproduction means based on the presentation progress data to be expressed.
In the production progress data, a channel for registering sound-related data is predetermined for each sound type, and at least two of the sound types are accompanied by output of the sound. The sound source reproduction means reproduces the designated phrase at a volume based on the designated first volume and second volume for each channel, and the production progress data is , Including phrase reproduction instruction information for instructing the reproduction of a phrase, wherein the first volume is described in the phrase reproduction instruction information in the performance progress data, and the volume of the phrase instructed to reproduce by the phrase reproduction instruction information The second volume is reproduced by the production control means separately from the first volume. Being a steerable volume information to stage, the presentation control unit, when outputting the sound of the reliable classification into output sound of low the reliability type, the reliability in which Ru is mute the sound of low the reliability classification by instructing said tone reproduction means so as to lower the second volume of the channel is being output sounds low type.

In the above-mentioned present invention, in the gaming machine in which the sound source reproducing means is configured to be capable of simultaneously reproducing a phrase of a plurality of channels, for each type of sound, a channel for registering sound-related data for the sound is determined in advance. Become.
For this reason, it is uniquely determined that a certain type of sound is reproduced on a certain channel.
In sound-related production control, the sound being played is controlled in order to instruct the sound source playing means to change the volume of the sound (phrase) being played, or to apply a sound effect such as fade-in playback / fade-out playback. Sound control information (sound control information) is used, but it is uniquely determined that a certain type of sound is reproduced on a certain channel as described above, so that the sound control information on the sound to be controlled Is not required to search for a channel that is reproducing the sound to be controlled. That is, the control content for the control target sound is registered by registering the control content information in a channel uniquely determined for the control target sound without searching for the channel in which the control target sound is being reproduced. Can be appropriately instructed to the sound source reproduction means.

In the present invention, at least two of the sound types are classified according to the reliability of the effect operation accompanied by the output of the sound. As a result, sound control can be individually performed for sounds with different degrees of reliability , and therefore sound priority control according to the reliability of the effects can be realized.

  In the present invention, the number of channels for registering the sound-related data is determined to be two or more for at least one of the sound types. Thereby, it is possible to instruct the sound source reproduction unit to reproduce two types of phrases simultaneously with respect to at least one kind of sound, and therefore, stereo reproduction can be realized with respect to at least one kind of sound.

  As described above, according to the present invention, the control load related to the rendering operation can be reduced.

1 is a perspective view of a pachinko gaming machine according to an embodiment of the present invention. It is a front view of the board surface of the pachinko game machine of an embodiment. It is a block diagram of a control configuration of the pachinko gaming machine of the embodiment. 3 is a block diagram of a connection configuration of a driver unit according to the first embodiment. FIG. It is a block diagram of an example of an internal configuration of a driver unit according to the first embodiment. It is a flowchart of the main control main process of an embodiment. It is a flowchart of the main control timer interruption process of an embodiment. It is a flowchart of an effect control main process of the embodiment. It is a flowchart of 1 ms timer interruption processing of effect control of an embodiment. It is a flowchart of the command analysis process in presentation control of an embodiment. It is a flowchart of the command corresponding | compatible process in presentation control of embodiment. It is a flowchart of the scenario registration process in presentation control of an embodiment. It is a flowchart of the scenario deletion process in presentation control of an embodiment. It is a flowchart of the scenario update process in presentation control of an embodiment. It is a flowchart of the subscenario update process in presentation control of an embodiment. It is explanatory drawing of scenario registration information, lamp data registration information, and motor data registration information of embodiment. It is explanatory drawing of the sound data registration information of embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub scenario table of embodiment. It is a flowchart of the LED drive data update process in presentation control of an embodiment. It is explanatory drawing of the registration information of the lamp data of embodiment. It is explanatory drawing of the address table of the lamp data and mask data of embodiment. It is explanatory drawing of the lamp data table and mask data table of embodiment. It is a flowchart of the registration process of the sound of embodiment. It is a flowchart of the setting process of SE of embodiment. It is a flowchart of the setting process of sound control of an embodiment. It is explanatory drawing about the data structure of the information of the sound control of embodiment. It is explanatory drawing about the conversion process of fade-type sound control information. It is explanatory drawing about the usage example of the information of fade type sound control. It is explanatory drawing about the example of control which mutes a predetermined kind of sound with a secondary volume. It is a flowchart of sound reproduction processing of an embodiment. It is explanatory drawing about the volume control according to error generation.

Hereinafter, a pachinko gaming machine will be exemplified as an embodiment of a gaming machine according to the present invention, and will be described in the following order.
<1. Pachinko machine structure>
<2. Control configuration of pachinko gaming machine and driver configuration of embodiment>
<3. Processing of main control unit>
<4. Processing of production control unit>
[4-1: Main processing]
[4-2: 1ms timer interrupt processing]
[4-3: Command analysis processing]
[4-4: Scenario registration / deletion processing]
[4-5: Scenario update processing]
[4-6: LED drive data update process]
[4-7: Sound registration processing]
[4-8: Sound reproduction processing]
<5. Summary and Modification>

<1. Pachinko machine structure>

First, with reference to FIG. 1 and FIG. 2, the structure of the pachinko gaming machine 1 as an embodiment of the present invention will be schematically described.
FIG. 1 is a front perspective view showing the appearance of a pachinko gaming machine 1 according to the embodiment, and FIG. 2 is a front view of the game board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” includes a front frame 2, an outer frame 2, a glass door 5, and an operation panel 7 described below. The “game board part” comprises the game board 3 of FIG. In the following description, “frame part” and “frame side” are a general term for the front frame 2, the outer frame 2, the glass door 5, and the operation panel 7. “Board” and “board side” indicate the game board 3.

As shown in FIG. 1, the pachinko gaming machine 1 has a frame-shaped front frame 2 attached to the front surface of a wooden outer frame 4 so as to be opened and closed. Although not shown, a game board storage frame is formed on the rear surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the gaming area 3a formed on the surface of the gaming board 3 faces the front side of the gaming machine in FIG.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player on the front side through the transparent glass.

The glass door 5 is attached to the front frame 2 by a shaft support mechanism 6 so as to be opened and closed. Then, by operating a door lock release key cylinder (not shown) provided at a predetermined position of the glass door 5, the glass door 5 is unlocked from the front frame 2, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock releasing key cylinder.
On the front side of the glass door 5, decorative lamps 20w are provided in various places as light emitting means on the frame side. The decorative lamp 20w performs, for example, a light emitting operation for effects, a light emitting operation for error notification, and a light emitting operation according to an operation state as a light emitting operation by an LED.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper tray unit 8, a lower tray unit 9, and a firing operation handle 10.

The upper tray unit 8 is formed with an upper tray 8a for storing game balls to be used as bullets. The lower tray unit 9 is formed with a lower tray 9a that stores game balls that cannot be stored in the upper tray 8a.
The upper tray unit 8 is provided with a ball removal button 16 for removing the game balls stored in the upper tray 8a toward the lower tray 9a. The lower tray unit 9 is provided with a ball removal lever 17 for pulling out the game balls stored in the lower tray 9a to the lower side of the gaming machine.
The upper tray unit 8 has a ball lending button 14 for requesting a game ball lending device (not shown) and a card for requesting return of a valuable medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with a patrol switch 11, an effect button 12, and a cross key 13. The patrol light switch 11 and the effect button 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input reception period and can be changed when the built-in lamp is turned on. Further, the cross key 13 is an operator for the player to perform an operation for an operation or an effect setting according to the effect situation.

The firing operation handle 10 is provided on the right end side of the operation panel 7 and is an operator for operating the launching device 32 shown in FIG.
In addition, speakers 25 that sound production effects are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

  Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin board. The game board 3 is provided with a ball guide rail 31 for guiding the launched game ball in a ring shape as a board surface partition member, and a substantially circular area surrounded by the ball guide rail 31 is a game area 3a. It has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided at a substantially central portion of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of the effect control unit 51, which will be described later, for example, three decorative symbols of left, middle and right are displayed in a variable manner on the background image. Various effect images such as a normal effect, a reach effect, and a super reach effect are also displayed. Similarly, the sub liquid crystal display device 32S performs display according to various effects.

A center decoration 35C is provided in the game area 3a so as to surround the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exhibits a decorative effect due to its design, but also has an action of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Furthermore, the center decoration 35C also functions as a member that enables the right and left shots of the flow path of the game ball depending on the strength or stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left hit, the game ball flows down the left game area 3b, and in the case of right hit, the game ball flows down the right game area 3c.

In addition, a lower left decoration 35L is provided below the left game area 3b to exhibit a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c, which exhibits a decorative effect and defines a range as the left game area 3b.
In the game area 3a (the left game area 3b and the right game area 3c), nails 49 and windmills 47 are provided at various places to form various flow paths for game balls.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exhibits a decorative effect and functions as a play area for a game ball.
Although not shown in the drawing, the center ornament 35C is provided with a movable body accessory that provides a visual effect in an appropriate place.

In the vicinity of the upper right edge of the game area 3a, a symbol display unit 33 is provided by a dot display formed by arranging a plurality of LEDs.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the normal symbol are displayed. Each variation display operation (variation display operation for setting variation start and variation stop as one set) is performed.
The main liquid crystal display device 32M described above variably displays the decorative symbol by the image in time synchronization with the variable display of the first and second special symbols by the symbol display unit 33.

A winning device having an upper start port 41 (first special symbol start port) is provided below the center ornament 35C, and a lower start port 42a (second special symbol start port) is further provided below that. A variable winning device 42 is provided.
Inside the upper start opening 41 and the lower start opening 42a, detection sensors (upper start opening sensor 71 and lower start opening sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

  The upper starting port 41 is a winning port related to the starting condition of the variable display operation of the first special symbol in the symbol display unit 33, and does not have a starting port opening / closing means (means for opening or expanding the starting port). It is a type winning device.

The normal variation winning device 42 having the lower starting port 42a is configured as a winning rate variation type winning device capable of changing the winning rate of the game ball at the starting port by the starting port opening / closing means. That is, it is a so-called electric tulip type winning device including a pair of left and right movable blades (movable members) 42b that can open or enlarge the lower start port 42a.
The lower start opening 42 a of the normal variation winning device 42 is a winning opening related to the start condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower start port 42a varies depending on the operating state of the movable blade piece 42b. That is, it is configured such that winning is easy when the movable blade piece 42b is open, and winning is difficult or impossible when the movable blade piece 42b is closed.

In addition, a plurality of general winning ports 43 are provided on the left and right sides of the normal variation winning device 42. A detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of the game ball is formed inside each general winning opening 42.
In addition, a normal symbol start port 44 including a gate (specific passage region) through which a game ball can pass is provided on the lower side of the right game region 3c. The normal symbol starting port 44 is a winning port related to a normal symbol variation display operation in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed in the normal symbol starting port 44. Has been.

A first special variable winning device 45 (special electric accessory) is provided along the flow path from the normal symbol starting port 44 to the normal variable winning device 42 in the right game area 3c.
The first special variable winning device 45 is configured to close / open the first big winning opening 45a by a retractable opening door 45b. In addition, a sensor for detecting the passage of the game ball to the first big prize opening 45a (the first big prize port sensor 75 in FIG. 3) is formed inside.
The lower right decoration 35R bulges from the surface of the game board 3 around the first grand prize winning opening 45a, and the upper side of the bulged portion and the upper surface of the open door 45b guide downstream of the right flow path 3c. Forming part. Therefore, when the open door 45b is drawn into the board, the game ball that has reached the downstream guide portion can easily enter the first big prize opening 45.

A second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 is configured to close / open the second large winning port 46a on the inside by an open door 46b that is pivotally supported at the lower part and can be opened and closed. In addition, a sensor (second big prize port sensor 76 in FIG. 3) for detecting the passage of the game ball to the second big prize port 46a is formed inside.
The second big prize opening 46a is opened by opening the open door 46b. In this state, the game balls that have flowed down the left game area 3b or the right game area 3c will enter the second big prize opening 50 with a high probability.

As described above, the upper starting port 41, the lower starting port 42a, the normal symbol starting port 44, the first large winning port 45a, the second large winning port 46a, and the general winning port 43 are formed in the game area of the board as winning ports. Has been.
In the pachinko gaming machine 1 according to the present embodiment, when a winning is made to a winning port other than the normal symbol starting port 44 among these winning ports, per winning ball set for each winning port. The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the upper start opening 41 and the lower start opening 42a are set to three, the first big winning opening 45a and the second big winning opening 46a are set to 13, the general winning opening 43 is set to 10 and the like.
Note that the game balls that have not won the prize holes are discharged from the game area 3 a through the out port 48.
Here, “winning” means that the winning opening takes the game ball inside, or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated that a “winning” has occurred in that winning opening. The game ball related to the winning is also referred to as “winning ball”.

On the board as described above, the center ornament 35C, the lower left ornament 35L, the lower right ornament 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and a movable object not shown in the figure. Although not shown in detail, decorative lamps 20b are provided as light emitting means on the panel side at various places.
The decorative lamp 20b performs, for example, a light emitting operation for effects, a light emitting operation for error notification, and a light emitting operation according to the operation state as a light emitting operation by an LED.

<2. Control configuration of pachinko gaming machine and driver configuration of embodiment>

Next, the configuration of the control system of the pachinko gaming machine 1 according to the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment mainly has a main control board 50, an effect control board 51, a liquid crystal control board 52, a payout control board 53, a launch control board 54, and a power supply board 58 as the boards forming the control configuration. Is provided.

The main control board 50 is equipped with a microcomputer or the like, and performs overall control related to the entire game operation of the pachinko gaming machine 1. In the following description, a component of the main control board 50 including a microcomputer mounted on the main control board 50 is referred to as a “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, and receives an effect control command from the main control unit 50 and performs control for executing various effect operations using image display, light emission, and sound output. Hereinafter, the structure of the effect control board 51 including the microcomputer mounted on the effect control board 51 is referred to as an “effect control unit 51”.

The liquid crystal control board 52 is equipped with a microcomputer, a video processor, etc., and receives display control commands from the effect control unit 51 to control display operations by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
Note that the main liquid crystal control substrate and the sub liquid crystal control substrate may be provided independently as the liquid crystal control substrate for controlling the display operation by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The payout control board 53 performs payout control of prize balls by the game ball payout device 55 connected to the pachinko gaming machine 1.
The launch control board 54 controls the launch operation of the game ball by the launch device 56 provided in the player's pachinko gaming machine 1.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC 24 V), and supplies an operation power supply voltage Vcc to each unit. The power supply path is not shown.

First, the main controller 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor incorporating a CPU 100 (hereinafter referred to as “main control CPU 100”), a ROM 101 (hereinafter referred to as “main control ROM 101”), and a RAM 102 (hereinafter referred to as “main control RAM 102”). A microcomputer is configured.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main control unit 50 includes an interface circuit with each unit, a random number generation circuit that generates random numbers for lottery related to special symbol variation display, a CTC (Counter Timer Circuit) for various time counting, An interrupt controller circuit for giving an interrupt signal to the control CPU 100 is also provided.

As described above, the main control unit 50 receives each winning means in the game area on the board (upper start port 41, lower start port 42a, normal symbol start port 44, first big win port 45a, second big win port 46a, general It is configured to receive a detection signal of a sensor provided in the winning opening 43).
That is, the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76 are sent to the main control unit 50. Supplied.
These sensors (71 to 76) are configured by detection switches that detect a game ball that has entered, but specifically, contactless switches such as photoswitches and proximity switches, and contact points such as microswitches. It can consist of switches.

  The main control unit 50 receives the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Depending on the process. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, and the like are performed.

The main control unit 50 is connected to a normal electric accessory solenoid 77 that opens and closes the movable wing piece 42b of the lower start port 42, and the main control unit 50 transmits a control signal according to the progress of the game to perform normal electric operation. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable blade piece 42b is executed.
Further, the main control unit 50 has a first grand prize opening solenoid 78 that opens and closes the opening door 45b of the first big prize opening 45 and a second big prize that opens and closes the opening door 46b of the second big prize opening 46. A mouth solenoid 79 is connected. The main control unit 50 drives and controls the first big prize opening solenoid 78 or the second big prize opening solenoid 79 in accordance with the so-called jackpot situation, and opens the first big prize opening 45 or the second big prize opening 46. Is executed.

  In addition, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LED OFF / ON / flashing). Thereby, the display operation in the 1st special symbol display part 80 in the symbol display part 33, the 2nd special symbol display part 81, and the normal symbol display part 82 is performed.

  The main control unit 50 is connected to a frame external terminal board 57. The main control unit 50 can transmit information related to game progress to a hall computer (not shown) via the frame external terminal board 57. The information related to the game progress is information such as jackpot winning information, prize ball number information, symbol variation display execution number information, and the like. The hall computer is a management computer that comprehensively manages pachinko hall gaming machines, and is installed outside the gaming machine.

In addition, a payout control board 53 is connected to the main control unit 50. Connected to the payout control board 53 are a launch control board 54 for controlling the launch device 56 and a game ball payout device 55 for paying out game balls.
The main control unit 50 transmits a payout control command (payout control command for designating the number of prize balls) to the payout control board 53. The payout control board 53 controls the game ball payout device 55 in accordance with the control command to cause the game ball to be paid out.
The payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. The main controller 50 monitors whether or not the game ball payout device 55 is functioning normally based on this payout state signal. Specifically, it is monitored whether or not a problem such as a clogged ball or insufficient payout of a prize ball has occurred during a prize ball payout operation.

  The main control unit 50 transmits an effect control command including information related to the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an unauthorized signal due to an illegal act from the outside from being input to the main control unit 50 via the effect control unit 51.

Next, the production control unit 51 and its peripheral circuits will be described.
The effect control unit 51 includes a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). A microcomputer is configured.
The effect control CPU 200 performs arithmetic processing for various effect operations and controls each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 according to the present embodiment, the effect means is the main liquid crystal display device 32M, the sub liquid crystal display device 32S, the decorative lamps 20w and 20b, the speaker 59, and a movable object that is not shown.
The effect control ROM 201 stores a control program of the effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like.
Although illustration is omitted, the production control unit 51 gives an interrupt signal to the interface circuit with each unit, a random number generation circuit for generating random numbers for lottery for production, CTC for various time counting, and the production control CPU 200. It also has an interrupt controller circuit.
The main roles of the effect control unit 51 are to receive an effect control command from the main control unit 50, to select an effect based on the effect control command, and to provide an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. , Output sound control by the speaker 25, light emission control of the decorative lamps 20w and 20b (LED), operation control of the movable body accessory, and the like.

  The effect control unit 51 transmits an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S, and the effect control command is sent to the liquid crystal control substrate 52 via the liquid crystal interface substrate 66.

The liquid crystal control board 52 performs display control of the main liquid crystal display device 32M and the sub liquid crystal display device 32S. Although not shown, the liquid crystal control board 52 includes a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP performs overall control of video output processing such as image development processing and image drawing.
The image ROM stores image data (effect image data) on which the VDP performs image expansion processing.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area and a buffer memory.

  With these configurations, the liquid crystal control board 52 generates various image data based on the effect control command from the effect control board 51, and outputs it to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effect images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The production control unit 51 controls the light production and the sound production. For this reason, a frame driver unit 61, a panel driver unit 62, and a sound source IC (Integrated Circuit) 59 are connected to the effect control unit 51.
The frame driver unit 61 performs light emission driving for the LEDs of the decorative lamp unit 63 on the frame side. Note that the decorative lamp portion 63 is a general view of the decorative lamp 20w provided on the frame side as shown in FIG.
The panel driver unit 62 performs light emission driving for the LEDs of the decorative lamp unit 64 on the panel side. In addition, the decorative lamp part 64 is a general view of the decorative lamp 20b provided on the panel side as shown in FIG. In the case of the present embodiment, the panel driver unit 62 also drives the movable body accessory motor 65 that drives the movable body accessory formed on the board side. As the movable body accessory motor 65, for example, a stepping motor is used.

In the case of the present embodiment, the frame driver unit 61 is a first-system drive signal output unit, and the panel driver unit 62 is a second-system drive signal output unit. Although details will be described later with reference to FIG. 4, the effect control unit 51 (effect control CPU 200) uses the serial data transmission channels ch1 and ch2 to generate the drive signals for the first and second systems using the effect drive data as serial data. The output means (the frame driver unit 61 and the panel driver unit 62) is supplied.
In this example, the board driver unit 62 also drives the movable body accessory motor 65 that drives the movable body accessory formed on the board side. However, each LED of the decorative lamp unit 64 is driven to emit light. The driver unit and the driver unit that drives the movable body accessory motor 65 may be provided separately.

Further, the effect control unit 51 controls the sound source IC 59 so that the speaker 25 outputs a desired sound.
The sound source IC 59 mixes phrases of a plurality of channels (a sound channel aCH described later) to obtain a predetermined number (number of channels) of audio signals. As shown in FIG. 1, in the case of this example, since a plurality of speakers 25 are provided, the number of output channels of the sound source IC 59 can be, for example, two channels of Lch and Rch (stereo output). Through the above mixing, phrases of a plurality of channels instructed to be reproduced from the effect control unit 51 can be reproduced simultaneously.
The sound source IC 59 performs sound control for the phrase instructed as a control target in accordance with the instruction from the effect control unit 51. Specifically, the production control unit 51 gives information related to an instruction to give a sound effect such as a volume change instruction or fade-in reproduction / fade-out reproduction to the sound source IC 59, and the sound source IC 59 is designated as a control target according to the information. Controls playback of the phrase that is played.

The sound source IC 59 used in the present embodiment also has a SUB volume setting function and a pan function (left-right pan and up-down pan).
In this case, the sound source IC 59 requests an instruction to output a sound, at least “phrase number”, “primary volume”, “primary volume transition amount”, “secondary volume”, “number of loops”, “SUB0 volume”, “SUB1”. “Volume”, “Left / Right Panpot”, “Left / Right Panpot Transition”, “Up / Down Panpot”, and “Up / Down Panpot Transition” In other words, the sound source IC 59 in this case is provided with a register for each of the sound channels aCH that accepts the input of the indicated value for each of these items.
In the present embodiment, the SUB volume is not used. Accordingly, “0” is set in the registers of the “SUB0 volume” and “SUB1 volume” (see step S1202 in FIG. 31 described later).

The output audio signal from the sound source IC 59 is amplified by the amplifier unit 67 and then given to the speaker 25.
In FIG. 3, for the sake of illustration, the number of output channels of the sound source IC 59 is one. However, in reality, the amplifier unit 67 and the speaker 25 are provided with output channels corresponding to, for example, Lch and Rch, and stereo sound Playback is possible.

  In the above description, the sound source IC 59 is provided separately from the effect control board 51. However, the sound source IC 59 may be provided integrally on the same board as the effect control board 51.

The effect control unit 51 is connected to an operation unit 60 that can be operated by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 is the patrol switch 11, the effect button 12, the cross key 13, and the operation detection mechanism described above with reference to FIG.
The effect control unit 51 can perform various effect controls according to the operation detection signal from the operation unit 60.

  The production control unit 51 determines a production pattern by lottery or uniquely from a plurality of types of production patterns prepared in advance based on the production control command sent from the main control unit 50, and performs various productions at necessary timing. Control means. Thereby, the display of the effect image by the main / sub liquid crystal display devices 32M and 32S corresponding to the effect pattern, the sound reproduction from the speaker 25, the lighting and blinking driving of the LEDs in the decoration lamp parts 63 and 64 (decoration lamps 20w and 20b), Operation of the movable body accessory by the movable body accessory motor 65 is realized, and various production patterns are developed in time series. Thereby, the “production scenario” is realized.

The effect control command defines a function by a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, MODE Bit 7 is ON, and EVENT Bit 7 is OFF.
When these pieces of information are transmitted as valid, a strobe signal is output corresponding to each of the mode (MODE) and the event (EVENT). That is, when there is a command to be transmitted, the main control CPU 100 sets and outputs mode (MODE) information for transmitting the command to the effect control unit 51, and the first strobe signal after a predetermined time has elapsed from this setting. Send. Furthermore, event (EVENT) information is set and output after the elapse of a predetermined time from the transmission of the strobe signal, and the second time of the strobe signal is transmitted after the elapse of the predetermined time from this setting.
The strobe signal is controlled by the main control CPU 100 to be in an active state for a predetermined period during which the effect control CPU 200 can reliably receive a command.
The effect control unit 51 (effect control CPU 200) generates an interrupt based on the input of the strobe signal and executes a control program for command reception interrupt processing, and the effect control command is acquired in this interrupt processing. .

Then, the structure of the drive signal output means (the frame driver unit 61 and the panel driver unit 62) of the first system and the second system described above will be described.
FIG. 4 shows the frame driver unit 61 and the board driver unit 62 connected to the effect control unit 51.

In the frame driver unit 61 which is the first-system drive signal output means, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the effect control CPU 200.
As a signal line of the serial data output channel ch1, a reset signal line for supplying a reset signal RESET, a clock line for supplying a clock signal CLK, a data line for supplying serial data DATA as effect drive data, and an enable signal ENABLE are supplied. An enable signal line is provided. Each of these signal lines is connected so as to supply each signal in parallel to n LED drivers 90 constituting the frame driver unit 61.
In each LED driver 90 of the frame driver unit 61, a device ID used as a slave address by the effect control CPU 200 is set. That is, the identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of the LED drivers 90 are denoted as w1 to w (n) as illustrated.

In the panel driver unit 62 which is the second-system drive signal output means, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
Similarly to channel ch1, the signal line of serial data output channel ch2 is a reset signal line for supplying reset signal RESET, a clock line for supplying clock signal CLK, a data line for supplying serial data DATA as effect drive data, and an enable signal ENABLE. An enable signal line for supplying is provided. Each of these signal lines is connected so as to supply each signal in parallel to m LED drivers 90 constituting the panel driver unit 62.
In each LED driver 90 of the panel driver unit 62, a device ID (identifier of each LED driver 90) used as a slave address by the effect control CPU 200 is set. For the sake of explanation, the device ID (slave address) of each LED driver 90 is represented as b1 to b (m) as shown in the figure.

As each LED driver 90 in the frame driver unit 61 and the panel driver unit 62, for example, “LV5236V (manufactured by Sanyo Semiconductor Co., Ltd.)” which is a 24-channel LED driver can be used, and 24 current output terminals are provided. Therefore, one LED driver 90 can output a maximum of 24 LED drive currents. Specifically, for example, 8 series of R (red) LED drive current outputs, 8 series of G (green) LED drive current outputs, and 8 series of B (blue) LED drive current outputs, and light emission of 8 full-color LEDs. It can be driven. Here, one “series” means one LED connected to one current output terminal, or a group of a plurality of LEDs connected in series or in parallel to one current output terminal. pointing.
The number n of LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of decorative lamps 20w). Therefore, n may be 1 or may be 2 or more. The frame driver unit 61 has one or a plurality of LED drivers 90.
Further, the number m of LED drivers 90 in the panel driver unit 62 is determined by the number of LED series (the number of series of decorative lamps 20b) arranged on the panel side. Accordingly, m may be 1 or may be 2 or more. The panel driver unit 62 has one or a plurality of LED drivers 90.

FIG. 5A shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 91, an address setting unit 92, a data buffer / PWM controller 93, a D / A converter 94, and drive current source circuits 95-1 to 95-24.
The drive current source circuits 95-1 to 95-24 are current sources that perform the 24 series drive current outputs from the output terminals 96-1 to 96-24, respectively.

The LED driver 90 receives an enable signal ENABLE, a clock signal CLK, and serial data DATA from the effect control CPU 200 with respect to the serial bus interface 91. The serial bus interface 91 takes in the serial data DATA at the timing of the clock signal CLK during the period specified by the enable signal ENABLE. The serial bus interface 91 converts the captured serial data into parallel data and transfers the parallel data to the data buffer / PWM controller 93.
The effect control CPU 200 designates a slave address and transmits LED drive data.
The data buffer / PWM controller 93 performs slave address confirmation for the parallel data transferred from the serial bus interface 91. When it is confirmed that the slave address included in the parallel data matches the own slave address (either w1 to w (n) or b1 to b (m)) set in the address setting unit 92 The LED drive data included in the parallel data is stored as valid data in a designated register.

When the data buffer / PWM controller 93 fetches each series of LED drive data, the data buffer / PWM controller 93 uses the values corresponding to the luminance information (gradation values) indicated by the LED drive data as 24 series drive control values as D / A. Output to the converter 94.
The D / A converter 94 converts a value corresponding to the luminance information into an analog signal, which is used as a control signal to each of the current source circuits 95-1 to 95-24.

24 series of LEDs 120 are connected to all (or part of) the output terminals 96-1 to 96-24. Note that the drawing shows a simplified state in which one LED 120 is connected to one series of output terminals 96, but a configuration in which a plurality of LEDs are connected to one series of output terminals 96 (for example, series connection) is also possible. Of course this is possible.
In each series (output terminals 96-1 to 96-24), the power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. Current is supplied to each series of LEDs 120 by the current source circuits 95-1 to 95-24 to emit light.
That is, each of the current source circuits 95-1 to 95-24 operates so that a drive current having a current amount corresponding to the signal supplied from the D / A converter 94 flows through the corresponding series of LEDs 120.

Specifically, such LED drive control is described for one series. The data buffer / PWM controller 93 converts the digital data string corresponding to the pulse duty corresponding to the gradation value of the series to the D / A converter 94. The D / A converter 94 converts the digital data string into a pulse signal as an analog signal and supplies the pulse signal to the current source circuit 95 of the series. The output of the current source circuit 95 is controlled by the H / L of the pulse signal, and for example, outputs currents of 0 mA and 5 mA. For example, in such an operation, a driving current having an average current value corresponding to the gradation value flows to the LED 120 as a result.
In this embodiment, the current value is set to, for example, 0 mA and 5 mA by the PWM driving method, and gradation control is performed (integrally) in the time axis direction. not only, it is needless to say that in practice may be a current value is changed according to the gradation. Regardless of duty control or level control, appropriate gradation expression can be realized by setting the average current value per unit time to a level corresponding to the gradation.

In the case of the present embodiment, a movable body accessory motor 65 that drives the movable body accessory is connected to some of the LED drivers 90 in the panel driver unit 62. FIG. 5B shows an example in which, for example, the stepping motor 121 is connected to all (or a part) of the output terminals 96-1 to 96-24 of a certain LED driver 90. 5B shows only the portions of the output terminals 96-1 to 96-24, but the internal configuration of the LED driver 90 is the same as that of FIG. 5A.
For example, when the stepping motor 121 is a four-phase driving motor, the output terminals 96-1 to 96-4 are connected so that an excitation current for one stepping motor 121 flows. Similarly, output terminals 96-5 to 96-8, output terminals 96-9 to 96-12, output terminals 96-13 to 96-16, output terminals 96-17 to 96-20, and output terminals 96-21 to 96. -24 are connected so that an exciting current flows through one stepping motor 121. In this case, a maximum of six stepping motors 121 can be driven by one LED driver 90.
The LED driver 90 is a circuit that outputs a current indicated by a given command (serial data) from the output terminals 96-1 to 96-24. Can also be used. Therefore, some LED drivers 90 are used as drivers for the stepping motor 121 as shown in FIG. 5B. The operation of the movable body accessory is finely set according to the production scenario, and the production control unit 51 controls the driving direction, the driving amount, and the like accordingly. By driving the accessory, the movable object accessory can be controlled by serial data together with each decoration lamp (LED 20b) of the decoration lamp unit 64, and the control processing and configuration can be made efficient.
In one LED driver 90, a method may be adopted in which some output terminals are used for LED driving and other part of the output terminals are used for driving a stepping motor, a solenoid, or the like.

As described above, each LED driver 90 is driven so that each LED 120 emits light with a designated luminance in accordance with the serial data DATA received from the effect control CPU 200. Alternatively, a part of the LED driver 90 drives the stepping motor 121 according to the serial data DATA.
Each of the first and second system drive signal output means (frame driver unit 61, board driver unit 62) includes a plurality of LED drivers 90 each outputting a drive signal to one or a plurality of effect means, The serial data from the effect control unit 51 is transmitted in parallel to each LED driver 90 in one system. Each LED driver 90 acquires effect drive data (serial data) including its own ID (slave address).

<3. Processing of main control unit>

Hereinafter, control processing according to the present embodiment will be described. First, main processing by the main control unit (main control board) 50 will be described here.
FIG. 6 is a flowchart showing main processing of the main control unit 50. The main process starts when the power is turned on without operating the initialization switch (not shown), such as when recovering from a power failure, and when the initialization switch is turned on. May turn on. In any case, when the pachinko gaming machine 1 is powered on, the power board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts the main process shown in FIG.

In the main control side main process, the main control CPU 100 first executes a necessary initial setting process before starting the game operation in step S11. For example, it first sets itself to an interrupt disabled state, sets it to a predetermined interrupt mode (interrupt mode 2), and initializes register values in the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of a RAM clear signal that is an output signal of a RAM clear switch that is input via an input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize all the areas of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the store clerk of the pachinko parlor.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the process from step S12 to S16, and performs zero clear of the entire area of the RAM. Therefore, the value of the backup flag set at the time of power-off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a “RAM clear display command” for notifying that the RAM area has been cleared to zero to each control board as an initialization command. In step S18, for example, 30 seconds is stored in the RAM clear notification timer as a time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initializes a CTC that outputs an interrupt signal for starting a timer interrupt operation, and sets the CPU to an interrupt enabled state.
Thereafter, as the processing of steps S20, S21, and S22, the interrupt disabled state and the interrupt enabled state are repeated until an interrupt occurs, and various random number update processes are executed during that time. In the various random number update processing in step S21, random numbers used for changing initial values (start values) of various random numbers used for special symbol fluctuation display and normal symbol fluctuation display, and fluctuations used for selection of fluctuation patterns. Update pattern random numbers.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to jackpot lotteries circulating through a predetermined numerical range by increment processing (special symbol determination random numbers used for symbol lottery). Or a random number related to a lottery per assistance (a random number for judging per assistance used in winning lottery per assistance). The random numbers used for changing the initial value include an initial value random number for special symbol determination, an initial value random number for auxiliary hit determination, and the like.

The main control RAM 102 has a special symbol determination random number counter initial value generation counter and a special symbol determination random number counter as various random number counters used for symbol lottery related to jackpot lottery, auxiliary lottery, or variation pattern lottery. There are provided a counter for generating an initial value per auxiliary sub-counting counter, a random counter for sub-peripheral determining, a random number 1 counter for variation pattern, a random number 2 counter for variation pattern, and the like. These counters serve as random number generation means for generating random numbers in software.
In the various random number update processing in step S21, two initial value generation counters for generating initial values of the special symbol determination random number counter and the auxiliary hit determination random number counter, a variation pattern random number 1 counter, and a variation pattern random number 2 The counter is updated to generate the above various soft random numbers. For example, if the numerical value range that can be taken as the variation pattern random number 1 counter is 0 to 238, a value is acquired from the count value storage area for generating the value of the variation pattern random number 1 in the main control RAM 102, and the acquired value is After adding 1, it is stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. Other initial value generation random number counters are updated in the same manner. The CPU 201 is configured to repeatedly execute various random number update processes except during a timer interrupt process that is executed intermittently.

The above describes the case where it is determined in step S12 that the RAM clear switch is ON. Next, the case where the RAM clear switch is OFF will be described. For example, at the time of recovery from a power failure state, the initialization switch (RAM clear signal) is in an OFF state. In such a case, the main control CPU 100 advances the process from step S12 to S13, and determines the backup flag value. The backup flag is set to the ON state when the power is shut off, and is reset to the OFF state in the first timer interrupt processing after the power is restored.
Therefore, when the power is turned on or when recovering from a power failure, the backup flag should normally be in the ON state. However, the backup flag is reset (OFF) if the predetermined processing is not completed before the power is cut off for some reason. Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from step S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from step S13 to S14, and executes a checksum calculation for calculating a checksum value. Here, the checksum operation is an 8-bit addition operation for the work area of the main control RAM 102.
When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the main control RAM 102. This SUM address stores a checksum value obtained by the same checksum calculation when the power is shut off. The stored calculation result is maintained by the backup power source together with other data of the main control RAM 102. Therefore, originally, both should match according to the determination in step S14.
However, there may be a case where the checksum operation cannot be executed when the power is turned off, or even if it can be executed, the data in the work area is damaged after the checksum operation of the main process is executed. In such a case, the determination result in step S14 is inconsistent.
When data corruption is detected due to the discrepancy of the determination results, the main control CPU 100 proceeds to the processing from step S14 to S16, executes the RAM clear processing, and returns the operating state of the gaming machine to the initial state.

If the checksum value obtained by the checksum calculation in step S14 matches the stored value at the SUM address, the main control CPU 100 proceeds to step S15, and returns the stack pointer before power-off based on the backup data. A game restoration process necessary for starting a game from the processing state at the time of power-off is executed.
When the game recovery process at step S15 is completed, the process proceeds to the process at step S19, the CTC is initialized and the CPU is set in the interrupt enabled state, and thereafter, the interrupt disabled state and the interrupt enabled state are generated until an interrupt occurs. In the meantime, various random number update processes described above are executed (steps S20 to S22).

  Next, timer interrupt processing of the main control CPU 100 will be described. FIG. 7 shows the timer interrupt process of the main control CPU 100. This main control timer interrupt process is activated by interruption every predetermined time (about 4 ms) from the CTC, and is interrupted and executed during execution of the main process described above.

  When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and then first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 in step S51 of FIG. In this power abnormality check process, it is mainly monitored whether the power is normally supplied. Here, for example, when an abnormality such as a power interruption occurs, a backup process is performed in which predetermined game information at the time of power interruption is stored in the RAM so that the game can be restored without any trouble when the power is restored.

  In step S52, the main control CPU 100 performs a timer management process for managing a timer used for gaming operation control. Timer values of various timers (for example, special symbol accessory operation timer) used for game operation control of the pachinko gaming machine 1 are managed (updated) by this processing.

In step S53, the main control CPU 100 performs input management processing. In this input management process, information detected by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. Here, the detection information by the various sensors includes, for example, an upper start opening sensor 71, a lower start opening sensor 72, a gate sensor (normal pattern start opening sensor) 73, a first large winning opening sensor 75, and a second second winning opening sensor. 76, ON / OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74.
Through the processing in step S53, it is monitored for each interrupt whether or not a winning is detected (winning has occurred) at each winning opening. The “winning counter” is a counter provided corresponding to each winning opening and counting the number of game balls (winning balls) won. In the present embodiment, in a predetermined area of the main control RAM 102, an upper start opening winning counter for the upper starting opening 41, a lower starting opening winning counter for the lower starting opening 42a, a normal symbol starting opening winning counter for the gate 44, A first grand prize winning counter for the first grand prize winning opening 45a, a second big winning prize winning prize counter for the second big winning prize opening 46a, a general winning prize winning counter for the general winning opening 43, and the like are provided. .
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during a period in which the prize should be allowed. For example, when the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not being played, the prize detection information is invalidated by invalidating the prize detection information. In order to notify the outside of the fact, a predetermined error process is performed in an error management process in step S55 described later.

  In step S54, the main control CPU 100 performs a timer interrupt random number management process for periodically updating the random numbers related to each variation display. In this periodic random number update process, a special symbol determination random number or auxiliary per-subject determination random number is updated (+1 is added for each interrupt), and a process for changing the start value of the random number counter is performed each time the random number counter makes a round. For example, the value of the special symbol judgment random number counter is updated (added by +1) within a predetermined range, and the special symbol judgment random number counter initial value generation counter value is read each time the special symbol judgment random number counter makes one round. The value of the generation counter is stored in the special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the generation counter, so that the count value of the special symbol determination random number counter is random while the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring whether or not there is an abnormality in the gaming operation state. In this error management process, as abnormalities in the game operation state, these operational abnormalities (errors) occur, for example, by monitoring whether or not a break has occurred between the boards or whether or not there has been an illegal winning. If so, predetermined error processing corresponding to the error is performed.
As the error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation or a game ball launch operation) is stopped, or an error notification command is transmitted to the effect control unit 51 to generate the effect means. To notify that an error has occurred.

In step S56, the main control CPU 100 performs prize ball management processing. In this prize ball management process, the data stored in the input management process in step S53 is grasped, the above-mentioned prize counter is confirmed, and if there is a prize, a payout control command for designating the number of prize balls is issued. Transmit to the substrate 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation for the designated number of prize balls. Thereby, the number of winning balls corresponding to each winning opening is paid out. The number of winning balls corresponding to a winning opening is the predetermined number of winning balls per winning ball set for each winning opening × the number of winning balls corresponding to the value of the winning counter.

  In step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, a lottery per auxiliary in the normal symbol variation display is performed, and based on the lottery result, the variation pattern of the normal symbol and the stop display mode of the normal symbol are determined, or the blinking is repeated every predetermined time. Create symbol data (data for LED blinking display during normal symbol variation), or create data for stop display (data for LED blinking display during normal symbol stop display) if normal symbol is not varying Or

In step S <b> 58, the main control CPU 100 performs a normal electric accessory management process. In this ordinary electric accessory management process, generation of an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) based on the lottery result of the auxiliary symbol lottery in the normal symbol management process in step S57. Set up. Based on the data set here, an excitation signal is output to the ordinary electric utility solenoid 77 in a solenoid management process in step S64 described later, whereby the operation of the movable blade piece 42b is controlled.
In step S59, the main control CPU 100 performs special symbol management processing. In this special symbol management process, the big hit lottery in the special symbol variation display is mainly performed, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the start of variation), the special stop symbol, etc. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric utility management process, when the big hit lottery result is “big hit” or “small win”, a setting process necessary to execute and control the hit game corresponding to the win is performed.

In step S61, the main control CPU 100 performs a right-handed notification information management process. In this right-handed notification information management process, for example, a right-handed instruction is given in situations where right-handed is advantageous, such as when the first and second winning holes 45a and 46a are opened or when the movable blade piece 42b is driven. A process for making a “launch position guidance effect (right-handed notification effect)” for performing the notification appears. Specifically, the right-handed instruction is an effect operation instructing the player to aim at the right game area 3c. For example, an image prompting the player to “right-hand” is displayed on the main liquid crystal display device 32M. Or a right-handed message sound is generated from the speaker 25.
When a right-handed notification effect is performed, in this right-handed notification information management process, a “right-handed instruction command” instructing execution of a right-handed notification effect is transmitted to the effect control unit 51 as an effect control command. Then, the production control unit 51 performs execution control of right-handed notification using an image or sound.
In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol displays to the symbol display unit 33. By this processing, normal symbol and special symbol change display and stop display are performed. The normal symbol display data created in the normal symbol management process in step S57 and the special symbol display data created in the special symbol display data update process in the special symbol management process in step S59 are the LED management process. Is output.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operation state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operating state information includes that a big hit game has occurred (condition device has been activated), that a small hit game has occurred, that a symbol variation display has been executed (a special symbol variation display game has started or ended) , Information such as winning information (information indicating that the player has won a winning opening or a big winning opening and information on the number of winning balls) is included.
In step S64, the main control CPU 100 performs solenoid management processing. In this solenoid management process, an excitation signal output process for the ordinary electric accessory solenoid 77 based on the solenoid control data created in the ordinary electric accessory management process in step S58, or a special electric accessory management process in step S60. Excitation signal output processing for the first and second big prize opening solenoids 78 and 79 based on the solenoid control data is performed. Thereby, the movable wing piece 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start port 42a and the big winning ports 45a and 46b are opened and closed.

After completing the above steps S51 to S64, the main control CPU 100 restores the saved register contents and sets the interrupt permitted state in step S65. As a result, the timer interrupt process is ended, the process returns to the main process on the main control side in FIG. 6 before the interruption, and the main control main process is performed until the next timer interrupt occurs.

<4. Processing of production control unit>
[4-1: Main processing]

Then, the process of the production | presentation control part 51 is demonstrated. As the processing of the effect control unit 51, mainly processing performed every 16 ms on the main loop (hereinafter also referred to as “16 ms processing”) and interrupt processing performed every 1 ms (hereinafter referred to as “1 ms timer interrupt processing”). Say).
First, main processing including 16 ms processing will be described here.
FIG. 8 shows the main process of the effect control unit 51. The effect control unit 51 (effect control CPU 200) starts the main process of FIG. 8 when the gaming machine body is powered on.
In this main process, the effect control CPU 200 first performs a necessary initial setting process before starting the game operation in step S101. For example, as an initial setting process, command reception interrupt setting, movable object starting point return processing, CTC initial setting, timer interrupt permission, initial setting of CPU internal register values including each part of the microcomputer, and the like are performed.

When the initial setting process in step S101 is completed, the processes in steps S102 to S117 are repeated as a process during normal operation.
In other words, in this example, the effect control CPU 200 performs the ID check in step S102 and the random number update in step S117 every loop, and performs the processing of steps S105 to S116 (16 ms processing) every 16 ms.
In the ID check in step S102, the effect control CPU 200 confirms the ID of itself or each connected part set on the system. If an ID abnormality is detected for some reason, system stop processing is performed as step S103.
In normal times when there is no problem with the ID, the effect control CPU 200 performs the processing of step S104 and subsequent steps. That is, the effect control CPU 200 determines whether or not the value of the interrupt counter for determining whether to execute the 16 ms process is greater than “15”. This interrupt counter is a counter that is incremented in step S207 of the 1 ms timer interrupt process described later. Therefore, when the value of the interrupt counter is larger than “15”, it means that the processing timing is 16 ms.

When the value of the interrupt counter is “15” or less, the production control CPU 200 proceeds from step S104 to S117, performs the production soft random number update process, finishes one main process, and again performs the process from step S102. I do.
On the other hand, if the value of the interrupt counter is equal to or greater than “16”, the effect control CPU 200 executes the processes of steps S105 to S116, and then updates the effect software random number in step S117 to perform one main process. The process from step S102 is performed again.

Thus, every 16 ms counted by the interrupt counter, the effect control CPU 200 performs the 16 ms processing from step S105.
In that case, first, in step S105, the interrupt counter is reset to zero. Thereafter, the counting up to the next 16 ms processing is performed again.

In step S106, the effect control CPU 200 performs error processing. The error processing includes error processing timer processing during a RAM clear error, an accessory error, a right-handed error, etc., scenario registration processing for error notification when various errors occur, error scenario after error notification Clearing processing will be performed.
In particular, in the case of the present embodiment, in step S106, a volume MAX error flag setting process corresponding to a predetermined error detection is also performed. The volume MAX error means an error for which the volume of a sound (error sound) output in response to the occurrence should be set to MAX. When a volume MAX error is detected, that is, when an error sound is to be output by MAX, for example, 0x5A is set as the volume MAX error flag, and when a volume MAX error is not detected, for example, 0x00 is set as the volume MAX error flag. Set.

  Next, in step S107, the effect control CPU 200 performs a demo process. In this demonstration process, processing such as scenario registration and command set for playback sound control, demonstration movie execution, and accessory origin correction are performed. In the customer waiting state or the like, the demonstration movie display is executed by executing the scenario set in the demonstration process.

  In step S108, the effect control CPU 200 performs command analysis processing. In this command analysis process, the effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and reads out this command if the effect control command is stored. . Then, an effect control process corresponding to the read effect control command is performed. Details will be described later with reference to FIGS.

  In step S109, the effect control CPU 200 performs input detection processing. In this input detection process, an input is detected by operating the operation elements (the patrol switch 11, the effect button 12, and the cross key 13) of the operation unit 60. When an input is detected, a process corresponding to the operation is performed.

  In step S110, effect control CPU200 performs a scenario update process. In this process, the main scenario and subscenario are updated. At that time, lighting pattern registration of the decorative lamp units 64 and 65, registration of sound to be reproduced, registration of motor operation for driving the movable body accessory, and the like are also performed. Details will be described later with reference to FIGS.

In step S111, the effect control CPU 200 performs sound reproduction processing. The effect control CPU 200 outputs data such as a phrase number and volume to the sound source IC 59 in accordance with the sound data registered for each sound channel in the work based on the scenario data. Thereby, the reproduction output of the sound effect, music / sound, etc. from the speaker 25 is performed.
This sound reproduction process will be described later with reference to FIG.

  In step S112, the effect control CPU 200 performs an accessory error process. Here, a position error determination such as a return of the origin of the movable object is not performed.

  In step S113, the effect control CPU 200 updates the LED drive data. Here, processing for creating LED output data (driving data) is performed based on the lamp data registered as a lamp channel in the workpiece based on the scenario data. Details will be described later with reference to FIG. The LED output data is output to each LED driver 90 at a predetermined timing in the 1 ms timer interrupt process.

In step S114, the effect control CPU 200 performs checksum calculation and storage for the work area of the effect control RAM 202, and in step S115, stores the backup data.
In step S116, the scenario update counter is reset to zero. The scenario update counter is a counter that is incremented by a 1 ms timer interrupt process described later.

The 16 ms processing as described above is performed every 16 ms in the main loop processing of FIG.

[4-2: 1ms timer interrupt processing]

Next, the 1 ms timer interrupt process will be described with reference to FIG. The effect control CPU 200 executes the 1 ms timer interrupt process of FIG. 9 in response to an interrupt request generated every 1 ms by the time count.
In this 1 ms timer interrupt process, first, in step S201, it is determined whether or not a checksum is being calculated according to a test command from the main control CPU 100. If the checksum is not being calculated, the effect control CPU 200 proceeds to the input process in step S202.

The input process in step S202 is a process for every 1 ms for performing input detection by operating the operator together with the input detection process in step S109 of FIG. For example, in this input process, when an edge is detected in the signal waveform of the operation detection signal of the operation element, the input counter is reset, and thereafter, the input counter is counted up during a period in which no edge occurs. In the 1 ms timer interrupt process, input information (H or L of the input signal waveform) is detected, and the input counter is reset or incremented depending on the presence or absence of an edge. In step S109 in the main loop process (16 ms process), when the input counter value is 16 or more and the input information has changed from the previous time, the input change is recognized.
Such input processing (S202) and input detection processing (S109) can prevent erroneous input recognition due to noise chattering. In addition, since an input counter is used and, in this embodiment, for example, a 16-bit counter can be used to count up to 65535 ms (about 65 seconds), so-called long press can be detected.

In step S203, the effect control CPU 200 performs a motor operation update process. In this case, the effect control CPU 200 performs processing for creating motor drive data based on motor data registered as a motor channel in a work (motor data registration information described in FIG. 16C) based on scenario data. This is motor drive data output to the LED driver of the panel driver unit 62 in order to drive and control the movable body accessory motor 65. In the present embodiment, the LED drive data is updated every 16 ms in step S113, while the motor data is updated every 1 ms.
In step S204, the effect control CPU 200 outputs motor drive data. As described above, the stepping motor 121 of the movable body accessory motor 65 and the like are connected to some of the LED drivers 90 of the panel driver unit 62. In this step S204, serial data as drive data for these stepping motors 121 is sent to a predetermined LED driver 90 of the panel driver unit 62 (LED driver 90 that drives the movable body accessory motor 65 such as the stepping motor 121). Will be output.

In step S205, the effect control CPU 200 executes each process according to the value of the interrupt counter. The interrupt counter is reset to zero in step S105 of the 16 ms process described above and incremented in step S207 of the 1 ms timer interrupt process. Therefore, when step S205 is executed in the 1 ms timer interrupt process, the value of the interrupt counter is 0-15.
According to the interrupt counter values 0 to 15, the process of step S205 is defined as case 0 to case 15. For example, in the present embodiment, in case 0, a WDT (watchdog timer) clear signal ON and an initialization process of the LED driver 90 are performed. In cases 1 to 3, the LED driver 90 is initialized. In case 8, the WDT clear signal is turned OFF. In cases 12 to 15, LED drive data is output to the LED driver 90.
The initialization of the LED driver 90 is a process of outputting a default value to a register that is not used in the LED driver 90. This initialization and LED drive data output are performed for a few LED drivers 90 in one 1 ms timer interrupt process.

In step S206, the effect control CPU 200 outputs an effect control command to the liquid crystal control board 52. For example, one command (2 bytes) is transmitted in one 1 ms timer interrupt process. That is, a 2-byte effect control command as a mode and an event is transmitted.
Thereafter, the effect control CPU 200 increments the interrupt counter in step S207, and increments the scenario update counter in step S208. If the value of the scenario update counter is less than 100, the 1 ms timer interrupt process ends.
Since the scenario update counter is reset to zero in step S116 of the 16 ms process as described above, the scenario update counter value does not normally exceed 100. The value of 100 or more is a case where the 16 ms process is not executed due to a calculation abnormality, a process response abnormality or the like, or the progress of a certain process in the 16 ms process is stopped. In such a case, an infinite loop is entered, and the time-up process is performed by WDT.

When it is determined that the checksum is being calculated in step S201 when entering the 1 ms timer interrupt process, the effect control CPU 200 advances the process to step S210 and clears the WDT. In step S211, an effect control command is transmitted to the liquid crystal control board 52. In step S212, the interrupt counter is incremented and the 1 ms timer interrupt process is completed.

[4-3: Command analysis processing]

Next, the command analysis processing performed in step S108 of FIG. 8 as 16 ms processing will be described with reference to FIGS. The effect control CPU 200 monitors whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer as the command analysis process in step S108, and if the effect control command is stored, this command Is read. As this specific process, the processes of steps S301 to S308 in FIG. 10 are performed.

In the effect control unit 51, a command reception buffer that captures the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202, for example. In step S301 in FIG. 10, the effect control CPU 200 first checks the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to the command reception, and the received effect control command is stored in the address indicated by the light pointer accordingly. The read pointer is updated when reading from the command reception buffer is performed (step S302). Therefore, if the read pointer is not the write pointer, the effect control command that has not been read is stored in the command reception buffer. Therefore, if the read pointer is not the write pointer, the process goes to step S302, and the effect control CPU 200 loads 1-byte command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next reading (loading).

As described above, one presentation control command is formed of two bytes, one byte as a mode and one byte as an event. In step S303, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit 7 out of 8 bits (Bit 0 to Bit 7).
If it is the mode, the process proceeds to step S304 as a process for receiving the upper data of the command, and the read command data is saved in the register “command HI byte”. Also, the “command LO byte” register is cleared. Then, the process returns to step S301.
Even if the read pointer is not equal to the write pointer, the effect control command that has not yet been read is stored in the command reception buffer, and thus the process proceeds to step S302, where the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. In addition, the read pointer is incremented.
If the read command is an event, the process proceeds from step S303 to S305 as processing for receiving lower-order data of the command, and the read command data is saved in the register “command LO byte”.

The command data of the mode and the event is saved in the registers “command HI byte” and “command LO byte”, so that the effect control CPU 200 takes in one command.
Therefore, the effect control CPU 200 performs processing according to the fetched command in step S306. A specific example will be described later with reference to FIG.

  The read pointer = write pointer is when the effect control command that has not yet been captured by the effect control CPU 200 does not exist in the command reception buffer. Therefore, since new acquisition is unnecessary, the process proceeds to step S307. In this case, it is confirmed whether 100 ms has elapsed while waiting for a symbol command. If such a situation does not occur, the command analysis processing of FIG. 10 is finished. On the other hand, if 100 ms has elapsed while waiting for a symbol command, symbol fluctuation processing due to a missing command is performed in step S308.

An example of the command response process in step S306 will be described with reference to FIG.
FIG. 11A shows basic processing as command response processing. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first checks in step S321 of FIG. 11A whether or not it is currently in the test mode. If it is in the test mode, all the production scenarios are cleared, the sound output is stopped, and the LEDs in the decorative lamp units 63 and 64 are turned off in step S322. In step S323, the test mode ends.
These processes are not performed unless in the test mode.
Then, the effect control CPU 200 performs a process for the acquired effect control command as step S330.

  As the effect control command, for example, a special symbol variation pattern designation command, a special symbol designation command, a holding ball subtraction command, a holding ball addition command, an error display designation command, a jackpot start designation command, etc. are variously set. In step S330, the effect control CPU 200 performs a process specified by the program in response to the received command. Here, in FIG. 11B, FIG. 11C, FIG. 11D, and FIG. 11E, specific processing is exemplified by giving four effect control commands.

FIG. 11B shows a process S330a when a variation pattern command is fetched as the command process in step S330.
In this case, the effect control CPU 200 performs a process of setting a symbol command waiting state in step S331. This is because the effect control CPU 200 controls the variation display of the symbols by sequentially receiving the variation pattern command and the symbol commands.
FIG. 11C shows a process S330b when a symbol command is fetched as the command process in step S330.
In this case, the effect control CPU 200 first confirms whether or not the variation pattern command has been received in step S332. If it has not been received, the process ends.
If a variation pattern command has already been received when the symbol command is received, the process proceeds to step S333, and first, scenario registration for the operation of correcting the accessory origin is performed. In step S334, variation start processing is performed. In this variation start process, the scenario setting of the symbol variation operation according to the variation pattern command and symbol command, the presence / absence of execution of the announcement effect that should appear during the variation display, and its type are determined by lottery. Set up. Furthermore, it also transmits a command for liquid crystal display synchronized with them.
After executing this variation start process, the effect control CPU 200 deletes the variation pattern command in step S335.

FIG. 11D shows a process S330c when a power-on command is fetched as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S337. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339 the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, a power-on scenario is registered, and in step S342, the power is transmitted to the liquid crystal control board 52. Perform a set of commands sequentially.

FIG. 11E shows a process S330d when a RAM clear command is fetched as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S343. For example, the command reception / transmission buffer, the contents of the input information buffer for the operation unit 60, and the checksum storage area are cleared.
In step S344, an error cancel command is transmitted, and in step S345, a RAM clear error set and an error notification timer are set. In step S346, information related to the lottery process in the effect control RAM 202 is cleared. In step S347, information related to the scenario is cleared. In step S348, an initial power-on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

[4-4: Scenario registration / deletion processing]

Next, scenario registration / deletion processing will be described. The scenario is data defining various operations to be executed such as production control and error processing. The scenario data to be executed is registered in the work area of the effect control RAM 202 as scenario registration information. The scenario registration information shown in FIG. 16A will be described later. As scenario registration information, 64 scenario channels from 0 to 63 are prepared. Scenarios registered in these 64 scenario channels can be executed simultaneously. Hereinafter, the scenario channel is indicated by “sCH”.
The scenario registration process is a process of registering a scenario having a scenario number requested to be registered in an arbitrary scenario channel sCH in the scenario registration information. In principle, any scenario channel of sCH0 to sCH63 may be used.

  Scenario registration to be described below is called and executed when necessary, for example, in the process of error processing in step S106, demo processing in step S107, command analysis processing in step S108, and the like. For example, step S333 in FIG. 11C and step S341 in FIG. 11D described above are an example of the case where scenario registration is executed.

As the process of FIG. 12, the effect control CPU 200 performs a process of registering a scenario number and a standby time (delay) value corresponding to a scenario specified on a command or program in a work (scenario registration information).
In step S401, the effect control CPU 200 first checks whether or not the scenario number to be registered this time is normal. If the scenario number is not possible, the process ends without doing anything.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S402. The variable B is a variable used for sequentially searching for an empty channel among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether it is an empty channel).

In step S403, the effect control CPU 200 confirms whether or not the “additional pointer” + B scenario channel is empty. The additional pointer is a pointer set in step S407 described later when scenario registration is performed. At the time of starting the processing of FIG. 12, the value of the additional pointer is a value indicating the scenario channel next to the scenario channel registered last time. Note that the initial value of the additional pointer (the value when the processing in FIG. 12 is performed for the first time from the initial state) is zero.
If the “addition pointer” + B scenario channel is not empty, the effect control CPU 200 increments the variable B in step S404.
If B <64 is not satisfied in step S405, the processing in FIG. This is a case where all scenario channels have been searched but scenario registration is impossible because there are no free channels.
At a time point when all scenario channels have not been searched (confirmation of whether or not they are free channels), B <64 in step S405. In that case, the confirmation process of step S406 is performed, and if the value of “addition pointer” + B is not equal to or greater than the value “64” exceeding the maximum value of the scenario channel sCH, the process returns to step S403.
If the value of “addition pointer” + B is “64” or more, correction processing for the value of the addition pointer is performed in step S407. Specifically, when the value of “addition pointer” + B becomes “64”, a process of subtracting “64” from the value of the addition pointer is performed. Then, the process returns to step S403.

According to the processing in steps S403 to S407, it is sequentially confirmed from the scenario channel next to the previously registered scenario channel whether or not the scenario channel is empty.
That is, the scenario channel sCH that is confirmed every time step S403 is performed sequentially advances one by one due to the increment of the variable B in step S404.
Since variable B is zero-reset in step S402 and incremented in step S404, if B <64 is not satisfied in step S405 (that is, if variable B reaches 64), step S403 has already been performed. This process is performed 64 times. This is a case where all the scenario channels sCH0 to sCH63 have been examined and it is determined that there is no free space. For this reason, the processing of FIG.

Further, since the value of the “addition pointer” is a value indicating the next scenario channel after the previously registered scenario channel, the “addition pointer” + B even when B <64 when all the scenario channels have not yet been checked. (That is, the number of the scenario channel sCH to be checked next) may be “64” or more. Specifically, the value of “addition pointer” + B is 63 at the time of immediately preceding step S403, and after confirming the scenario channel sCH63, the variable B is incremented in step S404. In this state, the scenario channel sCH64 that does not exist next is designated.
Therefore, this point is confirmed in step S406, and if the value of “addition pointer” + B is “64”, in step S407, correction of the addition pointer is performed to return the scenario channel to be confirmed next to “sCH0”. Do. That is, the value of “addition pointer” + B is set to “0” by setting the value of the addition pointer to −64. Thus, in the next step S403, it is confirmed whether or not the scenario channel sCH0 is empty.

If an empty scenario channel is found in the process of step S403 at a certain time, the presentation control CPU 200 proceeds to step S408, and sets a scenario number and a waiting time (delay) in the empty scenario channel. In addition, the data necessary for other scenario management is cleared to zero.
In step S409, the additional pointer is updated to the value of the registered scenario channel + 1. That is, the value of the scenario channel next to the scenario channel registered this time is stored as an additional pointer so that it can be used for the next registration process. In this embodiment, since the scenario channel is 64 channels sCH0 to sCH63, the maximum value of the additional pointer is 63.

  According to the processing of FIG. 12, at the time of scenario registration, an empty channel is searched from the scenario channel next to the scenario channel that was registered last time. The initial value of the additional pointer is “0”, and is subsequently updated in step S407 according to the registration. In many cases, according to this process, scenario registration is performed using the scenario channel sCH0 in order. . When the scenario is registered, the availability is confirmed from the scenario channel next to the previous registered channel. Therefore, in most cases, an empty channel can be found quickly, and the scenario registration process can be executed efficiently. As a result, the processing burden on the effect control CPU 200 is reduced.

  As a modification of the process, the value of the additional pointer updated in step S407 may be set as the number of the scenario channel that has been registered, and 1 may be substituted for variable B in step S402. In this case, however, it is determined in step S405 whether B ≦ 65.

Next, scenario deletion processing will be described. This is a process for deleting a scenario registered in a certain scenario channel of the work.
FIG. 13A shows processing of the effect control CPU 200 when a certain scenario is deleted from the scenario registration information.
The effect control CPU 200 starts the process of FIG. 13A based on the value of a scenario number to be deleted (a main scenario number (mcNo) described later) designated on the command or the programgram. First, in step S421, the effect control CPU 200 confirms whether or not the scenario number related to the deletion request is normal. If the scenario number is not possible, the process ends without being deleted.

  If the scenario number is appropriate, effect control CPU 200 sets variable B to zero in step S422. The variable B in this case is a variable used for searching for a channel in which the scenario to be deleted is registered among the scenario channels sCH0 to sCH63. Further, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario to be deleted is registered).

In step S423, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B) is the scenario number to be deleted. If the scenario registered in the scenario channel sCH (B) is not the scenario number to be deleted, the variable B is incremented in step S424, and it is confirmed in step S425 that B <64, and the process of step S423 is performed. Do.
According to the processing of steps S423 and F424, the scenario to be deleted is searched in order from the scenario channel sCH0 to the scenario channel sCH63.
If the scenario registered in the scenario channel sCH (B) is the scenario number to be deleted in step S423, the process proceeds to step S426, and the scenario registered in the B area, that is, the scenario channel sCH (B) is deleted. Perform the process.
As described above, the process of deleting the scenario with the requested scenario number from the work (scenario registration information) is performed.
If it is determined in step S425 that B <64 is not satisfied, that is, if the variable B reaches 64, all the scenario channels sCH0 to sCH63 have been searched, but the scenario to be deleted has not been registered. Therefore, the process is finished.

FIG. 13B shows processing for deleting a certain range of scenarios. This process is performed when a deletion scenario is specified by a range.
The effect control CPU 200 first sets a variable B to zero in step S431 when a deletion is designated within a range of a certain scenario number on a command or program. The variable B in this case is a variable used to search for a channel in which a scenario corresponding to the deletion target range is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been searched (confirmation of whether or not a scenario corresponding to the deletion target range is registered).

In step S432, the effect control CPU 200 confirms whether or not the scenario registered in the B area, that is, the scenario channel sCH (B), is a scenario number within the range to be deleted. If the scenario registered in the scenario channel sCH (B) is a scenario number within the range to be deleted, the scenario registered in the scenario channel sCH (B) is deleted in step S433. Then, the process proceeds to step S434.
If the scenario registered in the scenario channel sCH (B) is not a scenario number within the range targeted for deletion, the process proceeds to step S434 without performing step S433.
The effect control CPU 200 increments the variable B in step S434, confirms that B <64 in step S435, and returns to step S432. If the variable B has reached 64, the processing has been completed for all scenario channels sCH0 to sCH63, and the scenario range deletion processing is completed.
As described above, one or more scenarios in the scenario number range are deleted from the work (scenario registration information).

FIG. 13C shows a process for deleting all registered scenarios. For example, it is a process called when a scenario is unavoidably deleted due to circumstances on the system. Do not delete scenarios that are targeted for protection.
When it is requested to delete all scenarios, the effect control CPU 200 first sets the variable B to zero in step S441. The variable B in this case is a variable used for confirming the scenario channel in which the scenario to be protected is registered among the scenario channels sCH0 to sCH63. Furthermore, the variable B also serves as a variable for determining whether or not there remains a scenario channel that has not yet been confirmed (confirmation of whether or not a scenario to be protected is registered).

In step S442, the effect control CPU 200 confirms whether or not the scenario registered in the B region, that is, the scenario channel sCH (B), is a scenario to be protected. If it is a scenario to be protected, it is not deleted. On the other hand, if it is not a scenario to be protected, the scenario registered in the scenario channel sCH (B) is deleted in step S443.
In step S444, the variable B is incremented. If B <64 in step S445, the process returns to step S442. If the variable B has reached 64, the processing has been completed for all the scenario channels sCH0 to sCH63, and thus the scenario all deletion processing ends.
As described above, all scenarios other than the scenario to be protected are deleted from the scenario registered as scenario registration information in the work.

[4-5: Scenario update processing]

Next, the scenario update process performed in step S110 of the 16ms process of the main process will be described. In the scenario update process, the main scenario and the sub-scenario are updated as described with reference to FIGS.

First, the structure of scenario registration information will be described with reference to FIGS. FIG. 16A shows the structure of scenario registration information as a main scenario and a sub-scenario. This scenario registration information is set using the work area of the effect control RAM 202.
As described above, in the present embodiment, the scenario registration information has 64 channels of scenario channels sCH0 to sCH63. Scenarios registered in each scenario channel sCH can be executed simultaneously.

  As shown in the figure, information that can be registered in each scenario channel sCH includes a sub-scenario timer (scTm) used in the sub-scenario update process, a sub-scenario execution line (scIx) indicating an execution line of the sound / motor sub-scenario table, and a lamp sub-scenario. Sub scenario execution line lmp (lmpIx) indicating the execution line of the table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, main scenario number (mcNo), There are main scenario option (mcOpt), user option (userFn), waiting time (delay), and checksum (checkSum), which are optional data that can be added to the main scenario.

When starting production of sound output by the speaker 25, light emission by the decoration lamp portions 63 and 64, and driving of the movable body accessory by the movable body accessory motor 65, the standby time (delay) and the main scenario number (scNo) are set as scenarios. It registers in an empty scenario channel among channels sCH0 to sCH63.
The waiting time (delay) indicates the time from registration to the scenario channel sCH until the scenario is started. The waiting time (delay) is decremented by 1 every 16 ms processing. When the waiting time (delay) is 0, processing corresponding to the registered data is executed.

FIG. 18 shows an example of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the main scenario timer (msTm) value is described as time data in each line (row) of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. . That is, in the main scenario table, a sub-scenario (and optional in some cases) to be executed is designated as the time by the main scenario timer (msTm). In the last line of the scenario, a scenario data end code D_SEEND or a scenario data loop code D_SELOP is described.
Since the value of the main scenario timer (msTm) is incremented by 1 in the scenario update process performed in the 16 ms process from the start of the main scenario, “1” indicates 16 ms. The scenario table of each scenario number advances to the next line when the time of the main scenario timer (msTm) in a certain line has elapsed. The time data of each line indicates the timing when the line ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as a time of 1500 × 16 ms, the operation of sub-scenario number 20 is specified as the next time of 500 × 16 ms, and the operation is performed as the next time of 2000 × 16 ms. The operation of scenario number 21 is designated. The next line is the scenario data end code D_SEEND. In the case of the scenario data end code D_SEEND, this scenario is deleted from the scenario registration information (work) (see step S617 in FIG. 14 described later).

Next, the structure of the lamp data registration information will be described with reference to FIG. 16B. As the lamp data registration information, a scenario selected from the lamp sub-scenario table, that is, information indicating a rendering operation (lighting pattern) by the decorative lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the ramp data registration information has 16 channels of ramp channels dwCH0 to dwCH15. Priorities are set for each of the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. Therefore, the scenario (lamp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. For example, if a scenario is registered in the ramp channels dwCH3 and dwCH10, the scenario registered in the ramp channel dwCH10 is preferentially executed.
The ramp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the lamp channel dwCH15 is used for an error-related lamp effect, and the lamp channels dwCH1 to dwCH14 are used for a normal effect.

  As shown in the figure, information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the number of the registered lighting pattern, an execution lighting number (lmpNo) indicating the number of the lighting pattern to be executed, and a lamp sub-scenario. There are an offset indicating an execution line (offset), an execution time (time), and a checksum (checkSum).

  FIG. 19A shows an example of lamp sub-scenario numbers 1, 2, and 3 as a part of the lamp sub-scenario table. For each number of lamp sub-scenarios, time data (time) values are described in each line (row) of the scenario, and lamp channels and lamp numbers indicating various lighting patterns are described. In the last line, a lamp scenario data end code D_LSEND is described.

In this ramp sub-scenario table, the time data (time) of each line indicates the time at which the line is started after the sub-scenario is started.
When the main scenario timer (msTm) and the time data in the table are compared every 16 ms and they match, the lamp number of that line is registered in the lamp data registration information of FIG. 16B. The registered ramp channel dwCH is the channel indicated in the line.
For example, it is assumed that the scenario number 2 shown in FIG. 18 is registered and the sub-scenario number 2 is referred to in the certain scenario channel sCH. In the lamp sub-scenario number 2 shown in FIG. 19A, the lamp channel 5 (dwCH5) and the lamp number 5 are described as time data (time) = 0 on the first line. In this case, when the main scenario timer (msTm) = 0, the information on the first line is first registered in the lamp channel dwCH5 of the lamp data registration information in FIG. 16B as the registered lighting number (lmpNew) = 5. The value of the sub-scenario execution line lmp (lmpIx) in the scenario registration information (FIG. 16A) is updated to the value of the next line (second line). This is a registration for performing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, the same processing is performed when it becomes 500 × 16 ms. That is, the registered lighting number (lmpNew) = 6 (that is, the lighting pattern 6 lighting instruction) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) has the same value for two consecutive lines, the processing for each line is started simultaneously.
In the LED drive data update process to be described later, LED drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 16C. As the motor data registration information, information indicating a scenario selected from the sound / motor sub-scenario table (described later in FIG. 19B) is registered. This motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the motor data registration information is assumed to have eight channels of motor channels mCH0 to mCH7.
Information that can be registered in each motor channel mCH includes execution operation number (no), registration operation number (noNew), operation count (lcnt), excitation counter (tcnt), execution step (step), operation line as shown in the figure. (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), Current input information (currentSw), software switch information (softSw), and software count (softCnt).

FIG. 17 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound / motor sub-scenario table (described later in FIG. 19B) is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 channels of sound channels aCH0 to aCH15. Each of the sound channels aCH0 to aCH15 corresponds to each of the input channels (also 16) of the sound source IC 59.
Information that can be registered in each sound channel aCH includes primary volume transition amount (frzVq), primary volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0) as shown in the figure. , Stereo (frzSt), loop (frzLp), phrase number hi (frzHi), phrase number low (frzLo), and secondary volume (scdVl).

Here, the primary volume is volume information described together with phrase number information of a phrase to be reproduced in scenario data (BGM, SE1, SE2, error described later) instructing the start of reproduction of a certain phrase. .
The secondary volume is volume information that determines the final reproduction volume by multiplying with the primary volume.
The difference between the primary volume and the secondary volume is as follows.
As described above, the primary volume is also described in the scenario data for instructing the start of phrase reproduction, whereas the secondary volume is described in the scenario data for sound control (sound control information) described later.
Further, in the case of the present embodiment, depending on the primary volume, volume control for the phrase being played back is possible by combining with the information of the primary volume transition amount (frzVq). Phrase fade-in playback / fade-out playback is enabled. As will be described later, these fade-in playback / fade-out playback instructions are executed based on scenario data as sound control.
The secondary volume is usually set to a value according to the state of the volume switch provided on the back side of the pachinko gaming machine 1, and the MAX value is used when an error or a desired phrase is to be muted as described later. Different values are set.
The secondary volume change instruction can also be made by scenario data as sound control (this will also be described later).

The primary volume transition amount frzVq is information indicating the time (speed) for changing the primary volume.
The transition amount change rsv2 is information indicating whether or not the primary volume transition amount frzVq is changed, and the volume change rsv1 is information indicating whether or not the primary volume is changed during phrase reproduction. The phrase change rsv0 is information indicating whether or not the phrase number is rewritten. The stereo frzSt is either stereo playback or monaural playback, and the loop frzLp is either infinite loop playback or no loop playback. It becomes information to represent.

  As shown in the figure, the primary volume transition amount, the primary volume, and the data size of the secondary volume are each 1 byte (8 bits). Each information of transition amount change, volume change, phrase change, stereo, and loop is 1 bit. Furthermore, the phrase number hi is 3 bits, and the phrase number low is 1 byte. That is, the phrase number information is composed of 11 bits, so that a maximum of 2048 phrases can be specified.

In this example, in the case of stereo reproduction, two sound channels aCH that are adjacent to each other are used. Specifically, the sound channel aCHn that is an even channel and the sound channel aCHn + 1 that is the next odd channel are used.
In the scenario data instructing stereo playback, information on the phrase number for designating a phrase to be played back in stereo (one phrase number common to Lch and Rch is used as designation information) and stereo playback are designated. Based on the scenario data, the phrase number and stereo playback instruction information are registered in the even sound channel aCHn and the odd sound channel aCHn + 1 in the sound data registration information (described above). Phrase numbers hi, low and stereo frzSt).

FIG. 19B shows an example of sound / motor subscenario numbers 1 and 2 as part of the sound / motor subscenario table.
As the sound / motor sub-scenario of each number, the time data (time) value (ms) is described in each line (row) of the scenario, and BGM, SE1, SE2, error sound, sound control, motor, solenoid / User option information can be described. In the last line, a scenario data end code D_SEEND is described.
With respect to this sound / motor sub-scenario table, if the value of the sub-scenario timer (scTm) becomes the value of time data (time) described in a certain line in the sound / motor sub-scenario table (initially 0) The information corresponding to the BGM, SE1, SE2, error sound, sound control, motor, solenoid / user option described in the line is registered in the sound data registration information and motor data registration information.
The time data (time) of each line indicates the timing when the line ends.

Here, SE (SE1 and SE2) in the sound / motor sub-scenario table means sound related to effects other than BGM and error sound. Sounds for so-called notice effects (notice sounds) are classified into this SE.
The distinction between SE1 and SE2 is made according to the appearance frequency of the effect that outputs the sound. For example, in the case of a notice sound, the distinction is based on the appearance frequency (reliability) of the notice effect that uses the sound. In the case of this example, SE2 is a sound related to an effect having a lower appearance frequency than SE1.

Each information of BGM, SE1, SE2, and error sound in the sound / motor sub-scenario table includes a phrase number and primary volume information.
The BGM, SE1, SE2, and error sound information described in the sound / motor sub-scenario table are registered in one of the sound channels aCH in the sound data registration information. For each type of BGM, SE1, SE2, and error sound, a sound channel aCH for registering the information content is determined in advance.
Specifically, the BGM information described in the sound / motor sub-scenario table is registered in the sound channel aCH0 (in addition, in the case of stereo, aCH1). In addition, information on SE1 is registered in an empty channel of sound channels aCH2 to aCH9, and information on SE2 is registered in an empty channel of sound channels aCH10 to aCH14. Further, information on the error sound is registered in the sound channel aCH15.
As described above, in the present embodiment, the correspondence between the type of sound and the sound channel aCH for registering sound-related information about the sound is determined in advance.

The sound control information in the sound / motor sub-scenario table describes information for controlling the phrase being reproduced.
In the case of the present embodiment, the sound control information is composed of 4 bytes, the lower 3 bytes are information for designating a phrase to be controlled, and the upper 1 byte is control information (information indicating the control content of the sound) Has been.

Here, in the present embodiment, the correspondence between the type of sound and the sound channel aCH for registering information about the sound is determined as described above. This is because the phrase as BGM is the sound channel aCH0. (Stereo is aCH0 and aCH1), the phrase SE1 is reproduced on any of the sound channels aCH2 to aCH9, the phrase SE2 is reproduced on any of the sound channels aCH10 to aCH14, and an error sound In other words, it can be said that the phrase is reproduced on the sound channel aCH15.
Therefore, when a predetermined type of sound (BGM / SE1 / SE2 / error sound) is controlled based on the sound control information, the sound control information is registered for the sound channel aCH corresponding to the sound. That's fine.
In view of this point, in the sound control information of the present embodiment, information specifying the sound channel aCH is described as information of the lower 3 bytes, that is, information for specifying the phrase to be controlled. That is, the sound channel aCH (that is, aCH0 (and aCH1) / aCH2 to aCH9 / aCH10 to aCH14 / aCH15 according to the type of BGM / SE1 / SE2 / error sound) in which the sound (phrase) to be controlled is reproduced. Information to be specified is described.

  It should be noted that specific processing for registering each information of BGM, SE1, SE2, error sound, and sound control described in the sound / motor sub-scenario table in the work as sound data registration information is shown in FIGS. It will be described later.

In this embodiment, as described above, the correspondence between the sound type and the sound channel aCH in which information about the sound is registered is determined in advance, so that a certain type of sound is generated. The reproduced sound channel aCH can be uniquely determined. Thus, when a certain type of sound being played is controlled, it is only necessary to register control information for the sound channel aCH associated with that type of sound in the work, and the sound to be controlled is played back. It may be unnecessary to search for the middle sound channel aCH.
Therefore, the control load related to the rendering operation can be reduced as much as the search process is omitted.

Further, as described above, in the present embodiment, the sound control information for controlling the sound being reproduced includes information indicating the content of the control, and information indicating the sound channel aCH corresponding to the sound to be controlled. Information.
As described above, even when the sound control information is information that can designate the sound channel aCH that is the registration destination of the control content information, it is not necessary to search for the sound channel aCH that is reproducing the sound to be controlled. That is, the point that the sound control information has such a configuration also contributes to the omission of the search process, that is, the reduction of the control load related to the rendering operation.

The description returns to FIG. 19B.
In the sound / motor sub-scenario table, the motor data is configured to indicate the motor operation pattern number in one byte for each motor.
This operation pattern number is set for the motor channel corresponding to the motor number.

In the sound reproduction process described as step S111 in FIG. 8, reproduction output is performed based on the sound data registration information updated in the scenario update process in FIGS.
In the motor operation update process in step S203 of FIG. 9, motor drive data is created based on the motor data registration information updated in the scenario update process of FIGS.

Scenario update processing executed using each piece of information described so far will be described with reference to FIGS.
In the scenario update process of FIG. 14 executed as step S110 of the 16 ms process of FIG. 8, the effect control CPU 200 performs the processes of steps S600 to S616 for each of the scenario channels sCH0 to sCH63 as the loop process LP1. The scenario channel to be processed each time in the loop processing will be described as “sCHn”.

  The effect control CPU 200 confirms whether or not the main scenario number of the scenario channel sCHn is 0 in step S600. When the main scenario number is 0, the scenario channel sCHn is a channel sCH for which the main scenario has not been registered in the scenario registration process of FIG. 12, and thus information update of the scenario channel sCHn is unnecessary. Therefore, in this case, the processing after step S615 is executed to finish the processing. Specifically, the checksum of the data related to the scenario channel sCHn is calculated and stored in step S615, and the data related to the scenario channel sCHn is backed up and stored in step S616. This completes one process for the scenario channel sCHn.

  On the other hand, if it is determined in step S600 that the main scenario number is not 0, the process proceeds to step S601, and the standby time (delay) of the scenario channel sCHn is confirmed. If the standby time (delay) = 0 is not satisfied, the value of the standby time (delay) is decremented by −1 (decrement) in step S602. And the process of step S615 and S616 is performed and the process of 1 time about scenario channel sCHn is finished.

If it is confirmed in step S601 that the standby time (delay) = 0, the effect control CPU 200 proceeds to step S603, and the main scenario number (mcNo) registered in the scenario channel sCHn and the main scenario execution line ( Specify the address of the main scenario table corresponding to mcIx).
In step S604, it is confirmed whether or not an execution line of a certain main scenario number in the main scenario table indicated by the specified address is a final line in which an end code D_SEEND (see FIG. 18) is described.
If the end code matches the last line in which the end code is described, the processing to be executed in the scenario registered in the scenario channel sCHn has been completed. In step S617, the scenario registered in the scenario channel sCHn. Is deleted from the scenario registration information (work).
Note that the scenario registration deletion in this case is a normal deletion corresponding to the end of the scenario. It is added that the scenario deletion described above with reference to FIG. 13 is a process of deleting, for example, an unfinished scenario from the scenario registration information (work) other than the normal deletion.

  After the scenario is deleted in step S617, the process proceeds to step S615.

If it is determined in step S604 that the line in the main scenario table is not an end code, the production control CPU 200 proceeds to step S605, and first sets the option (OPT) of the line in the main scenario option (mcOpt) of the scenario channel sCHn. To do. In step S607, 0 is substituted for the user option (userFn).
In step S608, the sub-scenario specified by the scenario channel sCHn is updated. The sub-scenario update will be described later with reference to FIG.

In step S609, the effect control CPU 200 increments the main scenario timer (msTm) by +1. In step S610, the value of the main scenario timer (msTm) is compared with the time data of the corresponding line in the main scenario table (see FIG. 18: described in msTm). As described above, the time data of each line in the main scenario table defines the end timing of the line, so the value of the main scenario timer (msTm) is described in the relevant line in the main scenario table. If it is more than the time data, the process for that line ends and the next line is targeted. Accordingly, if it is determined in step S610 that the value of the main scenario timer (msTm) is equal to or greater than the time data described in the relevant line of the main scenario table, the process proceeds to step S611, and the main scenario execution line (mcIx for the scenario channel sCHn). ) +1. That is, next time, the next line is targeted.
If it is determined in step S610 that the value of the main scenario timer (msTm) is not equal to or greater than the time data described in the relevant line of the main scenario table, the process proceeds to step S615.

After the main scenario execution line (mcIx) of the scenario channel sCHn is incremented by 1 in step S611, it is confirmed in step S612 whether or not the next line is a loop designation. In scenario number 1 in the main scenario table of FIG. 18, an example is shown in which the last line is the scenario data loop code D_SELOP. Set loop line to mcIx).
If it is determined in step S612 that the next line is not designated as a loop, the process proceeds to step S614 without going through step S613.

In step S614, the effect control CPU 200 performs a clear process according to the end of one line. That is, main scenario timer (msTm), sub-scenario timer (scTm), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), main scenario option (mcOpt), user option (userFn), standby time (delay) To clear.
Then, the checksum process in step S615 and the backup process in step S616 are performed, and one process for the scenario channel sCHn is completed.
As the scenario update process, the above process is executed for each of the scenario channels sCH0 to sCH63 as the loop process LP1.

The sub-scenario update process performed in step S608 is shown in detail in FIG. 15A.
Based on the main scenario timer (msTm), the scenario channel sCHn, and the sub-scenario number (scNo) described in the main scenario table, the sub-scenario update process of FIG. 15A is performed.

First, in step S621, the effect control CPU 200 confirms whether or not the scenario channel sCHn indicates any of 0 to 63, that is, whether or not it is an appropriate value. If the scenario channel sCHn is 64 or more, the update process is impossible and the process of FIG. 15 ends.
If the scenario channel sCHn is an appropriate value, the effect control CPU 200 identifies the address of the lamp sub scenario table (see FIG. 19A) corresponding to the sub scenario number (scNo) and the sub scenario execution line lmp (lmpIx) in step S622. .

  In step S623, the effect control CPU 200 sets the lamp channel count value to zero. This lamp channel count value is a value managed by the effect control CPU 200 in order to prevent the lighting pattern number from being registered in the lamp data registration information beyond the number (16) of the lamp channels dwCH. It is.

  In step S624, the effect control CPU 200 compares the main scenario timer (msTm) with the time data (time) in the lamp sub-scenario table. The time data (time) in the lamp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer (actually, the time of msTm × 16 ms) is equal to or greater than the time data (time), the processing for that line is performed. In that case, in step S625, it is confirmed whether or not the ramp channel count value is normal (within “16” which is the number of ramp channels dwCH). If it is an abnormal value, the process ends. If it is a normal value, it is checked in step S626 if the current line is a line in which the lamp scenario data end code D_LSEND is described.

If it is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel and lamp number described in the line in step S627. In step S628, the lighting pattern number is registered.
The lighting pattern number registration process is shown in FIG. 15B. In this case, first, in step S651, the effect control CPU 200 determines whether or not the value of the lamp channel dwCH described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If it is a normal value, it is determined in step S652 whether or not the ramp number described in the line is a normal value. If it is not a normal value, the process ends without performing registration.
If both the lamp channel dwCH and the lamp number are normal values, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH in the lamp data registration information of the work in step S653. To do. That is, the lamp number acquired from the relevant line in the lamp sub-scenario table is set in the registered lighting number (lmpNew), and “0” is set in the execution lighting number (lmpNo).
15B is performed in step S628, the effect control CPU 200 increments the value of the sub-scenario execution line lmp (lmpIx) in step S629, increments the ramp channel count value in step S630, and returns to step S624.

  When the time of the main scenario timer does not reach the time data (time) of the line indicated by the sub-scenario execution line lmp (lmpIx) in step S624, and the lamp scenario data end code D_LSEND is confirmed in step S626 The process of the effect control CPU 200 proceeds to step S631.

In step S631, the sub-scenario number described in the main scenario table and the address of the sound / motor sub-scenario table corresponding to the sub-scenario execution line (scIx) registered in the currently processed scenario channel sCHn are specified. .
In step S632, it is checked whether the value of the sub-scenario timer (scTm) is equal to or greater than the value of the time data (time) in the table. That is, whether or not the value of the sub-scenario timer (scTm) is equal to or greater than the value of the time data (time) of the line indicated by the sub-scenario execution line (sclx) registered in the currently processed scenario channel sCHn. Check.

  In step S632, if the value of the sub-scenario timer (scTm) is not equal to or greater than the value of the time data (time) in the table, the registration process for the information described in the line should not be executed yet, as shown in the figure. Then, the process proceeds to step S640 without registering the sound and the motor, the value of the sub-scenario timer (scTm) is incremented (+1), and the process of FIG. 15A is completed.

On the other hand, if the value of the sub-scenario timer (scTm) is equal to or greater than the value of the time data (time) in the table in step S632, the effect control CPU 200 advances the process to step S633 and stores the corresponding sound / motor sub-scenario number table. Then, it is confirmed whether or not the line indicated by the sub-scenario execution line (scIx) is a line in which the scenario data end code D_SEEND is described. If the scenario data end code D_SEEND is described, the process ends.
If the scenario data end code D_SEEND is not described, the effect control CPU 200 performs sound registration in step S635 and motor registration in step S636. As the registration processing of these steps S635 and S636, the information on the corresponding line of the corresponding sub-scenario number in the sound / motor sub-scenario table as illustrated in FIG. 19B is used as the sound channel aCH of the sound data registration information in FIG. Each of the motor data registration information is registered in the motor channel mCH.
The detailed processing contents of the sound registration executed as step S635 will be described later (FIGS. 24 to 28).

Subsequently, in step S637, the effect control CPU 200 registers the solenoid / user option information described in the line in the scenario registration information or the like.
In step S638, the value of the next line is set as the value of the sub-scenario execution line (scIx). Further, in step S640, the sub-scenario timer (scTm) is incremented and the process is terminated.

  In step S110 in FIG. 8, the processes in FIGS. 14 and 15 are performed. Through this process, the scenario registration information, lamp data registration information, motor data registration information, and sound data registration information on the workpiece are sequentially updated, and effect control according to the scenario is realized by performing effect control accordingly. The

Particularly in the present embodiment, scenario registration information is set in the first work area (scenario channels sCH0 to sCH63) as effect data for specifying the effect type. Specifically, the main scenario number (mcNo) is set, and the sub-scenario on the main scenario table is specified. Further, in the first work area, a sub-scenario execution line (scIx) indicating an execution line of the sound / motor sub-scenario table and a sub-scenario execution line lmp (lmpIx) indicating an execution line of the lamp sub-scenario table are set. The production type is specified by these.
Further, the operation data of the effect device corresponding to the effect to be executed is set in the second work area. Lamp channels dwCH1 to dwCH15 for setting lamp data registration information, motor channels mCH0 to mCH7 for setting motor data registration information, and sound channels aCH0 to aCH15 for setting sound data registration information are prepared as second work areas.
In other words, in the present embodiment, overall presentation data using various presentation devices is set in the first work area, and operation data is set in the second work area based on the presentation data of the first work area. Will be.
In this case, in order to set various effects, it is preferable to relatively increase the number of effects data (number of scenario registration information) that can be registered in the first work area. For example, I want to increase the number of registered channels for production data. Therefore, 64 channels are prepared as scenario channels sCH0 to sCH63.
On the other hand, since the operation data that defines the operation of the rendering device need only be set in the second work area, the number of registerable operation data may be relatively small. In particular, since the second work area is provided corresponding to each effect device for lamps, motors, and sounds, it is not necessary to unnecessarily increase the number that can be registered for each device. Therefore, as the second work area, the ramp channel is 16 channels (dwCH1 to dwCH15), the motor channel is 8 channels (mCH0 to mCH7), and the sound channel is 16 channels (aCH0 to aCH15). Since it suffices for the operation data for one corresponding production device to be set for each of them, it is possible to cope with a wide variety of production operations even if the number of registered channels is small.
Thus, if the number of channels in the first work area is N (for example, N = 64) and the number of channels in the second work area is M (for example, M = 16 or M = 8), N> M. The storage area is allocated as follows.
This keeps the memory from being consumed by the dark clouds while still allowing a variety of performance operations.

[4-6: LED drive data update process]

The LED drive data update process in step S113 of FIG. 8 will be described.
This process is a process for creating LED drive data with reference to the lamp data table corresponding to the lighting number (registered lighting number (lmpNew), execution lighting number (lmpNo)) registered in the lamp data registration information. . As described above, the lamp number indicating the lighting pattern originally set in the lamp sub-scenario table is set as the lighting number of the lamp data registration information. The lamp number has been described as the number indicating the lighting pattern, but specifically indicates the lamp data number of the lamp data table described in FIG. 23A.

FIG. 20 shows LED drive data update processing.
In step S701, the effect control CPU 200 clears the LED drive data that has been output data until then.
Then, as loop processing LP2, the processing of steps S702 to S720 is performed for each of the lamp channels dwCH0 to dwCH15 of the lamp data registration information. Hereinafter, the lamp channel to be processed will be described as “dwCHn”.

In step S702, the effect control CPU 200 checks whether or not the execution lighting number (lmpNo) and the registered lighting number (lmpNew) in the target lamp channel dwCHn match. Since the lighting pattern number is registered as in step S653 of FIG. 15B, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) do not match at first. If they do not match, the lighting is started, and the value of the registered lighting number (lmpNew) is substituted into the execution lighting number (lmpNo) in step S703. In step S704, the execution line (ofset) is set to 0, and the execution time (time) is set to 0.
If the execution lighting number (lmpNo) matches the registered lighting number (lmpNew), the above steps S703 and S704 have already been performed, and these processes are unnecessary.

Regarding the information registered in a certain lamp channel dwCH, after the registration, the LED drive data to be output to each LED driver 90 is created for each occasion of the LED drive data update process.
FIG. 21A shows a state where registration is performed on the ramp channels dwCH0, dwCH5, and dwCH8 in the ramp data registration information of the workpiece shown in FIG. 16B. The state in this figure is an example of the state at time t0 in FIG. 21B.
That is, the information on the lamp channels dwCH0 and dwCH5 is reflected in the LED output data before time t0. For the lamp channel dwCH0, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 3 (third line). Also, for the lamp channel dwCH5, the execution lighting number (lmpNo) and the registered lighting number (lmpNew) have already been matched, and the execution line (ofset) has advanced to 2 (second line). At time t0, the lamp channel dwCH8 is immediately after registration, and the execution lighting number (lmpNo) and the registration lighting number (lmpNew) are not matched. Thereafter, the processes in steps S703 and S704 are performed.

As described above, in the present embodiment, priority is set for the ramp channels dwCH0 to dwCH15, and the priority increases in order from the ramp channels dwCH0 to dwCH15. As shown in FIG. 21A, the lamp channel dwCH15 having a high priority is used for error notification. Lamp channels with high priority, such as the lamp channels dwCH12, dwCH13, dwCH14, etc. are used for relatively highly reliable performances such as continuous notices and final notices. The lamp channel with medium priority is used for moving body effects, and the lamp channel with relatively low priority is used for effects with relatively low reliability, such as conversation notices and step-up notices. Channels are used for ramp effects that are synchronized with normal fluctuations, reach, and the like.
Due to such priority setting, when the operations of a plurality of lamp channels dwCH overlap as shown in FIG. 21B, a lighting operation of a lamp channel with a high priority is executed. For example, from time t0, the lighting operation based on the lamp channels dwCH0 and dwCH5 is limited, and the LED output data is generated so that lighting based on dwCH8 is performed. In order not to reflect the information of the lamp channel having a low priority, mask data described later is used.

Subsequently, in step S705 of FIG. 20, the effect control CPU 200 confirms whether or not the value of the execution lighting number (lmpNo) is within a normal range. The normal range is a range where numbers exist as lamp data in the lamp data table shown in FIG. 23A.
If the execution lighting number (lmpNo) is abnormal, the process proceeds to step S719. In the case of an empty channel in which the lamp channel dwCHn is not registered, the process proceeds to step S719 as abnormal here.

If the execution lighting number (lmpNo) is normal, the process proceeds to step S706. In step S706, the effect control CPU 200 specifies the address of the lamp data table corresponding to the execution lighting number (lmpNo) and execution line (ofset) registered in the lamp channel dwCHn.
In step S707, the execution lighting number (lmpNo) registered in the lamp channel dwCHn and the address of the mask data table are specified.
To specify the address, the effect control CPU 200 refers to a lamp data address table as shown in FIG. In this lamp data address table, the address of the lamp data number for realizing each lighting pattern, for example, entire flashing, right flashing, left flashing, and accessory lighting is shown. The numbers on the left side of FIG. 22 are the lamp numbers shown in the lamp sub-scenario table of FIG. 19A. The stored address is described.
In the address field of mask data, an address where mask data necessary for executing the lighting pattern of the lamp data number is stored is stored. For example, when a lighting pattern of blinking on the right side of the lighting number 5 is performed, a center case mask is required, but an address of mask data for performing the center case mask is described.

FIG. 23A shows lamp data 1 and 2 as part of the lamp data table.
Each line in each number of lamp data describes time data and lighting data as a timer (frame). The timer (frame) defines the time for generating LED output data based on the lighting data of each line.
The lighting data is described corresponding to each LED driver 90. In FIG. 4, it is assumed that there are n LED drivers 90 in the frame driver unit 61 and m LED drivers 90 in the panel driver unit 62. The description will be made on the assumption that there are five LED drivers 90 in 62, that is, a total of nine LED drivers 90.
In that case, lighting data is described in each line of the lamp data corresponding to each of the nine LED drivers 90, as shown in FIG. 23A. In the figure, the correspondence with each LED driver 90 is indicated by w1 to w4 and b1 to b5 as slave addresses of the LED driver 90.
As the lighting data, 4 bits (0h to Fh) are assigned to one output terminal 96 (one series of LED drive current outputs) of the LED driver 90 described in FIGS. 4 and 5 (“h” is Hexadecimal notation is shown), and the luminance of 16 gradations is designated. As described in FIG. 5, the LED driver 90 has 24 output terminals 96-1 to 96-24. Therefore, one piece of lighting data is information of (4 × 24) bits as “FFFF000055550000AAAAAAAA (h)”. If the lighting data for the LED driver 90 (w1) is “FFFF00000000000000055550000 (h)” as shown in the first line of the lamp data 1 shown in the figure, the output terminals 96-1 to 96-96 of the LED driver 90 (w1). -4 outputs a driving current for emitting the maximum luminance “F”, the output terminals 96-5 to 96-16 and 96-21 to 96-24 are not emitting light (minimum luminance), and the output terminal 96-17. ... 96 to 20 is information for designating output of a drive current having a luminance of “5”.
In the lamp data, such lighting data is set for each of the LED drivers 90 (w1 to w4, b1 to b5), and is set for each line, so that time series. A predetermined light emission pattern that changes is shown. (In the figure, the lighting data is illustrated only in part. The blank portion is not shown, and the lighting data is actually described.)

FIG. 23B shows mask data 1 to 5 as examples of the mask data table. Each mask data includes a mask for driving the decorative lamp 20w on the frame side, a mask for driving the decorative lamp 20b on the board side, an entire mask, a mask for the center case, Necessary mask patterns are stored for masking and the like.
The mask data 1 to 5 are data indicating that the output terminals 96-5 to 96-24 of the LED drivers 90 (w1 to w4 and b1 to b5) are turned off by “0h” and no mask by “Fh”, respectively. It is said that.
For example, in the mask data 1, the LED driver 90 (w1 to w4) in the frame driver unit 61 is “0000... 00 (h)” and the output terminals 96-5 to 96-24 are turned off. Is set for the LED drivers 90 (b1 to b5) of the panel driver unit 62, and "FFFF... FF (h)" and no output masks are set for the output terminals 96-5 to 96-24. ing. That is, the data specifies that only the decorative lamp 20w on the frame side is masked. (Note that the mask data 4 and 5 are not shown with data values)

In steps S706 and S707 in FIG. 20, an address corresponding to the lamp channel dwCHn being processed is specified in the lamp data table and the mask data table.
Subsequently, in step S708, the effect control CPU 200 obtains a timer (frame) of the relevant line (the line indicated by the execution line (offset) of the current target lamp channel dwCHn) in the lamp data table, and substitutes it for the variable Dtime. .

  In step S709, the effect control CPU 200 develops the corresponding lighting data and mask data specified in steps S706 and S707, and generates LED drive data. Although this process will be described later, the lighting data and mask data for the lamp channel dwCHn currently being processed are reflected in the LED drive data to be output.

In step S710, the execution time (time), which is information of the ramp channel dwCHn, is incremented by one.
In step S711, the variable Dtime is compared with the execution time (time). The timer (frame) of the currently executing line is assigned to the variable Dtime. The execution time (time) is incremented by 1 in step S710 for each LED drive data update process (every 16 ms). Therefore, if Dtime ≦ time, the current line end timing is reached. If Dtime ≦ time is not satisfied, it is determined that the end of the current line has not yet been reached, and the process proceeds from step S711 to S719. If Dtime ≦ time, the process proceeds from step S711 to S712 as the end of the current line.
The effect control CPU 200 resets the execution time (time) to 0 in step S712. In step S713, the execution line (offset) value is incremented by one. In other words, the next line is targeted.
In step S714, the effect control CPU 200 specifies the address of the lamp data table corresponding line corresponding to the execution line (offset). In steps S715 and S717, it is confirmed whether an end code (D_DTEND) or a loop code (LMP_LP) is described in the line.
If the end code (D_DTEND) is described, the registered lighting number of the lamp channel dwCHn is updated to 0 in step S716. In other words, it indicates that the processing corresponding to the registration of the lamp channel dwCH is completed on the work.
If the loop code (LMP_LP) has been described, the value of the execution line (offset) is updated to the loop destination address in step S718.

In step S719, the effect control CPU 200 calculates the checksum of the LED drive data at the time of the lamp channel dwCHn. In step S720, the backup data is saved.
This completes the LED data update for one lamp channel dwCHn. As the loop processing LP2, the above processing is sequentially performed up to the ramp channels dwCH0 to dwCH15.

The LED output data is updated in each lamp channel dwCHn in step S709, and this is the following process.
The output data buffer that generates the LED drive data by expanding the lighting data and the mask data corresponds to each of the LED drivers 90 (w1 to w4, b1 to b5), similarly to the lamp data table and the mask data table. Prepared. For example, an information area of (4 × 24) bits corresponding to one LED driver 90 is provided for each of, for example, nine LED drivers 90 (w1 to w4, b1 to b5). In this case, the output data buffer is a 9 × (4 × 24) bit buffer area.

For such an output data buffer, in step S709, a process of developing the mask data with AND (logical product) and developing the lighting data with OR (logical sum) is performed. This is sequentially performed in step S709 for each of the lamp channels dwCH0 to dwCH15 by loop processing (LP2).
For example, at the time t0 shown in FIG. 21, the output data buffer is AND-expanded with the mask data of the lamp data 2 (see FIG. 22: no mask), and the lighting data of the third line of the lamp data 2 is OR-expanded. After the state, the mask data of the lamp data 5 (see FIG. 22: center case mask) is AND expanded, and the lighting data of the second line of the lamp data 5 is OR expanded.
As described above, in the mask data, 0h (= 0000) is extinguished and Fh (= 1111) is no mask. Therefore, expanding the mask data with AND means that the bit to be extinguished (masked) is set to “0” in the output data buffer value up to that point, and the bits not masked are not changed.
Further, when the lighting data is expanded OR, the lighting data of the lamp channel dwCH being processed is reflected in the output data buffer after masking.
By sequentially performing this process for the lamp channels dwCH0 to dwCH15, the LED drive data that is prioritized for the higher-numbered lamp channels is formed on the output data buffer.

The LED drive data generated by the LED data update process as described above is actually sent to each LED driver in step S205 (in the above cases 12 to 15) of the 1 ms timer interrupt process described with reference to FIG. In this way, a lamp effect operation according to the scenario data is realized.

[4-7: Sound registration processing]

Next, the sound registration process executed as step S635 in FIG. 15 will be described.
This sound registration processing is processing for registering information corresponding to the description content (subscenario data) of the sound / motor sub-scenario table illustrated in FIG. 19B in the sound channel aCH of the sound data registration information of FIG.

FIG. 24 shows a sound registration process.
First, the effect control CPU 200 determines in step S800 whether sound data exists in the sound / motor sub-scenario table. That is, it is determined whether or not any information of BGM / SE1 / SE2 / error sound / sound control exists as the description information of the corresponding line of the sub-scenario number in the sound / motor sub-scenario table.
If these sound data do not exist, the process ends.

On the other hand, if any of these sound data exists, the effect control CPU 200 determines whether or not it is BGM in step S801. If the sound data is BGM, the effect control CPU 200 sets the sound data of the sound / motor sub-scenario table to the sound channel aCH0 in step S806. That is, the BGM information described in the corresponding line of the sub-scenario number in the sound / motor sub-scenario table is registered in the sound channel aCH0 as the sound channel aCH associated with the BGM in the sound data registration information.
As described above, when the sound data is BGM, SE1, SE2, or an error sound, the description content (that is, scenario data) includes at least the phrase number of the phrase to be reproduced and the information of the primary volume. Therefore, these pieces of information are registered in the sound data registration information.
Note that BGM can be played back in stereo, and in that case, the BGM information in the sound / motor sub-scenario table is instructed. As described above, when BGM is reproduced in stereo, not only the sound channel aCH0 but also the sound channel aCH1 is used. In this case, in both of these sound channels aCH0 and aCH1, a common phrase number described in the BGM information is registered as a phrase number (frzHi, frzLo), and “1” is stored as stereo (frzSt) information. Described.

  If BGM sound data is set in step S806, or if the sound data is not BGM in step S801, the effect control CPU 200 determines whether the sound data is an error sound in step S802, and is an error sound. In this case, the sound data of the sound / motor sub-scenario table is set in the sound channel aCH15 in step S807. That is, information corresponding to the description content of the sub-scenario data is registered in the sound channel aCH15 as the sound channel aCH corresponding to the error sound.

When the sound data of the error sound is set in step S807, or when the sound data is not an error sound in step S802, the effect control CPU 200 determines whether the sound data is SE1 in step S803, and is SE1. In this case, SE1 setting processing is performed in step S808.
If the SE1 setting process is executed in step S808, or if the sound data is not SE1 in step S803, the effect control CPU 200 determines whether the sound data is SE2 in step S804, and is SE2. In this case, the SE2 setting process is performed in step S809.
Further, when the SE2 setting process is executed in step S809, or when the sound data is not SE2 in step S804, the effect control CPU 200 determines whether or not the sound data is sound control in step S805. If there is, sound control setting processing is performed in step S810.
If the sound control setting process is executed in step S810, or if the sound data is determined not to be sound control in step S805, the effect control CPU 200 ends the process shown in FIG.

  The contents of the SE1 setting process, the SE2 setting process, and the sound control setting process executed in steps S808, S809, and S810 will be individually described below.

First, the contents of the SE1 setting process and SE2 setting process executed in steps S808 and S809, respectively, will be described with reference to FIG.
The contents of the setting process of SE1 and the setting process of SE2 are the same except that the sound channel aCH (corresponding sound channel aCH) to which sound data is to be registered is different, so the description in FIG. And

First, the effect control CPU 200 acquires the reproduction state of the corresponding sound channel aCH in step S901. As described above, in the present embodiment, the correspondence of the sound channel aCH to be registered is determined for each sound type. In the case of SE1, the sound channels aCH2 to aCH9 are set, and in the case of SE2, the sound channels aCH10 to aCH14 are set. Are the corresponding sound channels aCH.
Therefore, the process of step S901 is a process of acquiring the playback state of the sound channels aCH2 to aCH9 when executed as the SE1 setting process (S808), and the sound channel when executed as the SE2 setting process (S809). This is a process of acquiring the playback state of aCH10 to aCH14.
Acquisition of the reproduction state of each sound channel aCH, that is, acquisition of information on whether or not a phrase is being reproduced, is performed by acquiring the value of a reproduction state information storage register provided for each sound channel aCH in the sound source IC 59. .

Next, in step S902, the effect control CPU 200 sets the set sound channel aCH as the start sound channel aCH. Here, the set sound channel aCH means a sound channel aCH that is a target of sound data registration. The start sound channel aCH means the sound channel aCH having the smallest channel number among the corresponding sound channels aCH, and corresponds to aCH2 in the case of SE1 and aCH10 in the case of SE2.
In step S902, the set sound channel aCH is set as the start sound channel aCH in order to search for an empty channel in order from the start sound channel aCH and register SE sound data by the processing in steps S903 to S911.

In step S903, the effect control CPU 200 determines whether or not the set sound channel aCH is being reproduced. If the set sound channel aCH is being reproduced, the set sound channel aCH is incremented by 1 in step S908, and whether or not the set sound channel aCH is larger than the end channel is determined in step S909. The end channel means the sound channel aCH having the largest channel number among the corresponding sound channels aCH. Therefore, in the case of SE1, whether or not it is larger than the sound channel aCH9, and in the case of SE2, it is larger than the sound channel aCH14. Whether or not each is determined.
If the set sound channel aCH is larger than the end channel, the corresponding sound channel aCH is empty, and the process ends.
On the other hand, if the set sound channel aCH is not larger than the end channel, the process returns to step S903 (that is, it is determined whether or not the next sound channel aCH is being reproduced).

If it is determined in step S903 that the set sound channel aCH is not being reproduced, the effect control CPU 200 proceeds to step S904, and determines whether there is no sound data in the work of the set sound channel aCH.
If there is sound data in the set sound channel aCH, that is, if the set sound channel aCH is not empty, the effect control CPU 200 proceeds to step S908. In other words, this searches for the next empty channel in the corresponding sound channel aCH.

On the other hand, if there is no sound data in the set sound channel aCH, that is, it is determined that the set sound channel aCH is empty, the effect control CPU 200 proceeds to step S905 and determines whether or not there is a stereo request. That is, with reference to information indicating whether or not stereo playback is included in the SE information of the table, it is determined whether or not the SE information is accompanied by a request for stereo playback. As described above, in the scenario data for requesting stereo reproduction, individual phrase numbers of Lch and Rch are not described, but one common phrase number is described.
If there is no stereo request, the effect control CPU 200 proceeds to step S910, sets the sound data of the table in the work area corresponding to the set sound channel aCH, and ends the process.

On the other hand, if there is a stereo request, the effect control CPU 200 proceeds to step S906 and determines whether or not the set sound channel aCH is an even channel. If the set sound channel aCH is not an even channel, the effect control CPU 200 proceeds to step S908 and increments the set sound channel aCH by one. That is, an empty channel is searched after the next sound channel aCH.
Here, as described above, in this example, stereo reproduction is performed using the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn + 1. Therefore, according to the scenario data requesting stereo reproduction. The sound data such as the phrase number described in the scenario data should be set to the even sound channel aCHn and the next odd sound channel aCHn + 1. For this reason, if the set sound channel aCH is not an even channel, an empty channel is searched after the next sound channel aCH as described above.

On the other hand, if the set sound channel aCH is an even channel, the effect control CPU 200 proceeds to step S907 and determines whether or not the next sound channel aCH of the set sound channel aCH is also an empty channel (including an empty channel including that not being played). Whether or not there is).
If the sound channel aCH next to the set sound channel aCH is not an empty channel, the process proceeds to step S908. That is, the next empty channel in the corresponding sound channel aCH is searched.
On the other hand, if the next sound channel aCH of the set sound channel aCH is an empty channel, the process proceeds to step S911, and the sound data in the table is set in the work area corresponding to the set sound channel aCH and the next sound channel aCH, respectively. Then, the process ends.

Through the above SE setting process, the sound data of SE1 or SE2 described in the sub-scenario table is registered in an empty channel among the corresponding sound channels aCH in the sound data registration information.
Further, when the information of SE1 or SE2 requests stereo playback of a phrase, this corresponds to the case where the sound source IC 59 requests to use an even channel and the next odd channel for stereo playback. Sound data can be properly registered in the even channel and the next odd channel in the corresponding sound channel aCH. In other words, this makes it possible to perform appropriate information registration according to the specifications of the sound source IC 59.

Next, the sound control setting process executed as step S810 of FIG. 24 will be described with reference to FIGS.
FIG. 26 shows the sound control setting process in step S810.
First, the effect control CPU 200 confirms the value of the upper 1 byte of the sound control information in step S1001.

FIG. 27 shows an example of the data structure of sound control information.
In the case of the present embodiment, the sound control information is composed of 4 bytes, information (control type information) for describing the sound control content is described in the upper 1 byte, and the sound control target is described in the lower 3 bytes. Information for designating the sound channel aCH (information to be controlled) is described.
Depending on the control type information of the upper 1 byte, fade-in reproduction, fade-out reproduction, and secondary volume change instruction can be made.

As shown in the figure, as the control type information represented by the upper 1 byte, 0x20 to 0x70 are fade-type information, and 0x80 or more is secondary volume change instruction information.
Specifically, as for the fade system information from 0x20 to 0x70, 0x25 (SFO1M) is "fade-out slow mute", 0x35 (SFO2M) is "fade-out normal mute", 0x45 (SFO3M) is "fade-out mute", 0x20 (SFO1) is “fading out slowly”, 0x30 (SFO2) is “fading out normal”, 0x40 (SFO3) is “fading out quickly”, 0x50 (SFI1) is “fading in slowly”, 0x60 (SFI2) “Fade in normal” and 0x70 (SFI3) means “Fade in fast”.
Here, “slow”, “normal”, and “fast” mean the volume transition speed (speed) in the fade control. The difference between “mute” and “sound volume” for fade-out is whether or not the volume after transition is “0”.

  As the change instruction information of the secondary volume of 0x80 or higher, 0x80 (SVO8), 0x81 (SVO0), 0x82 (SVO2), and 0x83 (SVO4) are secondary volumes = 0x80 (MAX) and 0x00 (0), respectively. , 0x20, 0x40. Then, 0x90 (SVO8E) represents the secondary volume of all sound channels aCH (aCH0 to aCH14) other than the error = 0x80, and 0x91 (SVO0E) represents the secondary volume of all sound channels aCH other than the error = 0x00. .

  The lower 3 bytes of the sound control information are 0x110000 (BG_T) for sound channel aCH0 (BGM), 0x220,000 (YK1_T) for sound channels aCH2 to aCH9 (SE1), and 0x330000 (YK2_T) for sound channels aCH10 to aCH14 (SE2). ), 0x440000 (YKA_T) represents the sound channel aCH2 to aCH14 (SE1 + SE2 = all SEs), and 0x00 ---- (other) represents the sound channel aCH reproducing the phrase indicated by “----”.

  In step S1001 of FIG. 26, the production control CPU 200 confirms the value of the upper 1 byte of the sound control information having the above data structure, and the value of the upper 1 byte is less than 80h (0x80), 80h or more and less than 90h. , 90h or more is confirmed. This is equivalent to confirming whether the control type is a fade type, a simple secondary volume change instruction, or a secondary volume change instruction with designation of all sound channels aCH other than errors.

In the case of 80h or more and less than 90h, the effect control CPU 200 sets the secondary volume of the sound channel aCH indicated by the lower 3 bytes of the sound / motor sub-scenario table (sound control information) to the volume value indicated by the upper 1 byte in step S1002. To finish the process.
If it is 90h or more, the effect control CPU 200 sets the secondary volume of the sound channels aCH0 to aCH14 to the volume value indicated by the upper 1 byte in step S1003 and ends the process.

  On the other hand, if the upper 1 byte is less than 80h, the effect control CPU 200 performs the process of converting to control data corresponding to the value of the upper 1 byte in step S1004, and then in step S1005 the sound / motor sub-scenario table ( The converted control data is set in the work area corresponding to the sound channel aCH indicated by the lower 3 bytes of the sound control information), and the process ends.

  Here, the fade-type control information whose upper 1 byte is less than 80h is information for identifying only the difference in the control type such as “fade out slowly mute” or “fade in quickly”. Therefore, the information of the control type of the upper 1 byte is converted into information that allows the sound source IC 59 to execute the corresponding operation in step S1004.

FIG. 28A shows the contents of the conversion process in step S1004 of FIG.
First, the effect control CPU 200 acquires a 2-byte value corresponding to the higher-order 1-byte value from the conversion table in step S1101. In step S1102, a 2-byte value is acquired based on the lower 3 bytes.
In step S1103, the 2-byte values acquired in steps S1101 and S1102 are concatenated.

FIG. 28B is an explanatory diagram of the acquisition process of steps S1101 and S1102 described above.
First, in the acquisition process of step S1101, a conversion table storing the corresponding value (2 bytes) for each value (0x25 to 0x70) of the upper 2 bytes of the fade system is used as shown in the figure. The effect control CPU 200 refers to the conversion table and acquires a 2-byte value corresponding to the higher-order 1-byte value.
In the acquisition process in step S1102, the control target is other than SE1 and SE2 (that is, other than aCH2 to aCH14: other than the warning sound) and SE1 and SE2 based on the value of the lower 3 bytes of the sound control. , 2 byte values as shown in the figure are acquired. That is, it is 0xD000 in cases other than SE1 and SE2, and 0xC000 in cases of SE1 and SE2.
As will be described later, the acquisition value differs depending on whether the control target is either SE1 or SE2 or not, because the fade control is set to monaural only for SE1 and SE2. Because.
The 2-byte values thus obtained are concatenated in step S1103 to obtain 4-byte control data.

FIG. 28C illustrates the correspondence between the sound control fade system information and the control data obtained by the conversion processing of FIG. 28A according to the information content (value).
Here, in this embodiment, the control data of a total of 4 bytes obtained by the conversion process of FIG. 28A is set (registered) as it is in the sound data registration information. In this sense, in the figure, the control data obtained by the conversion process of FIG. 28A is indicated as “data to be set in the sound data registration information”.
According to FIG. 28C, as information about fade-type sound control, for example, information in which the upper 1 byte = SFO1M (fading out slowly mute) and the lower 3 bytes = BG_T is converted to control data “0x2000D000” by the above conversion process. It turns out that it is converted. Also, for example, the sound control information in which the upper 1 byte = SFO3M (fading out quickly mute) and the lower 3 bytes = YK1_T is converted into control data “0xFF00C000”.

Referring to FIG. 17, in the sound data registration information, the first byte is “primary volume transition amount”, the second byte is “primary volume”, the third byte is “transition amount change”, “volume change”, and “phrase change”. “Stereo” “Loop” (1 bit each so far) and “Phrase number hi” (3 bits), and the fourth byte is “Phrase number low”.
As described above, in the present embodiment, the converted control data is set in the sound data registration information as it is. Therefore, for example, according to the control data (0x2000D000) of the sound control information of SFO1M + BG_T described above, the registered content of the sound data registration information is ,
“Primary volume transition amount” = “0x20”
“Primary volume” = “0x00”
“Transition amount change” = “1”
"Volume change" = "1"
“Phrase change” = “0”
"Stereo" = "1"
"Loop" = "0"
“Phrase number hi” = “000”
“Phrase number low” = “0x00”
It becomes.
For example, according to the control data (0xFF00C000) of the sound control information of SFO3M + YK1_T described above, the registration content of the sound data registration information is
“Primary volume transition amount” = “0xFF”
“Primary volume” = “0x00”
“Transition amount change” = “1”
"Volume change" = "1"
“Phrase change” = “0”
"Stereo" = "0"
"Loop" = "0"
“Phrase number hi” = “000”
“Phrase number low” = “0x00”
It becomes.

  When the control target is other than SE1 or SE2 as in the former example, “1” (stereo) is set to “stereo”, and the control target is SE1 (same for SE2) as in the latter example. In this case, “0” (monaural) is set in “stereo”. As understood from this point, monaural designation for the above-described SE fade control is realized.

As described above, in the present embodiment, for fade type sound control information, information indicating only the difference in fade control is described as the control type information, and this is converted by the above conversion processing. Thus, the data is converted into data that can be registered in the sound data registration information (that is, data required for the sound source IC 59 to execute the fade control).
Here, fade control such as “slow mute fade out” and “fast fade in” can be realized by preparing sub-scenario data that gradually changes the volume over time. Will hold sub-scenario data for each hour, which requires more memory capacity. On the other hand, according to the present embodiment that performs the conversion processing as described above, the sub-scenario data may simply describe information representing only the difference in fade control such as “fade out slowly mute” and “fade in fast”. The number of sub-scenario data required for a kind of fade control can be reduced to one, and as a result, the memory capacity for holding the sub-scenario data can be reduced.

Further, if the conversion process as described above is performed, even if the specification of the sound source IC 59 is changed, it can be handled only by changing the contents of the conversion table shown in FIG. 28B. There is no need to rewrite or rewrite the program. Therefore, it is possible to flexibly cope with a change in the specification of the sound source IC 59 and to reduce a work load for dealing with a change in the specification of the sound source IC 59.
Also, when a specific volume transition amount or the like is changed as a fade-in / out, it is only necessary to change the contents of the conversion table shown in FIG. 28B. Similarly, the sub-scenario data is rewritten or the program is rewritten. It is possible to reduce the work load related to the change.

Here, referring to FIG. 29, an example of use of fade-type sound control information will be described.
In the example of FIG. 29, as sub-scenario data of sound / motor sub-scenario number 001 in the sound / motor sub-scenario table, BGM is faded in the form of “fading out quickly, small sound” (SFO3 + BG_T) at time = 0. , SE1 phrase 0001 is played at volume 0x80 at time = 0 to 2000, SE1 phrase 0002 is played at stereo volume 0x80 at time = 2000 to 5000, and BGM is "fade in slowly" at time = 5000 (SFI1 + BG_T) The case where the information to be faded is described is described.
As also shown in the figure, the phrase end timing is the time when the sound data as the phrase ends.

The scenario update process, the sub-scenario update process, and the sound data registration process described with reference to FIGS. 14, 15, and 24 to 28 are executed, so that first, the sound control information described in the time = 0 line ( Control data corresponding to SFO3 + BG_T) and SE1 information (0x00806001) described in the time = 0 line are set in the sound data registration information. For confirmation, according to the processing shown in FIGS. 14, 15, and 24, the data described in the same time = 0 line is set at once for the sound data registration information. (It is set at a time in the “sound registration process (S635)” of FIG. 15).
By the sound reproduction process (S111) in the main process of FIG. 8, the information set in the sound data registration information is sequentially output to the sound source IC 59, and the sound output according to the sub-scenario data is realized. As a result, BGM fade-out and phrase 0001 reproduction as shown in the lower part of the figure are realized.

In response to time = 2000, SE2 information (0x00807002) described in the line of time = 2000 is registered in the sound data registration information, and this registration information is stored in the sound source IC 59 in the sound reproduction process in step S111. Are sequentially output, the reproduction of the phrase 0002 is started from time = 2000 as shown in the lower part of the figure.
Further, when time 5000 is reached, control data corresponding to the sound control information (SFI1 + BG_T) described in the line of the time = 5000 is registered in the sound data registration information, and this registration information is stored in step S111. By sequentially outputting to the sound source IC 59 in the reproduction process, BGM fade-in at time = 5000 as shown in the figure is realized.

Here, depending on the information of the sound control, as described with reference to FIG. 27, it is also possible to give an instruction to change the secondary volume of the phrase reproduced on the designated sound channel CHa.
An example of volume control based on a secondary volume change instruction will be described with reference to FIG.
FIG. 30 is an explanatory diagram of a control example in which a predetermined type of sound is muted by the secondary volume. Specifically, when a scenario for reproducing the phrase 0010 of SE1 is registered during BGM reproduction, An example in which BGM is muted by the next volume is shown.
In this example, there are two lines of time = 0 in the sub-scenario table, and “SVO0 + BG_T” (see FIG. 27) is described as sound control information in one line of time = 0. The other time = 0 line describes “0x0080700A” (stereo reproduction of phrase 0010 with primary volume 0x80) as SE1 information.
When there are two lines having the same time as described above, the description information of these lines is sequentially converted into the sound data registration information by the processing shown in FIGS. 14, 15, and 24. Will be registered. In response to these pieces of registration information, mute by the secondary volume of BGM as shown in the figure and playback of the phrase 0010 as SE1 are started corresponding to time = 0.
In the example of this figure, “SVO8 + BG_T” (secondary volume = 0x80) is described as the sound control information in the line of time = 5000, and as a result, the BGM mute state is canceled after time = 5000 as shown in the figure. Is done.

  As described above, according to the present embodiment in which the secondary volume of the designated sound channel aCH can be changed by the sound control information, when a certain type of sound is being reproduced, the priority is high later. When another sound is to be reproduced, it is possible to easily reproduce and output a high priority sound without giving an instruction to stop the reproduction of the sound being reproduced. Therefore, sound priority control can be easily realized.

Here, the priority control for BGM and other sounds has been exemplified above, but in this embodiment, the sounds as SE are classified into SE1 and SE2, that is, SE1 and SE2 are separated into separate sounds. Therefore, for these SE1 and SE2, sound priority control can be realized by controlling the secondary volume based on sound control information.
As described above, the classification of SE1 and SE2 is classified according to the appearance frequency of the effect. Therefore, in the case where the sound of SE1 having a lower appearance frequency (higher reliability) is to be reproduced later while the sound of SE1 having a higher appearance frequency (that is, low reliability) is being reproduced, FIG. By controlling the secondary volume based on the sound control information as in the example, SE1 being reproduced can be muted, and SE2 can be preferentially output.

In addition, since the volume control can be performed not only by the primary volume but also by the secondary volume, the mute control as shown in FIG. 30 can be appropriately realized.
Here, when the BGM mute control as shown in FIG. 30 is to be realized using only the primary volume, for example, by performing fade-out with the transition speed as fast as possible based on the sound control information, during playback. It is conceivable to silence the BGM.
However, as described above, the primary volume is a volume value that is set in the sound source IC 59 together with the phrase number when the reproduction of the phrase is started. For this reason, even if the sound is silenced by the primary volume using the sound control information as described above, the timing (X) in FIG. If the start of BGM playback is newly instructed by another scenario at the previous timing), the BGM volume is set to a required volume other than 0x00 at the time of the “X”, and the BGM is emitted. End up.
On the other hand, according to the present embodiment in which the volume control by the secondary volume is also possible, as described with reference to FIG. 30, once the secondary volume of the BGM is controlled to 0x00 by the sound control information, Even if a new BGM playback is started before the sound control for returning the secondary volume is performed and the primary volume is set to a volume other than 0x00, the output volume can be maintained at 0x00. . Thereby, the sound volume control as shown in FIG. 30 can be appropriately realized.

[4-8: Sound reproduction processing]

Next, the sound reproduction process executed as step S111 in FIG. 8 will be described.
As described above, the sound reproduction process is a process for causing the sound source IC 59 to output a sound based on information set in the work as the sound data registration information.

FIG. 31 is an explanatory diagram of sound reproduction processing.
First, the effect control CPU 200 performs steps S1200 to S1220 for each of the sound channels aCH0 to aCH15 of the sound data registration information as the loop process LP3. Hereinafter, the sound channel aCH to be processed will be described as “aCHn”.

In step S1200, the effect control CPU 200 confirms the volume MAX error flag. Note that the volume MAX error flag is a flag set in the error processing (see FIG. 8) in the previous step S106. As described above, 0x5A indicates that a volume MAX error is occurring, and 0x00 is occurring. It represents that it is not.
If the volume MAX error flag is 0x5A, the process proceeds to step S1221, and the secondary volume of the work is rewritten to sound channel aCH0-14 (other than error sound) = 0x00, sound channel aCH15 (error sound) = 0x80, and step S1201 is performed. move on.
On the other hand, if the volume MAX error flag is 0x00, the process proceeds to step S1201 without rewriting the work secondary volume in step S1221.

In step S1201, the effect control CPU 200 outputs the value of the secondary volume to the target sound channel aCHn. That is, the value of the secondary volume set in the sound channel aCH of the sound data registration information is output to the secondary volume register for the sound channel aCHn in the sound source IC 59.
As described above, the value of the secondary volume is normally set in the all sound channel aCH of the sound data registration information as a value corresponding to the state of the volume switch. Alternatively, as a scenario, when the sound control information for instructing the change of the secondary volume of a certain sound channel aCH is described, the value of the secondary volume described in the sound control information is the sound data. It is set to the sound channel aCH indicated by the sound control information in the registration information. If the volume MAX error is occurring, “0” is set for the sound channel aCH0 to 14 and the MAX value is set for the sound channel aCH15 by the process of step S1221.

  Next, the effect control CPU 200 outputs the value “0x00” to the SUB volumes 0 and 1 in step S1202. That is, the value “0x00” is output to each register of “SUB volume 0” and “SUB volume 1” of the sound channel aCHn. As described above, the SUB volume is not used in this embodiment.

  In step S1203, the effect control CPU 200 determines whether there is sound data (sound data other than the secondary volume) in the work sound channel aCHn. If there is no sound data, the process for the sound channel aCHn ends.

On the other hand, if there is sound data, the process proceeds to step S1204 to determine whether or not it is a replacement request.
Here, in the present embodiment, a phrase replacement request can be made using the value of the upper 2 bytes (“primary volume transition amount” and “primary volume”) of the sound data registration information shown in FIG. ing. Specifically, if the upper 2 bytes of the sound data registration information is a predetermined value (for example, “0x5A5A” in this example), it is interpreted as a phrase replacement request.
In step S1204, it is determined whether or not it is a phrase replacement request by determining whether or not the upper 2 bytes of the data set in the sound channel aCHn is a predetermined value “0x5A5A”.

If it is a replacement request, the effect control CPU 200 rewrites the phrase number in step S1205, and proceeds to step S1206. The phrase number is rewritten by outputting the values of “phrase number hi” and “phrase number low” of the data set in the sound channel aCHn to the phrase number register of the sound channel aCHn of the sound source IC 59.
On the other hand, if it is not a replacement request, the process proceeds to step S1206 without going through step S1205.

In step S1206, the effect control CPU 200 determines whether there is a transition amount change request or a volume change request. That is, it is determined whether or not “1” is set in either the transition amount change rsv2 or the volume change rsv1 of the sound channel aCHn.
Here, the value of the transition amount change rsv2 in the sound data registration information is set to “1” when the sound registration process (S635) is executed based on the fade-type sound control information, and other than the fade-type information. In other words, “0” is set when the sound registration process is executed based on the sound control information (ie, secondary volume change instruction), BGM, SE1, SE2, and error sound information. .
On the other hand, the volume change rsv1 (whether or not to change the primary volume) is not limited to the case where the sound registration process is executed based on the fade sound control information, and the BGM, SE1, SE2, error sound information, “1” is set when the sound registration processing is executed based on the information of the fade-type sound control. Then, “0” is set when the sound registration process is executed based on the sound control information other than the fade system.
As understood from these points, not only when sound data based on fade-type sound control information is registered, but also when sound data based on BGM, SE1, SE2, and error sound information is registered. Even in the case where there is, the primary volume transition amount and the information of the primary volume are output to the sound source IC 59 by the subsequent steps S1209 or S1211.

If there is a transition amount change request or a volume change request, the effect control CPU 200 proceeds to step S1207 and determines whether or not the sound channel aCHn is stereo reproduction, that is, whether or not the value of the stereo frzSt is “1”. To do.
If the sound channel aCHn is not stereo playback, the process proceeds to step S1209 to output the primary volume transition amount and the primary volume to the sound channel aCHn of the sound source IC 59, and further output the panpot to the sound channel aCHn of the sound source IC 59 in step S1210. And go to step S1213.
Here, as the output of the pan pot, the value is output to each register of “left / right pan pot”, “left / right pan pot transition amount”, “up / down pan pot”, and “up / down pan pot transition amount” for the sound channel aCHn in the sound source IC 59. To do. In this example, the pan function of the sound source IC 59 is not used. Therefore, in step S1210, all “0” (0x00) are output.

On the other hand, if the sound channel aCHn is stereo reproduction, the process proceeds to step S1208 to determine whether or not the sound channel aCHn is an even number.
If the sound channel aCHn is an even number, the process proceeds to step S1211, and the primary volume transition amount and the primary volume are output to the sound channel aCHn and the sound channel aCHn + 1. And proceeds to step S1213.

In this embodiment, the “left and right panpot” registers of the even-numbered sound channel aCHn and the next odd-numbered sound channel aCHn + 1 are used for the stereo reproduction instruction. Specifically, the sound source IC 59 in this case is a “left and right panpot” of the even sound channel aCHn (corresponding to the Lch side of stereo reproduction) and the next odd sound channel aCHn + 1 (corresponding to the Rch side of stereo reproduction). By setting predetermined values in the registers, the sound channel aCHn and the sound channel aCHn + 1 are configured to recognize that they are stereo reproduction. More specifically, in the sound source IC 59 in this case, “0x81” is set in the “left and right panpot” register of the even sound channel aCHn, and the “left and right panpot” register of the next odd sound channel aCHn + 1 is set. Is set to “0x82”, it is configured to recognize that the sound channel aCHn and the sound channel aCHn + 1 are in stereo reproduction.
In response to this, in step S1212, as a panpot output process for the sound channel aCHn and the sound channel aCHn + 1, “0x81” is set in the “left and right panpot” register of the sound channel aCHn, and “left and right panning of the sound channel aCHn + 1”. “0x82” is output to the “pot” register.
As described above, since the panning function of the sound source IC 59 is not used in the present embodiment, in step S1212 “left / right panpot transition amount”, “upper / lower panpot”, “upper / lower panpot transition amount” other than “left / right panpot”. “0x00” is output to each of the registers.

If the sound channel aCHn is not an even number in step S1208, the process proceeds to step S1220, the sound data of the work sound channel aCHn is cleared, and the process for the sound channel aCHn is ended.
That is, when the sound channel aCHn is stereo reproduction and is an odd number, the phrase number registered in the sound channel aCHn is not output to the sound source IC 59 (note that the primary volume transition amount and the primary volume are even numbers. The registration sound data of the sound channel aCHn is cleared (already output in S1211, which is the process for aCHn). Since the sound source IC 59 in this case specifies the phrase data of Lch and Rch to be reproduced based on the phrase number set in the processing for the even sound channel aCHn, it is registered in the odd sound channel aCHn + 1 of the work. There is no need to specify the phrase number to the sound source IC 59.

  If there is no transition amount change request or volume change request in the previous step S1206, the presentation control CPU 200 proceeds to step S1213 without passing through the processing of steps S1207 to S1212.

In step S1213, the effect control CPU 200 determines whether or not there is a phrase change request, that is, whether or not the value of the phrase change rsv0 is “1”.
If there is no phrase change request, the sound data of the sound channel aCHn is cleared in step S1220, and the process for the sound channel aCHn is ended. That is, when there is no phrase change request, the phrase number set in the work sound channel aCHn is not output to the sound source IC 59 (S1215).

  On the other hand, if there is a phrase change request, it is determined in step S1214 whether or not the sound channel aCHn is stereo and odd. If the sound channel aCHn is stereo and odd, the sound data of the sound channel aCHn is cleared in step S1220, and the process for the sound channel aCHn is ended.

If the sound channel aCHn is not stereo and odd in step S1214, the process proceeds to step S1215 to output the phrase number to the sound channel aCHn. That is, the phrase number information composed of the phrase number hi and the phrase number low registered in the work sound channel aCHn is output to the phrase number register for the sound channel aCHn of the sound source IC 59.

  In the next step S1216, the effect control CPU 200 determines whether or not there is a loop request, that is, whether or not the value of the loop frzLp is “1”. If there is a loop request, the loop count 0xFF (infinite loop) is output to the sound channel aCHn of the sound source IC 59 in step S1217 and the process proceeds to step S1219. If there is no loop request, the loop count 0x00 is set to the sound channel aCHn of the sound source IC 59 in step S1218. (No loop) is output and the process proceeds to step S1219.

In step S1219, the effect control CPU 200 issues a playback output instruction for the sound channel aCHn. That is, a reproduction instruction based on the data set in the sound channel aCHn is given to the sound source IC 59.
Next, the effect control CPU 200 clears the sound data of the work sound channel aCHn in step S1220, and ends the process for the sound channel aCHn.

The effect control CPU 200 sequentially performs the processes of steps S1201 to S1220 described above from the sound channels aCH0 to aCH15 by the loop process LP3. Thereby, the sound reproduction process of step S111 is completed.
By such sound reproduction processing, sound output based on information registered in the sound data registration information is executed, and sound production according to the scenario is realized.

  Here, as described above, in the present embodiment, a stereo reproduction instruction is given to the sound source IC 59 by setting a predetermined value in the “left and right panpot” registers of the even-numbered and next odd-numbered sound channels aCH. However, this makes it possible to properly instruct stereo reproduction / monaural reproduction without providing the sound source IC 59 with a register for instructing stereo reproduction / monaural reproduction. That is, the number of registers of the sound source IC 59 can be reduced. At the same time, since the stereo reproduction / monaural reproduction instruction to the sound source IC 59 can be realized by the output process of the pan pot, it is not necessary to separately perform the stereo reproduction / monaural reproduction instruction process, and the processing load is reduced accordingly.

  By the way, in the sound reproduction process of FIG. 31, the volume MAX error flag is confirmed each time in step S1200, and if the volume MAX error is occurring, the secondary volume of the work is rewritten in step S1221. Will be described with reference to FIG.

FIG. 32 is an explanatory diagram of volume control according to the occurrence of an error.
FIG. 32A shows the state of occurrence of the volume MAX error, and the period from the time point t1 to t2 is the occurrence period of the volume MAX error as shown in the figure.
32B to 32E show cases in which phrases are played back in different playback periods, and in the case of FIG. 32B as shown in the figure, the phrase playback period is from time point t0 (time point before time point t1) to time point tn (time point). In the case of FIG. 32C, the phrase playback period is from the time point tn to the time point t3 (time point after the time point t2), and in the case of FIG. 32D, the phrase playback period is from the time point t0 to the time point t3. In the case of 32E, the phrase reproduction period is the time point tn1 to the time point tn2 (the time point between the time points t1 and tn2 between the time points t1 and tn2). In addition, the phrase said here shall mean phrases other than an error sound.
32B to 32E, it is assumed that sound control information for controlling the secondary volume of the phrase is also described as a scenario. The figure also shows the state of the secondary volume (“secondary volume state” in the figure). Note that “0x **” means a value of the secondary volume that is larger than “0x00” and smaller than “0x80”.
As described above, the value of the work secondary volume is normally set according to the state of the volume switch. In the example of this figure, it is assumed that the value corresponding to the state of the volume switch is “0x80”.

In the case of FIG. 32B, in response to the fact that the sound control information for controlling the secondary volume to “0x **” is registered in the work at the timing corresponding to the time point t0, the secondary volume of the phrase corresponds to the time point t0. The timing is lowered from “0x80” to “0x **”. If the volume MAX error does not occur, the secondary volume of the phrase is maintained at “0x **” after time t0.
However, in this case, in response to the occurrence of the volume MAX error at time t1, the secondary volume is forcibly lowered to “0x00” at the timing corresponding to time t1 as shown in the figure. This is because the value of the secondary volume other than the work sound channel aCH15 is rewritten to “0x00” in step S1221 of FIG. 31 in accordance with the occurrence of the volume MAX error.
If a volume MAX error is occurring, the rewriting process in step S1221 is performed every 16 ms. For this reason, even after time t1, the secondary volume of the work (sound channel aCH other than the error sound) is set to “0x00” each time, and this is output to the sound source IC 59, so that the secondary volume is maintained at “0x00”. The
At this time, at the time tn when the reproduction of the phrase ends, the effect control CPU 200 sets a value corresponding to the state of the volume switch as the value of the secondary volume of the sound channel aCH (work) corresponding to the phrase. . Therefore, there is a concern that the mute state of the sound channel aCH is canceled at time tn. However, even in this case, the volume rewriting process in step S1221 is executed in the sound reproduction process shown in FIG. By rewriting, “0x00” can be instructed to the sound source IC 59 as the secondary volume. This reliably prevents the phrase from being emitted by setting a value greater than “0x00” as the secondary volume during the volume MAX error occurrence period.

Subsequently, in the case of FIG. 32C, the reproduction of the phrase is started at time tn after time t1 when the error occurs. In this case, in the period up to time t1, the value of the secondary volume of the work was “0x80” corresponding to the volume switch state. The value of the secondary volume is rewritten to “0x00”.
Here, although not reflected in the figure, in this case, since the sound control information for controlling the secondary volume of the phrase is described as a scenario, at the time tn when the reproduction of the phrase is started, the phrase in the work The value of the secondary volume of the sound channel aCH corresponding to is set to the value indicated by the sound control information. However, in this case as well, by executing the rewriting process in step S1221 in the sound reproduction process, the value of the secondary volume that is finally output to the sound source IC 59 can be set to “0x00”. It is reliably prevented that the next volume is set to a value larger than “0x00” and the phrase is emitted.
In the case of FIG. 32C, the phrase reproduction period is also after time t2, but at time t2, the value of the secondary volume of the work is a value corresponding to the volume switch state (in this case, “0x80”). Set to At time t2, the rewriting process in step S1221 is not executed after time t2 in response to the volume MAX error flag changing to “0x00”. From these points, after time t2, “0x80” is output to the sound source IC 59, and as a result, the phrase is properly emitted after the error is resolved.

In the case of FIG. 32D, the reproduction of the phrase is started at time t0, and the secondary volume of the phrase is controlled from “0x80” to “0x **” based on the sound control information.
Also in this case, in the period t1 to t2 which is an error occurrence period, the value of the secondary volume of the work is rewritten to “0x00” every time by the process of step S1221, and thus the phrase is muted during the error occurrence period.
At time t2, the value of the secondary volume of the work is set to a value (“0x80”) corresponding to the state of the volume switch, and the volume MAX error flag changes to “0x00”. Thus, the phrase is properly emitted after time t2 when the error is resolved.

In the case of FIG. 32E, the value of the secondary volume of the work is “0x80” in the period up to the time point t1, but in the period after the time point t1 according to the occurrence of an error, the work 2 is processed by the process in step S1221. The value of the next volume is “0x00”.
In the case of FIG. 32E, the reproduction of the phrase is started at the time tn1 after the time t1, but even if the value of the secondary volume indicated by the sound control information is set to the work at the time tn1, The value of the secondary volume of the work is rewritten to “0x00” by the process of step S1221, so that the phrase is not emitted. When the phrase playback period ends at time tn2, the value of the work secondary volume is rewritten to a value corresponding to the volume switch. However, the value of the work secondary volume is changed to “ Since “0x00” is rewritten, the phrase is not emitted during the period from the time point tn2 to the time point t2.
Also in this case, at time t2, the value of the secondary volume of the work becomes a value (“0x80”) corresponding to the state of the volume switch, and the volume MAX error flag changes to “0x00” and the time t2 and thereafter. Since the rewriting process in step S1221 is not executed, the secondary volume returns to “0x80” after time t2 when the error is resolved.

In this way, the volume MAX error flag is confirmed each time in the sound reproduction processing of FIG. 31 (S1200), and if the volume MAX error is occurring, the work secondary volume is rewritten (step S1221). The sound other than the error sound can be reliably silenced during the occurrence of the volume MAX error.

<5. Summary and Modification>

By the processing of the effect control CPU 200 described above, various effect operations can be efficiently realized while reducing the control load. In addition, the memory capacity required for effect control can be reduced.

Note that the present invention is not limited to the examples given in the embodiments, and various modifications and application examples can be considered.
For example, in the above description, an example in which the present invention is applied to a ball game machine such as the pachinko gaming machine 1 has been shown, but the present invention can also be suitably applied to a revolving game machine (so-called slot machine). Is.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 2 Front frame 3 Game board 3a Game area 4 Outer frame 5 Glass door 6 Axle support mechanism 7 Operation panel 8 Upper tray unit 9 Lower tray unit 10 Launching operation handle 11 Patrite switch 12 Direction button 13 Cross key 14 Ball rental Button 15 Card return button 20w, 20b Decorative lamp 25 Speaker 31 Sphere guide rail 32M Main liquid crystal display device 32S Sub liquid crystal display device 33 Symbol display section 41 Upper start opening 42 Ordinary variable winning device 42a Lower start opening 43 General winning opening 44 Gate 45 First special variable winning device 46 Second special variable winning device 50 Main control board 50
51 Production control board 51
52 Liquid Crystal Control Board 53 Dispensing Control Board 54 Launch Control Board 58 Power Supply Board 59 Sound Source IC
60 Operation Unit 61 Frame Driver Unit 62 Panel Driver Unit 63, 64 Decoration Lamp Unit 67 Amplifier Unit 200 Production Control CPU
201 Production control ROM
202 Production control RAM

Claims (2)

A gaming machine that executes at least sound-related production operations accompanying a game,
A sound source playback means capable of simultaneously playing back multiple channel phrases;
Production control means for controlling the reproduction operation of the sound source reproduction means based on the production progress data representing the progress of the production operation to be performed, and
In the performance progress data, a channel for registering sound-related data is predetermined for each type of sound,
At least two types of sound among the types of sound are divided by the reliability of the performance operation accompanied by the output of the sound,
The sound source reproduction means reproduces the designated phrase for each channel at a volume based on the designated first volume and second volume,
The performance progress data includes phrase reproduction instruction information for instructing reproduction of a phrase,
The first volume is volume information that is described in the phrase playback instruction information in the performance progress data and that indicates the volume of a phrase that is instructed to be played back by the phrase playback instruction information.
The second volume is volume information that can be instructed to the sound reproduction means by the effect control means separately from the first volume,
The production control means includes
When outputting the type of sound with high reliability while outputting the type of sound with low reliability , the second volume of the channel that is outputting the type of sound with low reliability is reduced. gaming machine Ru is mute the sound of low the reliability classification by instructing said tone reproduction means. 2. The gaming machine according to claim 1, wherein the number of channels for registering the sound-related data is set to two or more for at least one of the sound types.

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