JP6073479B2 - マルチスレッド処理システムにおいてサブルーチンを実行すること - Google Patents

マルチスレッド処理システムにおいてサブルーチンを実行すること Download PDF

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Publication number
JP6073479B2
JP6073479B2 JP2015531090A JP2015531090A JP6073479B2 JP 6073479 B2 JP6073479 B2 JP 6073479B2 JP 2015531090 A JP2015531090 A JP 2015531090A JP 2015531090 A JP2015531090 A JP 2015531090A JP 6073479 B2 JP6073479 B2 JP 6073479B2
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Prior art keywords
minrc
instruction
thread
value
program
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JP2015531090A
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Japanese (ja)
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JP2015531945A (ja
JP2015531945A5 (enExample
Inventor
チェン、リン
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G06F9/38885—Divergence aspects

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2015531090A 2012-09-10 2013-08-08 マルチスレッド処理システムにおいてサブルーチンを実行すること Expired - Fee Related JP6073479B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/608,668 2012-09-10
US13/608,668 US9229721B2 (en) 2012-09-10 2012-09-10 Executing subroutines in a multi-threaded processing system
PCT/US2013/054148 WO2014039206A1 (en) 2012-09-10 2013-08-08 Executing subroutines in a multi-threaded processing system

Publications (3)

Publication Number Publication Date
JP2015531945A JP2015531945A (ja) 2015-11-05
JP2015531945A5 JP2015531945A5 (enExample) 2016-03-31
JP6073479B2 true JP6073479B2 (ja) 2017-02-01

Family

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JP2015531090A Expired - Fee Related JP6073479B2 (ja) 2012-09-10 2013-08-08 マルチスレッド処理システムにおいてサブルーチンを実行すること

Country Status (6)

Country Link
US (1) US9229721B2 (enExample)
EP (1) EP2893434B1 (enExample)
JP (1) JP6073479B2 (enExample)
KR (1) KR101660659B1 (enExample)
CN (1) CN104603749B (enExample)
WO (1) WO2014039206A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8832417B2 (en) 2011-09-07 2014-09-09 Qualcomm Incorporated Program flow control for multiple divergent SIMD threads using a minimum resume counter
US9256429B2 (en) 2012-08-08 2016-02-09 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system
US9619230B2 (en) * 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US9582321B2 (en) * 2013-11-08 2017-02-28 Swarm64 As System and method of data processing
FR3013869B1 (fr) * 2013-11-22 2016-01-01 Thales Sa Procede de detection des debordements de pile et processeur pour la mise en oeuvre d'un tel procede
US10133572B2 (en) * 2014-05-02 2018-11-20 Qualcomm Incorporated Techniques for serialized execution in a SIMD processing system
GB2529899B (en) * 2014-09-08 2021-06-23 Advanced Risc Mach Ltd Shared Resources in a Data Processing Apparatus for Executing a Plurality of Threads
US9928076B2 (en) * 2014-09-26 2018-03-27 Intel Corporation Method and apparatus for unstructured control flow for SIMD execution engine
US9766892B2 (en) * 2014-12-23 2017-09-19 Intel Corporation Method and apparatus for efficient execution of nested branches on a graphics processor unit
US9921838B2 (en) * 2015-10-02 2018-03-20 Mediatek Inc. System and method for managing static divergence in a SIMD computing architecture
US9928117B2 (en) 2015-12-11 2018-03-27 Vivante Corporation Hardware access counters and event generation for coordinating multithreaded processing
FR3082331B1 (fr) * 2018-06-08 2020-09-18 Commissariat Energie Atomique Processeur mimd emule sur architecture simd
US12405790B2 (en) * 2019-06-28 2025-09-02 Advanced Micro Devices, Inc. Compute unit sorting for reduced divergence
US12314760B2 (en) * 2021-09-27 2025-05-27 Advanced Micro Devices, Inc. Garbage collecting wavefront
US20250306946A1 (en) * 2024-03-27 2025-10-02 Advanced Micro Devices, Inc. Independent progress of lanes in a vector processor

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435758A (en) 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US5522083A (en) * 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
GB2273377A (en) 1992-12-11 1994-06-15 Hughes Aircraft Co Multiple masks for array processors
US5689677A (en) 1995-06-05 1997-11-18 Macmillan; David C. Circuit for enhancing performance of a computer for personal use
US5938762A (en) * 1995-10-06 1999-08-17 Denso Corporation Method and apparatus for performing exception processing routine in pipeline processing
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6889319B1 (en) 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US7454600B2 (en) * 2001-06-22 2008-11-18 Intel Corporation Method and apparatus for assigning thread priority in a processor or the like
US6947047B1 (en) 2001-09-20 2005-09-20 Nvidia Corporation Method and system for programmable pipelined graphics processing with branching instructions
JP2004206692A (ja) * 2002-12-20 2004-07-22 Internatl Business Mach Corp <Ibm> マルチスレッド化プロセッサ・システム上での実行のために、スレッドについての優先順位値を決定する方法および装置
US20050050305A1 (en) 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7477255B1 (en) 2004-04-12 2009-01-13 Nvidia Corporation System and method for synchronizing divergent samples in a programmable graphics processing unit
US7890734B2 (en) * 2004-06-30 2011-02-15 Open Computing Trust I & II Mechanism for selecting instructions for execution in a multithreaded processor
US7890735B2 (en) 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7765547B2 (en) * 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
US7761697B1 (en) 2005-07-13 2010-07-20 Nvidia Corporation Processing an indirect branch instruction in a SIMD architecture
US7543136B1 (en) 2005-07-13 2009-06-02 Nvidia Corporation System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits
US7353369B1 (en) * 2005-07-13 2008-04-01 Nvidia Corporation System and method for managing divergent threads in a SIMD architecture
US7788468B1 (en) 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
JP2007272353A (ja) 2006-03-30 2007-10-18 Nec Electronics Corp プロセッサ装置及び複合条件処理方法
US7617384B1 (en) 2006-11-06 2009-11-10 Nvidia Corporation Structured programming control flow using a disable mask in a SIMD architecture
US8312254B2 (en) * 2008-03-24 2012-11-13 Nvidia Corporation Indirect function call instructions in a synchronous parallel thread processor
US8438554B1 (en) * 2008-12-11 2013-05-07 Nvidia Corporation System, method, and computer program product for removing a synchronization statement
US8615646B2 (en) 2009-09-24 2013-12-24 Nvidia Corporation Unanimous branch instructions in a parallel thread processor
US8539204B2 (en) 2009-09-25 2013-09-17 Nvidia Corporation Cooperative thread array reduction and scan operations
US8850436B2 (en) 2009-09-28 2014-09-30 Nvidia Corporation Opcode-specified predicatable warp post-synchronization
US8832417B2 (en) * 2011-09-07 2014-09-09 Qualcomm Incorporated Program flow control for multiple divergent SIMD threads using a minimum resume counter
US9256429B2 (en) * 2012-08-08 2016-02-09 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system

Also Published As

Publication number Publication date
KR20150054858A (ko) 2015-05-20
EP2893434B1 (en) 2018-03-21
US9229721B2 (en) 2016-01-05
CN104603749A (zh) 2015-05-06
CN104603749B (zh) 2017-09-19
EP2893434A1 (en) 2015-07-15
JP2015531945A (ja) 2015-11-05
US20140075165A1 (en) 2014-03-13
WO2014039206A1 (en) 2014-03-13
KR101660659B1 (ko) 2016-09-27

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