JP2015531945A5 - - Google Patents

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Publication number
JP2015531945A5
JP2015531945A5 JP2015531090A JP2015531090A JP2015531945A5 JP 2015531945 A5 JP2015531945 A5 JP 2015531945A5 JP 2015531090 A JP2015531090 A JP 2015531090A JP 2015531090 A JP2015531090 A JP 2015531090A JP 2015531945 A5 JP2015531945 A5 JP 2015531945A5
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JP
Japan
Prior art keywords
minrc
value
subroutine
resume counter
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015531090A
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English (en)
Japanese (ja)
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JP6073479B2 (ja
JP2015531945A (ja
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Publication date
Priority claimed from US13/608,668 external-priority patent/US9229721B2/en
Application filed filed Critical
Publication of JP2015531945A publication Critical patent/JP2015531945A/ja
Publication of JP2015531945A5 publication Critical patent/JP2015531945A5/ja
Application granted granted Critical
Publication of JP6073479B2 publication Critical patent/JP6073479B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015531090A 2012-09-10 2013-08-08 マルチスレッド処理システムにおいてサブルーチンを実行すること Expired - Fee Related JP6073479B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/608,668 2012-09-10
US13/608,668 US9229721B2 (en) 2012-09-10 2012-09-10 Executing subroutines in a multi-threaded processing system
PCT/US2013/054148 WO2014039206A1 (en) 2012-09-10 2013-08-08 Executing subroutines in a multi-threaded processing system

Publications (3)

Publication Number Publication Date
JP2015531945A JP2015531945A (ja) 2015-11-05
JP2015531945A5 true JP2015531945A5 (enExample) 2016-03-31
JP6073479B2 JP6073479B2 (ja) 2017-02-01

Family

ID=49004016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015531090A Expired - Fee Related JP6073479B2 (ja) 2012-09-10 2013-08-08 マルチスレッド処理システムにおいてサブルーチンを実行すること

Country Status (6)

Country Link
US (1) US9229721B2 (enExample)
EP (1) EP2893434B1 (enExample)
JP (1) JP6073479B2 (enExample)
KR (1) KR101660659B1 (enExample)
CN (1) CN104603749B (enExample)
WO (1) WO2014039206A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8832417B2 (en) 2011-09-07 2014-09-09 Qualcomm Incorporated Program flow control for multiple divergent SIMD threads using a minimum resume counter
US9256429B2 (en) 2012-08-08 2016-02-09 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system
US9619230B2 (en) * 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US9582321B2 (en) * 2013-11-08 2017-02-28 Swarm64 As System and method of data processing
FR3013869B1 (fr) * 2013-11-22 2016-01-01 Thales Sa Procede de detection des debordements de pile et processeur pour la mise en oeuvre d'un tel procede
US10133572B2 (en) * 2014-05-02 2018-11-20 Qualcomm Incorporated Techniques for serialized execution in a SIMD processing system
GB2529899B (en) * 2014-09-08 2021-06-23 Advanced Risc Mach Ltd Shared Resources in a Data Processing Apparatus for Executing a Plurality of Threads
US9928076B2 (en) * 2014-09-26 2018-03-27 Intel Corporation Method and apparatus for unstructured control flow for SIMD execution engine
US9766892B2 (en) * 2014-12-23 2017-09-19 Intel Corporation Method and apparatus for efficient execution of nested branches on a graphics processor unit
US9921838B2 (en) * 2015-10-02 2018-03-20 Mediatek Inc. System and method for managing static divergence in a SIMD computing architecture
US9928117B2 (en) 2015-12-11 2018-03-27 Vivante Corporation Hardware access counters and event generation for coordinating multithreaded processing
FR3082331B1 (fr) * 2018-06-08 2020-09-18 Commissariat Energie Atomique Processeur mimd emule sur architecture simd
US12405790B2 (en) * 2019-06-28 2025-09-02 Advanced Micro Devices, Inc. Compute unit sorting for reduced divergence
US12314760B2 (en) * 2021-09-27 2025-05-27 Advanced Micro Devices, Inc. Garbage collecting wavefront
US20250306946A1 (en) * 2024-03-27 2025-10-02 Advanced Micro Devices, Inc. Independent progress of lanes in a vector processor

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US8832417B2 (en) * 2011-09-07 2014-09-09 Qualcomm Incorporated Program flow control for multiple divergent SIMD threads using a minimum resume counter
US9256429B2 (en) * 2012-08-08 2016-02-09 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system

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