JP6070139B2 - Voltage abnormality detector - Google Patents

Description

  The present invention relates to a voltage abnormality detection device.

  The power converter directly generates an AC output of an arbitrary frequency from an AC power source having a constant frequency without passing through a DC, and controls the AC motor. When an abnormality occurs in the input power supply voltage, an abnormality occurs in the output voltage waveform, which makes it difficult to operate the AC motor satisfactorily. Abnormalities in the power supply voltage of the three-phase AC power supply include various states such as an open phase state or a state where the phase sequence of the power source is reversed. The phase loss state is a state in which only one of the three phases is disconnected. Therefore, the power conversion device needs a power supply voltage abnormality detection circuit that detects a power supply voltage abnormality by some method and stops operation.

  The power supply voltage abnormality detection circuit and method disclosed in Patent Document 1 detect a power supply voltage abnormality in any state of an open phase state and a phase sequence in reverse phase. The power supply voltage abnormality detection circuit includes a power supply voltage information generation circuit, an abnormality detection signal generation circuit, and a determination circuit. The power supply voltage information generation circuit detects information according to the magnitude relationship between the voltage values of each phase of the RST of the three-phase AC power supply and outputs it as a power supply voltage information signal. The abnormality detection signal generation circuit holds in advance information based on the magnitude relationship between the voltage values of each phase of the RST when the three-phase AC power supply is normal, and outputs this information as an abnormality detection signal. The determination circuit compares the power supply voltage information signal and the abnormality detection signal at regular intervals, and outputs a power supply voltage abnormality signal when these signals are different.

JP 2001-258151 A

  The power supply voltage abnormality detection circuit and method described in Patent Document 1 compare the power supply voltage information signal and the abnormality detection signal only at regular intervals. Therefore, the power supply voltage abnormality could not be detected accurately. Further, both the power supply voltage information signal and the abnormality detection signal are information according to the magnitude relationship of the voltage values, and are not voltage values. Therefore, the current voltage value could not be accurately grasped. Since the circuit area of the power supply voltage abnormality detection circuit is large, it was difficult to handle.

  An object of the present invention is to provide a voltage abnormality detection device that can accurately detect abnormality of a power supply voltage.

  A voltage abnormality detection device according to claim 1 of the present invention is a voltage abnormality detection device that detects an abnormality of an AC voltage, and the voltage dividing means that divides the AC voltage into a plurality of phases, and the voltage dividing means divides the voltage. Pulse output that outputs a pulse when the potential difference from the target phase, which is the lower phase of the other phases different from the reference phase, becomes a predetermined voltage or more when each pressed phase is a reference phase Means, measuring means for measuring the width and period of the pulse output from the pulse output means for each phase, the width and period measured for each phase by the measuring means, and a reference stored in advance in a memory And an abnormality determining means for determining whether or not the AC voltage is abnormal based on the information. The voltage abnormality detection device divides an alternating voltage supplied by a power source or the like into a plurality of phases, obtains a pulse generated in each phase, and compares the pulse width and period with reference information. That is, instead of judging abnormality for each phase of the three-phase AC voltage, the presence / absence of abnormality is judged based on the pulse output based on the potential difference from the other two phases with reference to one phase. The pulse reflects the overall state of the three phases. Therefore, the voltage abnormality detection device can easily and accurately detect whether or not the AC voltage is abnormal.

In addition to the configuration of the invention of claim 1, a voltage abnormality detection device of an invention according to claim 2 includes a calculation unit that calculates a duty ratio from the width and period measured for each phase by the measurement unit, The voltage dividing means includes a light receiving element device, and the abnormality determining means compares the duty ratio calculated for each phase by the calculating means with the reference information, and determines whether or not the AC voltage is abnormal. It is characterized by determining. Since the voltage dividing means includes a light receiving element device, it can be insulated. Therefore, it can be judged only by the pulse without being influenced by other voltages. By detecting the duty ratio and comparing it with reference information , the voltage abnormality detection device can determine whether there is an abnormality in the AC voltage without being affected by individual differences in the light receiving element devices.

According to a third aspect of the present invention, in addition to the configuration of the second aspect of the invention, the voltage abnormality detection device includes a frequency specifying unit that specifies the frequency of the pulse from the period measured by the measuring unit, and the reference information Has the reference information for each frequency, and the abnormality determination means compares the duty ratio calculated by the calculation means with the reference information corresponding to the frequency specified by the frequency specification means, respectively. And determining whether or not the AC voltage is abnormal. Therefore, the voltage abnormality detection device can accurately detect the presence or absence of abnormality in the AC voltage according to the frequency of the AC voltage.

  In addition to the configuration of the invention according to any one of claims 1 to 3, the voltage abnormality detection device according to a fourth aspect of the invention is configured such that the pulse generated in each of the phases includes the plurality of phases. It is characterized by comprising invalidating means for invalidating the pulses continuously generated in the same phase when the same phase is continuously arranged instead of the phase sequence arranged in order. When the AC voltage is normal, the pulses generated in each phase are in phase order. When the AC voltage is unstable and the voltage drops instantaneously, the pulse of any phase is divided. In this case, a phenomenon occurs in which pulses continue in the same phase. The phenomenon is noise. The invalidating means invalidates the noise. Therefore, the voltage abnormality detection device can accurately detect whether there is an abnormality in the AC voltage even if the AC voltage is temporarily unstable.

  In addition to the configuration of the invention according to any one of claims 1 to 4, the voltage abnormality detection device of the invention according to claim 5 is a three-phase AC voltage, and the voltage dividing means The phase AC voltage is divided into an R phase, an S phase, and a T phase, respectively. Therefore, the voltage abnormality detection device can obtain the effect according to any one of claims 1 to 4 for the three-phase AC voltage.

In addition to the configuration of the invention according to any one of claims 1 to 5, the voltage abnormality detection device according to the invention according to claim 6 is configured to calculate the voltage value of the AC voltage based on the width of the pulse measured by the measurement unit. Voltage value calculating means for calculating, and display means for displaying on the display section at least one of information on the voltage value calculated by the voltage value calculating means and information on the determination result of the abnormality determining means. It is characterized by. The voltage abnormality detection device can display the voltage value and the presence or absence of abnormality on the display unit. Therefore, the user can easily confirm the current voltage value and the presence or absence of voltage abnormality.

1 is a block diagram showing an electrical configuration of a numerical control device 1 and a machine tool 2. FIG. The circuit diagram of the voltage abnormality detection circuit 15. FIG. The pulse conceptual diagram when using RST phase as each reference phase, and the voltage waveform diagram of a three-phase input. The flowchart of a voltage analysis process. Explanatory drawing of a pulse period and a pulse width. Conceptual diagram of normal pulse. The conceptual diagram of the pulse which produced the noise on the way. The graph which compared the calculated value and the three-phase measured value about the relationship between the voltage value in 50Hz, and a pulse width. The graph which compared the calculated value and the three-phase measured value about the relationship between the voltage value in 60Hz, and a pulse width. The graph (50 Hz) which plotted the relationship between a pulse width and a ratio. The graph (60 Hz) which plotted the relationship between a pulse width and a ratio. The conceptual diagram of the calculation parameter table 91. FIG.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A numerical control device 1 shown in FIG. 1 is an example of a voltage abnormality detection device of the present invention. The numerical control device 1 controls the machine tool 2 to cut a workpiece held on the upper surface of a table (not shown).

  The configuration of the machine tool 2 will be briefly described with reference to FIG. The left-right direction, the front-rear direction, and the vertical direction of the machine tool 2 are an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively. The machine tool 2 includes a spindle mechanism, a spindle moving mechanism, a tool changer, and the like (not shown). The spindle mechanism includes a spindle motor 32 and rotates the spindle on which a tool is mounted. The main shaft moving mechanism includes a Z-axis motor 31, an X-axis motor 33, and a Y-axis motor 34, and moves the main shaft in each of the XYZ directions relative to the workpiece supported on the table upper surface.

  The tool changer includes a magazine motor 35, drives a tool magazine (not shown) that holds a plurality of tools, and exchanges a tool mounted on the spindle with another tool. The machine tool 2 further includes an operation panel (not shown). The operation panel includes an input device 17 and a display device 18. The input device 17 is a device for performing various inputs and settings. The display device 18 is a device that displays voltage information, abnormality information, and the like, which will be described later, in addition to various display screens and setting screens. The voltage information is information on the current voltage value supplied by the three-phase AC power source 19. The abnormality information is information indicating that the voltage supplied from the three-phase AC power supply 19 is abnormal. Voltage anomalies include overvoltage or voltage drop conditions. The input device 17 and the display device 18 are connected to the input / output unit 16 of the numerical controller 1.

  The Z-axis motor 31 includes an encoder 41. The spindle motor 32 includes an encoder 42. The X-axis motor 33 includes an encoder 43. The Y-axis motor 34 includes an encoder 44. The magazine motor 35 includes an encoder 45. The encoders 41 to 45 are connected to the drive circuits 21 to 25 of the numerical controller 1, respectively.

  The electrical configuration of the numerical control device 1 will be described with reference to FIG. The numerical control device 1 includes a CPU 11, a ROM 12, a RAM 13, a nonvolatile storage device 14, a voltage abnormality detection circuit 15, an input / output unit 16, drive circuits 21 to 25, and the like, and uses a three-phase AC power source 19 as a drive source. The CPU 11 performs overall control of the numerical control device 1. The ROM 12 stores various programs. The RAM 13 temporarily stores various data during execution of various processes. The non-volatile storage device 14 stores a plurality of NC programs and the like registered by the operator using the input device 17. The NC program is composed of a plurality of blocks including various control commands, and controls various operations including axis movement of the machine tool 2, tool change, and the like in units of blocks.

  The voltage abnormality detection circuit 15 detects the presence or absence of abnormality in the three-phase AC voltage supplied from the three-phase AC power source 19. The drive circuit 21 is connected to the Z-axis motor 31 and the encoder 41. The drive circuit 22 is connected to the spindle motor 32 and the encoder 42. The drive circuit 23 is connected to the X-axis motor 33 and the encoder 43. The drive circuit 24 is connected to the Y-axis motor 34 and the encoder 44. The drive circuit 25 is connected to the magazine motor 35 and the encoder 45. The drive circuits 21 to 25 receive command signals from the CPU 11 and output drive currents to the corresponding motors 31 to 35, respectively. The drive circuits 21 to 25 receive feedback signals from the encoders 41 to 45 and perform feedback control of position and speed. The input / output unit 16 is connected to the input device 17 and the display device 18, respectively.

  The user can select one NC program from among a plurality of NC programs with the input device 17. The CPU 11 displays the selected NC program on the display device 18. The CPU 11 controls the operation of the machine tool 2 based on the NC program displayed on the display device 18.

  The three-phase AC power source 19 will be described with reference to FIG. The three-phase AC power source 19 is an AC power source combining three systems of single-phase AC with the current or voltage phases shifted from each other, and supplies an AC voltage of 200 V, for example. The first phase is the R phase, the second phase is the S phase, and the third phase is the T phase. The three-phase AC power source 19 shown in FIG. 2 has a Δ connection (delta connection). The Δ connection is a connection in which the three phases are connected in the direction in which the phase voltage is applied to form a closed circuit. The three-phase AC power source 19 may be a Y connection or a V connection in addition to the Δ connection.

  The configuration of the voltage abnormality detection circuit 15 will be described with reference to FIG. The voltage abnormality detection circuit 15 detects an abnormality in the AC voltage supplied from the three-phase AC power source 19. The voltage abnormality detection circuit 15 includes an R-phase reference circuit 51, an S-phase reference circuit 52, a T-phase reference circuit 53, and an FPGA 55 (hereinafter collectively referred to as reference circuits 51 to 53). Since the voltage abnormality detection circuit 15 has a simple configuration, the circuit area can be reduced as compared with the conventional case and is easy to handle.

  The R-phase reference circuit 51 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other S phase and the lower one of the T phases becomes a predetermined voltage or more with the R phase as a reference. Sometimes outputs a pulse. The S-phase reference circuit 52 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other R phase and the lower one of the T phases becomes a predetermined voltage or more with the S phase as a reference. Sometimes outputs a pulse. The T-phase reference circuit 53 divides the three-phase AC voltage output from the three-phase AC power supply 19, and the potential difference between the other R phase and the lower one of the S phases becomes a predetermined voltage or more with the T phase as a reference. Sometimes outputs a pulse. The FPGA 55 executes a voltage analysis process (see FIG. 4) described later. The voltage analysis process is a process of analyzing the pulse output from the reference circuits 51 to 53 to analyze the presence / absence of a voltage abnormality and the voltage value.

  The configuration of the R-phase reference circuit 51 will be described with reference to FIG. The R-phase reference circuit 51 includes resistors 61 and 62, a shunt regulator 63, a photocoupler 64, and the like. The resistors 61 and 62 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The shunt regulator 63 is turned on when the potential difference between the other S phase and the lower one of the T phases on the R phase basis becomes a predetermined voltage or more. When the shunt regulator 63 is turned on, the photocoupler 64 lights up and outputs a pulse to the FPGA 55. The shunt regulator 63 is turned off when the potential difference between the other S phase and the lower T phase is less than a predetermined voltage on the R phase basis. When the shunt regulator 63 is turned off, the photocoupler 64 is turned off.

  The S-phase reference circuit 52 includes resistors 71 and 72, a shunt regulator 73, a photocoupler 74, and the like. The resistors 71 and 72 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The shunt regulator 73 is turned on when the potential difference between the other R phase and the lower one of the T phases on the S phase basis becomes a predetermined voltage or more. When the shunt regulator 73 is turned on, the photocoupler 74 is lit and outputs a pulse to the FPGA 55. The shunt regulator 73 is turned off when the potential difference between the other R phase and the lower one of the T phases is less than a predetermined voltage based on the S phase. When the shunt regulator 73 is turned off, the photocoupler 74 is turned off.

  The T-phase reference circuit 53 includes resistors 81 and 82, a shunt regulator 83, a photocoupler 84, and the like. The resistors 81 and 82 divide the three-phase AC voltage output from the three-phase AC power source 19 into an R phase, an S phase, and a T phase, respectively. The shunt regulator 83 is turned on when the potential difference between the other R phase and the lower one of the S phases is equal to or higher than a predetermined voltage on the T phase basis. When the shunt regulator 83 is turned on, the photocoupler 84 is turned on and a pulse is output to the FPGA 55. The shunt regulator 83 is turned off when the potential difference between the other R phase and the lower one of the S phases is less than a predetermined voltage on the T phase basis. When the shunt regulator 83 is turned off, the photocoupler 84 is turned off.

  The operation of the R-phase reference circuit 51 will be described with reference to FIGS. The waveform at the bottom of FIG. 3 is a voltage curve in which three phases of RST are input. Each voltage curve is a sin curve, and the phase is shifted by 120 degrees. The upper three waveforms in FIG. 3 are conceptual diagrams of each pulse waveform when the R phase reference, the S phase reference, and the T phase reference are set in order from the top. Each conceptual diagram shows a pulse waveform having a potential difference of a predetermined voltage or more (for example, 152.5 V or more) for easy understanding. When the potential difference is less than a predetermined voltage, the pulse voltage is zero.

  As described above, the R-phase reference circuit 51 outputs a pulse when the potential difference between the lower of the other S-phase and T-phase and the R-phase is equal to or higher than a predetermined voltage on the R-phase basis. For example, the description will be made by paying attention to a frame surrounded by a two-dot chain line shown in FIG. At t1, the voltage of the S phase is lower than that of the T phase, and the potential difference between the R phase and the S phase is the same. When the voltage of the S phase is lower than that of the T phase, the voltage is applied in the direction of the dotted arrow A in the R phase reference circuit 51 as shown in FIG. After t1, a potential difference is gradually generated between the R phase and the S phase, and reaches a predetermined voltage or more at t2. The shunt regulator 63 is turned on. A current flows between the K terminal (cathode terminal) and the A terminal (anode terminal) of the shunt regulator 63. The photocoupler 64 is lit and outputs a pulse to the FPGA 55. The pulse rises from t2 and reaches a certain value. The potential difference between the R phase and the S phase gradually decreases.

  At t3, the S phase and the T phase are reversed. The pulse drops slightly at t3. After t3, the voltage in the T phase becomes lower than that in the S phase, so that the voltage is applied in the direction of the two-dot chain line arrow B in the R phase reference circuit 51 as shown in FIG. After t3, a potential difference of a predetermined voltage or more is generated between the R phase and the T phase, so that the pulse rises again and reaches a constant value. The potential difference between the R phase and the T phase gradually decreases and becomes less than a predetermined voltage at t4. The shunt regulator 63 is turned off. The photocoupler 64 is turned off. The pulse becomes zero at t4. The pulse output from the R-phase reference circuit 51 repeats the waveform from t2 to t4 at regular intervals.

  The S phase reference circuit 52 and the T phase reference circuit 53 operate in the same manner as the R phase reference circuit 51. As shown in FIG. 3, the S-phase and T-phase pulse waveforms are out of phase with the R-phase pulse waveform. The R-phase pulse, S-phase pulse, and T-phase pulse are each output to the FPGA 55 in the RST phase order. The FPGA 55 executes voltage analysis processing for each pulse output from the reference circuits 51 to 53.

  The voltage analysis process will be described with reference to FIG. The voltage analysis process is executed by the FPGA 55. First, the FPGA 55 receives RST phase pulse information (S10). The pulse information is information on pulses output from the R-phase reference circuit 51, the S-phase reference circuit 52, and the T-phase reference circuit 53, respectively.

  Next, the FPGA 55 measures the pulse width and the pulse period for each phase based on the pulse information (S11). As shown in FIG. 5, the pulse repeats at regular intervals. t7 is the time for the pulse to rise from the reference voltage. The reference voltage is a constant voltage of 152.5V, for example. t8 is the time when the pulse reaches the maximum voltage. t9 is the time when the pulse starts to drop from the maximum voltage. t10 is the time when the pulse drops to the reference voltage. t11 is the time when the next pulse rises from the reference voltage. The pulse width is the time from t7 to t10. The pulse period is the time from t7 to t11. The pulse width may be a time from t8 to t9. t7 to t11 are stable parts of the pulse. Therefore, the FPGA 55 can accurately measure the pulse width and the pulse period.

  Incidentally, a photocoupler generally includes two elements, a light emitting element and a light receiving element. There are variations in the light emitting condition, light receiving sensitivity, etc. of each element. The relationship between the light emission condition and the light receiving sensitivity is called CTR (conversion efficiency) and is expressed in%. CTR varies from lot to lot and may decrease with aging. CTR variation mainly affects the FALL time. Therefore, the FPGA 55 may correct the pulse width using the RISE time and FALL time of the pulse in consideration of the variation of each element. The RISE time is a time from t7 to t8. The FALL time is a time from t9 to t10. The FPGA 55 may measure the RISE time and the FALL time, and subtract half the width of each time from the pulse width from t7 to t10. When the pulse width is a time from t8 to t9, half the width of the RISE time and the FALL time may be added to the pulse width, respectively.

  Next, the FPGA 55 calculates a frequency (S12). The FPGA 55 determines whether the frequency of the three-phase AC power source 19 is 50 Hz, 60 Hz, or other based on the pulse period measured for each phase. The FPGA 55 stores the determination result in a memory (not shown).

  Next, the FPGA 55 performs a pulse check process (S13). The pulse check process is a process of detecting the presence or absence of abnormality of each pulse output from the R-phase reference circuit 51, the S-phase reference circuit 52, and the T-phase reference circuit 53, and invalidating the pulse having the abnormality. The pulse shown in FIG. 6 is a normal pulse. One cycle of the pulse is a time from t15 to t16. t15 and t16 are times when the pulse is updated. If each pulse of the RST phase is normal, it appears in the phase order of the RST as shown in FIG.

  In the pulse shown in FIG. 7, noise occurs in the middle. If normal, one cycle of the pulse is the time from t17 to t19. For example, the voltage may drop instantaneously depending on local power conditions. An instantaneous voltage drop during pulse output becomes noise. If noise is generated during pulse output, the pulse is divided into two peaks. Therefore, the pulse is updated at t17, t18, and t19. The pulse period has two periods, a period from t17 to t18 and a period from t18 to t19. When the abnormality shown in FIG. 7 occurs in the R-phase pulse, the R-phase pulse is continuously updated in the same phase. The FPGA 55 detects each pulse in the order of “RRST”. If the pulse is updated continuously in the same phase, the pulse is abnormal. The FPGA 55 determines that consecutive pulses are invalid. Therefore, the FPGA 55 can determine abnormality by extracting only normal pulses.

  Next, the FPGA 55 executes a phase order check process (S14). The phase sequence check process checks whether the AC voltage is in phase sequence based on each pulse output from the reference circuits 51 to 53. A state where the AC voltage is not in phase order is an abnormal state. The abnormal state is, for example, a missing state or a reverse phase state. The missing state is a state in which only one of the three phases is disconnected. The reverse phase state is a state in which the phase order of the RST phase is reversed. When the FPGA 55 detects a missing state or a reverse phase state, the FPGA 55 stores it in the memory as abnormality information.

  Next, the FPGA 55 performs an abnormality detection process (S15). The abnormality detection process is a process for detecting an overvoltage and a voltage drop of the three-phase AC power supply 19 respectively. In the abnormality detection process, the FPGA 55 calculates the pulse width and the duty ratio of the pulse period for each phase of RST. The duty ratio is the ratio of the pulse width to the pulse period. The FPGA 55 stores a first threshold value and a second threshold value in advance in a memory for each frequency (for example, 50 Hz and 60 Hz). The first threshold is a threshold for determining an overvoltage. The second threshold is a threshold for determining a voltage drop. You may obtain | require a 1st threshold value and a 2nd threshold value from the measured value of an experimental result. For example, at a frequency of 50 Hz, the first threshold value can be set to 57.19% and the second threshold value can be set to 46.62%. The FPGA 55 determines an overvoltage if the duty ratio is equal to or greater than the first threshold, and determines a voltage drop if the duty ratio is equal to or less than the second threshold. The FPGA 55 stores the determination result in the memory as abnormality information. A power failure may be detected by setting a third threshold lower than the second threshold. The first threshold value and the second threshold value correspond to the reference information of the present invention.

  Although not described in detail, the FPGA 55 uses the BIT shift division and the adder to calculate the upper and lower determination reference values of the pulse width from the pulse period as approximate values, and compares this approximate value with the pulse width. For example, when the pulse period is 20 ms at 50 Hz, the internal counter of the FPGA 55 is 1 counter = 2 us unit and the BIT length is 14 bits, so the counter value is about 10,000. The BIT shift division is performed by 2 for every shift. Therefore, the FPGA 55 performs BIT shift 13 times, adds only the first, fourth, seventh, tenth, eleventh and thirteenth times, and calculates the upper limit value of the pulse width of 57.19% which is the first threshold value from the pulse period. The FPGA 55 compares the upper limit value with the pulse width, and if it exceeds the value, it can be determined as an overvoltage.

Next, the FPGA 55 executes a voltage value calculation process (S16). The voltage value calculation process is a process for calculating the three-phase voltage value of the RST using the pulse width, the pulse period, and the frequency. A general arithmetic expression for calculating a single-phase voltage value is as follows. V _IN is an input voltage, V _E is a voltage detection threshold, and is a voltage at which the photocoupler becomes conductive. f is a frequency.
V _IN = V _E / (cos (2π × f × (pulse width / 2)) (1)

  The graph of FIG. 8 shows the relationship between the voltage value calculated using the equation (1) at a frequency of 50 Hz and the pulse width. The lower curve P1 is a calculated value, and the upper curve P2 is a three-phase measured value. The calculated value is a pulse width calculated using the equation (1). The three-phase measured value is a pulse width of a voltage value measured by the FPGA 55. It can be seen that the curve P1 is about 0.6 times the curve P2. Therefore, in order to calculate the voltage value of the three-phase AC power supply 19 at a frequency of 50 Hz, the equation (1) for a single phase cannot be used as it is.

  The relationship between the voltage value calculated using the equation (1) at a frequency of 60 Hz and the pulse width is shown in the graph of FIG. The lower curve Q1 is a calculated value, and the upper curve Q2 is a three-phase measured value. It can be seen that the curve Q1 is about 0.6 times the curve Q2. Therefore, in order to calculate the voltage value of the three-phase AC power supply 19 at a frequency of 60 Hz, the equation (1) for a single phase cannot be used as it is.

From the above examination, the equation (1) is improved in order to calculate the voltage value of the three-phase AC power source 19 from the measured pulse width. The pulse width input to the equation (1) may be corrected to directly derive the three-phase measured value. FIG. 10 is a plot of the ratio between the calculated value and the three-phase measured value for each pulse width calculated at a frequency of 50 Hz. The horizontal axis represents the pulse width measured by the FPGA 55, and the vertical axis represents the ratio. The ratio is a correction value for correcting the pulse width measured by the FPGA 55. The approximate expression of these plot data is as follows.
y = -0.0005510245x ⁴ + 0.0203099438x ³ -0.2793184179x ² + 1.7165523815x-3.3316034929 (2)

FIG. 11 is a plot of the ratio between the calculated value and the measured three-phase value for each pulse width at a frequency of 60 Hz. The horizontal axis represents the pulse width measured by the FPGA 55, and the vertical axis represents the ratio. The ratio is a correction value for correcting the pulse width measured by the FPGA 55. The approximate expression of these plot data is as follows.
y = 0.0137540330x ⁴ -0.4256553089x ³ + 4.9038648653x ² -24.8943800941x + 47.6117061713 (3)

Calculation formulas and calculation parameters for calculating the voltage value of the three-phase AC power supply 19 from the pulse width measured by the FPGA 55 are as follows. Calculation parameters are set for each frequency.
V _IN = V _E / (cos (π × F × ActPW × (ApP1 × ActPW ⁴ + ApP2 × ActPW ³ + ApP3 × ActPW ² + ApP4 × ActPW + ApP5) × 10 ⁻³ )) / √2 (4 )
V _E : voltage detection threshold (152.5 V in this embodiment)
・ ActPW: Measured pulse width (ms)
・ F ： Frequency ・ ApP1 to ApP5: Approximate equation parameters obtained from Equations (2) and (3)

  The FPGA 55 stores a calculation parameter table 91 shown in FIG. 12 in a memory. The calculation parameter table 91 sets the above-described calculation parameters. The approximate expression parameters of ApP1 to ApP5 may be changed according to the above evaluation results. Therefore, the FPGA 55 applies the approximate equation parameter of the frequency calculated from the measured pulse period in the calculation parameter table 91 to the equation (4), and substitutes the measured pulse width into ActPW, so that the voltage value of the three-phase AC power source 19 is obtained. Can be calculated. The FPGA 55 stores the calculated voltage value in the memory as voltage information.

  Next, the FPGA 55 outputs the abnormality information and voltage information stored in the memory to the CPU 11 (S17). The CPU 11 stores the output abnormality information and voltage information in the RAM 13 and displays them on the display device 18. The operator can recognize whether the three-phase AC voltage is normal or abnormal by checking the abnormality information and voltage information displayed on the display device 18. Therefore, the operator can promptly respond such as repair and replacement of the abnormal part. Since the operator can check not only abnormality information but also voltage information, it can always check that the three-phase AC voltage is normal.

  In the above description, the reference circuits 51 to 53 correspond to the voltage dividing means and the pulse output means of the present invention, and the FPGA 55 that executes the process of S11 in FIG. 4 corresponds to the measuring means of the present invention and executes the process of S12. The FPGA 55 that corresponds to the frequency specifying means of the present invention corresponds to the FPGA 55 that executes the process of S13 corresponds to the invalidation means of the present invention, and the FPGA 55 that executes the process of S15 corresponds to the abnormality determination means of the present invention. The CPU 11 that displays voltage information and abnormality information on the display device 18 corresponds to the display means of the present invention.

  As described above, the numerical controller 1 according to this embodiment includes the voltage abnormality detection circuit 15. The voltage abnormality detection circuit 15 detects whether or not the three-phase AC power source 19 is abnormal. The voltage abnormality detection circuit 15 includes an R-phase reference circuit 51, an S-phase reference circuit 52, a T-phase reference circuit 53, and an FPGA 55. The R-phase reference circuit 51 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other S phase and the lower one of the T phases becomes a predetermined voltage or more with the R phase as a reference. Sometimes outputs a pulse. The S-phase reference circuit 52 divides the three-phase AC voltage output from the three-phase AC power source 19, and the potential difference between the other R phase and the lower one of the T phases becomes a predetermined voltage or more with the S phase as a reference. Sometimes outputs a pulse. The T-phase reference circuit 53 divides the three-phase AC voltage output from the three-phase AC power supply 19, and the potential difference between the other R phase and the lower one of the S phases becomes a predetermined voltage or more with the T phase as a reference. Sometimes outputs a pulse. The FPGA 55 analyzes the pulses output from the reference circuits 51 to 53 and detects the presence / absence of voltage abnormality and the voltage value in real time. The FPGA 55 does not determine the abnormality for each phase of the three-phase AC voltage, but determines the presence or absence of an abnormality based on the pulse output based on the potential difference from the other two phases based on one phase. Therefore, the numerical controller 1 can accurately detect whether or not the three-phase AC voltage is abnormal.

  In the present embodiment, the FPGA 55 further calculates the duty ratio from the pulse width and pulse period measured for each phase. The FPGA 55 can detect the overvoltage and voltage drop of the three-phase AC power source 19 by comparing the calculated duty ratio with the first threshold value and the second threshold value. Since the comparison is based on the duty ratio, the influence of individual differences of the photocoupler can be reduced. Further, since each of the reference circuits 51 to 53 includes a photocoupler that is a light receiving element device, the circuit can be insulated. Therefore, the FPGA 55 can calculate the voltage value only from the pulse information without being affected by other voltages.

  In the present embodiment, the FPGA 55 further specifies the frequency from the pulse period. The FPGA 55 compares the threshold value corresponding to the specified frequency with the duty ratio. Therefore, the numerical controller 1 can accurately detect the presence or absence of an abnormality in the AC voltage according to the frequency of the AC voltage.

  In the present embodiment, the FPGA 55 further invalidates the pulses generated continuously in the same phase when the pulses generated in the respective phases are continuously arranged in the same phase. Therefore, the numerical control device 1 can invalidate the pulse when noise caused by an instantaneous voltage drop or the like is generated in the middle of the pulse, so that only the normal pulse can be extracted to determine the voltage abnormality.

  In the present embodiment, the CPU 11 further displays at least one of voltage information and abnormality information on the display device 18. Therefore, the user can easily monitor the current voltage value and the presence or absence of abnormality.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. In the embodiment described above, an abnormality in the three-phase AC voltage supplied from the three-phase AC power source 19 is detected, but two phases may be used, or a plurality of three or more phases may be used.

  In the above embodiment, each of the reference circuits 51 to 53 includes the photocouplers 64, 74, and 84. However, any light receiving element device may be used, and for example, an optical MOSFET may be used.

  In the above embodiment, the CPU 11 displays the abnormality information output from the FPGA 55 on the display device 18. The CPU 11 may perform control to stop the operation of the machine tool 2 based on the abnormality information. For example, when detecting an overvoltage or a voltage drop, the CPU 11 may stop the operation of the machine tool 2. Moreover, although the said embodiment detects an overvoltage and a voltage drop by comparing with a 1st threshold value and a 2nd threshold value, you may detect an overvoltage and a voltage drop in multiple steps further using a some threshold value. In this case, it is possible to detect the level of overvoltage and voltage drop. Further, according to the level of overvoltage or voltage drop, the display device 18 may notify the abnormality and forcibly stop the operation of the machine tool 2.

  Moreover, although the said embodiment demonstrated the numerical control apparatus 1 as one Embodiment of the voltage abnormality detection apparatus of this invention, the voltage abnormality detection apparatus independent of the numerical control apparatus 1 may be sufficient.

  In the above embodiment, the FPGA 55 calculates the duty ratio from the pulse width and the pulse period and compares the first threshold value with the second threshold value to determine the abnormality. However, the FPGA 55 may determine the abnormality only with the pulse width.

DESCRIPTION OF SYMBOLS 1 Numerical control apparatus 15 Voltage abnormality detection circuit 19 Three-phase alternating current power supply 51 R phase reference circuit 52 S phase reference circuit 53 T phase reference circuit 55 FPGA
61, 62 Resistor 64 Photocoupler 71, 72 Resistor 74 Photocoupler 81, 82 Resistor 84 Photocoupler

Claims (6)

A voltage abnormality detection device for detecting an abnormality in an AC voltage,
Voltage dividing means for dividing the AC voltage into a plurality of phases;
When each phase divided by the voltage dividing means is used as a reference phase, when a potential difference with a target phase which is a lower phase among other phases different from the reference phase becomes a predetermined voltage or more Pulse output means for outputting a pulse;
Measuring means for measuring the width and period of the pulse output by the pulse output means for each phase;
An abnormality determining means for determining whether or not there is an abnormality in the AC voltage based on the width and period measured for each phase by the measuring means and reference information stored in advance in a memory. Voltage abnormality detection device. The measuring means comprises a calculating means for calculating a duty ratio from the width and period measured for each phase,
The voltage dividing means includes a light receiving device,
The abnormality determining means includes
2. The voltage abnormality detection according to claim 1, wherein the calculation unit compares the duty ratio calculated for each phase with the reference information to determine whether or not the AC voltage is abnormal. apparatus. A frequency specifying means for specifying the frequency of the pulse from the period measured by the measuring means;
The reference information has the reference information for each frequency,
The abnormality determining means includes
The duty ratio calculated by the calculating means and the reference information corresponding to the frequency specified by the frequency specifying means are respectively compared to determine whether or not the AC voltage is abnormal. Item 3. The voltage abnormality detection device according to Item 2.   The measuring means is configured such that, when the pulses generated in the respective phases are not in the phase order in which the plurality of phases are sequentially arranged, and the same phase is continuously arranged, the pulses generated continuously in the same phase. The voltage abnormality detection device according to claim 1, further comprising invalidating means for invalidating the voltage. The AC voltage is a three-phase AC voltage,
5. The voltage abnormality detection device according to claim 1, wherein the voltage dividing unit divides the three-phase AC voltage into an R phase, an S phase, and a T phase. Voltage value calculating means for calculating a voltage value of the AC voltage based on the width of the pulse measured by the measuring means;
2. The display device according to claim 1, further comprising: a display unit configured to display at least one of information on the voltage value calculated by the voltage value calculation unit and information on a determination result of the abnormality determination unit on a display unit. The voltage abnormality detection device according to any one of 5.

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