JP6866800B2 - Voltage abnormality detector - Google Patents

Description

The present invention relates to a voltage abnormality detection device.

Patent Document 1 discloses a voltage abnormality detecting device that detects an abnormality of a three-phase AC voltage. The voltage abnormality detecting device detects the duty ratio for each of the R phase, the S phase, and the T phase of the three-phase AC voltage. The voltage abnormality detection device compares the detected duty ratio with a predetermined threshold value and determines whether an overvoltage or a voltage drop has occurred. The voltage abnormality detection device displays the determination result on the display device.

Japanese Patent No. 60701139

Due to the influence of the low-pass filter and bypass capacitor provided on the signal line of the three-phase AC voltage, the duty ratio fluctuates according to the fluctuation of the frequency of the three-phase AC voltage. Therefore, the voltage abnormality detection device has a problem that when the duty ratio is determined by a common threshold value regardless of the frequency fluctuation, the occurrence of overvoltage or voltage drop may not be accurately determined.

An object of the present invention is to provide a voltage abnormality detecting device capable of accurately detecting a power supply abnormality.

Voltage abnormality detection apparatus according to the present invention, R phase, S phase, a voltage abnormality detection apparatus for detecting an abnormality of the three-phase AC power supply voltage, including a T-phase, the three-phase AC power supply R phase, S phase , A first set resistance, a second set resistance, and a third set resistance that divide the voltage into the T phase, and is a voltage dividing means consisting of three reference circuits, the first set resistance, the second set resistance, and Each of the third set resistors includes two resistors connected in series, the first set resistor and a bypass capacitor connected in parallel to one of the two resistors included in the first set resistor. An R-phase reference circuit including at least a pulse output unit that outputs a pulse when the potential difference between the other S-phase and the T-phase, whichever is lower than the R-phase, becomes a predetermined voltage or more, the second set of resistors, and the above. A bypass capacitor connected in parallel to one of the two resistors included in the second set of resistors and a pulse is output when the potential difference between the other R phase and T phase, whichever is lower, exceeds a predetermined voltage based on the S phase. An S-phase reference circuit including at least a pulse output unit, a bypass capacitor connected in parallel to one of the third set resistor and one of the two resistors included in the third set resistor, and another T-phase reference. A voltage dividing means including at least a T-phase reference circuit including a pulse output unit that outputs a pulse when the potential difference between the lower of the R phase and the S phase becomes a predetermined voltage or more, and each of the three reference circuits. Reference information that defines the threshold of the duty ratio, which is the ratio of the pulse width to the pulse period of the pulse signal output by the pulse output unit, for each frequency of the three-phase AC power supply, is a circuit condition that indicates the frequency characteristics of the bypass capacitor. a storage unit which stores a table associating each, identifiable instructing said circuit condition, receiving directly through the input device Luke, or indirectly accepted on the basis of the setting information of the setting switch, determining means for determining the reference information for each of the frequencies in which the instruction accepted is attached corresponding to the circuit condition to identify among the tables stored in the storage unit, each of the three criteria circuit outputs the pulse period and the pulse width based on the pulse signal measured for each phase, a first specifying means based on the pulse period measured for each phase, identifying the frequency of the three-phase AC power supply for each phase, the determination among the reference information for each of the frequency determined by the unit, a second specifying unit that particular the reference information which is correlated to the frequency specific to each phase by said first specifying means, the second specific The threshold defined by the reference information specified for each phase by means. Values and, based on the magnitude relation between the pulse duty ratio is the ratio of the width to the pulse period of the three reference circuits each pulse signal the pulse output unit outputs of abnormal voltage of the three-phase AC power supply It is characterized in that it is provided with a determination means for determining whether or not there is.

The voltage abnormality detection device stores the reference information in which the duty ratio threshold is defined according to the circuit conditions indicating the frequency characteristics of the bypass capacitor in the table in association with the frequency of the three-phase AC power supply and stores it in the storage unit. .. The voltage abnormality detection device identifies the frequency of the three-phase AC power supply and identifies the corresponding reference information based on the table. The voltage abnormality detection device has an abnormality in the voltage of the three-phase AC power supply based on the magnitude relationship between the threshold value defined by the specified reference information and the duty ratio of the pulse signal output by the pulse output unit of each of the three reference circuits. Determine if there is. Said time, the abnormal voltage detecting apparatus, when the frequency of the three-phase AC power source varies according to the circuit condition of the bypass capacitor (frequency characteristic) is also based on the reference information corresponding to a frequency variation, three-phase AC power supply It can be determined whether there is an abnormality in the voltage. Therefore, the voltage abnormality detecting device can accurately detect whether or not there is an abnormality in the voltage of the three-phase AC power supply.

The determination means in the present invention, among the pulse signals the pulse output unit of each of the three criteria circuit outputs the duty ratio of the pulse signal on the two or more is out of the defined the threshold by the reference information When it is larger than the first threshold value for detecting the overvoltage, it may be determined that the overvoltage has occurred in the voltage of the three-phase AC power supply. At this time, the voltage abnormality detection device can accurately determine the overvoltage of the voltage of the three-phase AC power supply.

In the present invention, the determination means is the first for detecting the duty ratio of the pulse signal output by the pulse output unit of each of the three reference circuits and the overvoltage among the threshold values defined by the reference information. When the duty ratio of any of the pulse signals output by each of the three reference circuits is continuously larger than the first threshold value by a predetermined number of times or more, the voltage of the three-phase AC power supply is overvoltage. May be determined to have occurred. At this time, the voltage abnormality detection device can accurately determine the overvoltage of the voltage of the three-phase AC power supply.

In the present invention, the determining means, on the two or more of the pulse outputs of each of the three reference circuits, when no output pulse signal for a predetermined time or more, the voltage drop occurs in the voltage of the three-phase AC power supply May be determined. At this time, the voltage abnormality detection device can accurately determine the voltage drop of the voltage of the three-phase AC power supply.

In the present invention, the determination means is a first for detecting a voltage drop among the duty ratio of the pulse signal output by the pulse output unit of each of the three reference circuits and the threshold value defined by the reference information. When the duty ratio of the pulse signal output by each of the three reference circuits is continuously smaller than the second threshold value by a predetermined number of times or more by repeatedly comparing the two threshold values, a voltage drop occurs in the voltage of the three-phase AC power supply. It may be determined that it has occurred. At this time, the voltage abnormality detection device can accurately determine the voltage drop of the voltage of the three-phase AC power supply.

In the present invention, as the frequency of the pulse signal the pulse output unit outputs a large, may be the predetermined number of times is larger. At this time, the voltage abnormality detection device can equalize the time until the determination of whether or not there is an abnormality in the three-phase AC voltage is completed.

In the present invention, a result output means for outputting a determination result by the determination means may be further provided. At this time, the voltage abnormality detection device can notify the outside of the occurrence of the voltage abnormality.

The block diagram which shows the electrical structure of a numerical control device 1 and a machine tool 2. The circuit diagram of the voltage abnormality detection circuit 15. Conceptual diagram of pulse and voltage waveform diagram of three-phase input when RST phase is used as each reference phase. The figure which shows the threshold value table 14A. Flow diagram of main processing. Explanatory drawing of pulse period and pulse width. The flow chart of the first judgment process. The flow chart of the second judgment process.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The numerical control device 1 shown in FIG. 1 is an example of the voltage abnormality detection device of the present invention. The numerical control device 1 controls the machine tool 2 and cuts the work held on the upper surface of the table (not shown).

<Overview of Machine Tool 2>
The configuration of the machine tool 2 will be briefly described with reference to FIG. The horizontal direction, the front-rear direction, and the vertical direction of the machine tool 2 are the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively. The machine tool 2 includes a spindle mechanism (not shown), a spindle moving mechanism, a tool changing device, and the like. The spindle mechanism includes a spindle motor 32 and rotates a spindle equipped with a tool. The spindle moving mechanism includes a Z-axis motor 31, an X-axis motor 33, and a Y-axis motor 34, and moves the spindle in each axial direction of XYZ relative to the work supported on the upper surface of the table.

The tool changing device includes a magazine motor 35, drives a tool magazine (not shown) for holding a plurality of tools, and replaces a tool mounted on the spindle with another tool. The machine tool 2 further includes an operation panel (not shown). The operation panel includes an input device 17 and a display device 18. The input device 17 is a device for performing various inputs, settings, and the like. The display device 18 displays notification information and the like, which will be described later, in addition to various display screens and setting screens. The notification information includes a state of overvoltage or voltage drop. The input device 17 and the display device 18 are connected to the input / output unit 16 of the numerical control device 1.

The Z-axis motor 31 includes an encoder 41. The spindle motor 32 includes an encoder 42. The X-axis motor 33 includes an encoder 43. The Y-axis motor 34 includes an encoder 44. The magazine motor 35 includes an encoder 45. The encoders 41 to 45 are connected to the drive circuits 21 to 25 of the numerical control device 1, respectively.

<Overview of Numerical Control Device 1>
The electrical configuration of the numerical control device 1 will be described with reference to FIG. The numerical control device 1 includes a CPU 11, a ROM 12, a RAM 13, a non-volatile storage device 14, a voltage abnormality detection circuit 15, an input / output unit 16, drive circuits 21 to 25, and the like, and uses a three-phase AC power supply 19 as a drive source. The CPU 11 controls the numerical control device 1 in an integrated manner. The ROM 12 stores various programs. The RAM 13 temporarily stores various data during execution of various processes. The non-volatile storage device 14 stores a plurality of NC programs input and registered by the operator in the input device 17. The NC program is composed of a plurality of blocks including various control commands, and controls various operations including axis movement and tool change of the machine tool 2 in block units. Further, the non-volatile storage device 14 stores the threshold value table 14A (see FIG. 4) described later.

The voltage abnormality detection circuit 15 detects the presence or absence of abnormality in the three-phase AC voltage supplied by the three-phase AC power supply 19. The drive circuit 21 is connected to the Z-axis motor 31 and the encoder 41. The drive circuit 22 is connected to the spindle motor 32 and the encoder 42. The drive circuit 23 is connected to the X-axis motor 33 and the encoder 43. The drive circuit 24 is connected to the Y-axis motor 34 and the encoder 44. The drive circuit 25 is connected to the magazine motor 35 and the encoder 45. The drive circuits 21 to 25 receive a command signal from the CPU 11 and output drive currents to the corresponding motors 31 to 35, respectively. The drive circuits 21 to 25 receive feedback signals from the encoders 41 to 45 and perform feedback control of position and speed. The input / output unit 16 is connected to the input device 17 and the display device 18, respectively.

The user can select one NC program from the plurality of NC programs with the input device 17. The CPU 11 displays the selected NC program on the display device 18. The CPU 11 controls the operation of the machine tool 2 based on the NC program displayed on the display device 18.

The three-phase AC power supply 19 will be described with reference to FIG. The three-phase AC power supply 19 is an AC power supply that combines three systems of single-phase AC that are out of phase with each other in current or voltage, and supplies, for example, an AC voltage of 200 V. The first phase is the R phase, the second phase is the S phase, and the third phase is the T phase. The three-phase AC power supply 19 shown in FIG. 2 has a delta connection. The Δ connection is a connection in which each of the three phases is connected in the direction in which the phase voltage is applied to form a closed circuit. The three-phase AC power supply 19 may be Y-connected or V-connected in addition to the Δ connection.

<Voltage abnormality detection circuit 15>
The configuration of the voltage abnormality detection circuit 15 will be described with reference to FIG. The voltage abnormality detection circuit 15 detects an abnormality in the AC voltage supplied by the three-phase AC power supply 19. The voltage abnormality detection circuit 15 includes an R-phase reference circuit 51, an S-phase reference circuit 52, a T-phase reference circuit 53, and an FPGA 55 (hereinafter collectively referred to as reference circuits 51 to 53).

The R-phase reference circuit 51 divides the three-phase AC voltage output by the three-phase AC power supply 19, and the potential difference between the other S-phase and the T-phase, whichever is lower, becomes equal to or higher than a predetermined voltage with respect to the R-phase. Sometimes it outputs a pulse. The S-phase reference circuit 52 divides the three-phase AC voltage output by the three-phase AC power supply 19, and the potential difference between the other R phase and the lower T phase becomes equal to or higher than a predetermined voltage with the S phase as a reference. Sometimes it outputs a pulse. The T-phase reference circuit 53 divides the three-phase AC voltage output by the three-phase AC power supply 19, and the potential difference between the other R phase and the S phase, whichever is lower, becomes equal to or higher than a predetermined voltage with respect to the T phase. Sometimes it outputs a pulse. The FPGA 55 executes the main process (see FIG. 5) described later. The main process analyzes the pulses output by the reference circuits 51 to 53 and determines whether or not a voltage abnormality has occurred.

The configuration of the R-phase reference circuit 51 will be described with reference to FIG. The R-phase reference circuit 51 includes resistors 61 and 62, a shunt regulator 63, a photocoupler 64, a bypass capacitor 65, and the like. The resistors 61 and 62 divide the three-phase AC voltage output by the three-phase AC power supply 19 into the R phase, the S phase, and the T phase, respectively. The bypass capacitor 65 is connected in parallel with the resistor 62. The bypass capacitor 65 is connected to the signal line of the divided R-phase voltage to suppress fluctuations in the R-phase voltage. The shunt regulator 63 is turned on when the potential difference between the other S phase and the lower T phase on the basis of the R phase becomes equal to or higher than a predetermined voltage. When the shunt regulator 63 is turned on, the photocoupler 64 lights up and outputs a pulse to the FPGA 55. The shunt regulator 63 is turned off when the potential difference between the other S phase and the lower T phase is less than a predetermined voltage on the basis of the R phase. When the shunt regulator 63 is turned off, the photocoupler 64 is turned off.

The S-phase reference circuit 52 includes resistors 71 and 72, a shunt regulator 73, a photocoupler 74, a bypass capacitor 75, and the like. The resistors 71 and 72 divide the three-phase AC voltage output by the three-phase AC power supply 19 into the R phase, the S phase, and the T phase, respectively. The bypass capacitor 75 is connected in parallel with the resistor 72. The bypass capacitor 75 is connected to the signal line of the divided S-phase voltage to suppress fluctuations in the S-phase voltage. The shunt regulator 73 turns on when the potential difference between the other R phase and the lower T phase on the S phase basis becomes a predetermined voltage or more. When the shunt regulator 73 is turned on, the photocoupler 74 lights up and outputs a pulse to the FPGA 55. The shunt regulator 73 is turned off when the potential difference between the other R phase and the lower T phase on the S phase basis becomes less than a predetermined voltage. When the shunt regulator 73 is turned off, the photocoupler 74 is turned off.

The T-phase reference circuit 53 includes resistors 81 and 82, a shunt regulator 83, a photocoupler 84, a bypass capacitor 85, and the like. The resistors 81 and 82 divide the three-phase AC voltage output by the three-phase AC power supply 19 into the R phase, the S phase, and the T phase, respectively. The bypass capacitor 85 is connected in parallel with the resistor 82. The bypass capacitor 85 is connected to the signal line of the divided T-phase voltage to suppress fluctuations in the T-phase voltage. The shunt regulator 83 turns on when the potential difference between the other R phase and the S phase, whichever is lower, becomes a predetermined voltage or more based on the T phase. When the shunt regulator 83 is turned on, the photocoupler 84 lights up and outputs a pulse to the FPGA 55. The shunt regulator 83 is turned off when the potential difference between the other R phase and the S phase, whichever is lower, is less than a predetermined voltage on the basis of the T phase. When the shunt regulator 83 is turned off, the photocoupler 84 is turned off.

The operation of the R-phase reference circuit 51 will be described with reference to FIGS. 2 and 3. The waveform at the bottom of FIG. 3 is a voltage curve in which the three phases of RST are input. Each voltage curve is a sine curve and is 120 degrees out of phase. The three upper waveforms in FIG. 3 are conceptual diagrams of each pulse waveform when the R phase reference, the S phase reference, and the T phase reference are used in this order from the top. Each conceptual diagram shows a pulse waveform having a potential difference of a predetermined voltage or more (for example, 152.5 V or more) so that the explanation is easy to understand. If the potential difference is less than the predetermined voltage, the pulse voltage is set to zero.

As described above, the R-phase reference circuit 51 outputs a pulse when the potential difference between the lower of the other S-phase and the T-phase and the R-phase becomes equal to or higher than a predetermined voltage on the basis of the R-phase. For example, the inside of the frame surrounded by the alternate long and short dash line shown in FIG. 3 will be described. At t1, the voltage of the S phase is lower than that of the T phase, and the potential difference between the R phase and the S phase is the same. When the voltage of the S phase is lower than that of the T phase, the voltage is applied in the direction of the dotted arrow A in the R phase reference circuit 51 as shown in FIG. After t1, a potential difference gradually occurs between the R phase and the S phase, and reaches a predetermined voltage or more at t2. The shunt regulator 63 is turned on. A current flows between the K terminal (cathode terminal) and the A terminal (anode terminal) of the shunt regulator 63. The photocoupler 64 lights up and outputs a pulse to the FPGA 55. The pulse rises from t2 and reaches a constant value. The potential difference between the R phase and the S phase gradually decreases.

At t3, the S phase and the T phase are reversed. The pulse drops slightly at t3. After t3, the voltage of the T phase becomes lower than that of the S phase. Therefore, as shown in FIG. 2, the voltage is applied in the direction of the arrow B of the alternate long and short dash line in the R phase reference circuit 51. After t3, a potential difference of a predetermined voltage or more is generated between the R phase and the T phase, so that the pulse rises again and reaches a constant value. The potential difference between the R phase and the T phase gradually decreases and becomes less than a predetermined voltage at t4. The shunt regulator 63 is turned off. The photocoupler 64 is turned off. The pulse becomes zero at t4. The pulse output by the R-phase reference circuit 51 repeats the waveforms from t2 to t4 at regular intervals.

The S-phase reference circuit 52 and the T-phase reference circuit 53 operate in the same manner as the R-phase reference circuit 51. As shown in FIG. 3, the S-phase and T-phase pulse waveforms are out of phase with the R-phase pulse waveform. The R-phase pulse, S-phase pulse, and T-phase pulse are output to the FPGA 55 in the RST phase order, respectively. The FPGA 55 executes the main process based on each pulse output by the reference circuits 51 to 53.

<Threshold table 14A>
FIG. 4 shows a threshold table 14A stored in the non-volatile storage device 14. The threshold table 14A stores a first threshold value for detecting an overvoltage in the main process described later and a second threshold value for detecting a voltage drop in the main process described later. The first threshold and the second threshold are associated with each of a plurality of frequency ranges. The plurality of frequency ranges are based on a range including 50 Hz or 60 Hz, which is the reference voltage of the three-phase AC power supply 19, (thick line frame in the figure), and each defines a range of 5 Hz.

Further, the first threshold value and the second threshold value are set to each of the conditions (first condition to third condition, hereinafter referred to as "circuit condition") corresponding to the parameters of the bypass capacitors 65, 75, 85 (see FIG. 2). It is associated. The circuit conditions are, for example, the frequency characteristics (cutoff frequency) of the bypass capacitors 65, 75, 85 and the like. Hereinafter, the first threshold value and the second threshold value corresponding to the i-th condition (i is any one of 1 to 3) are referred to as "first threshold value (i)" and "second threshold value (i)", respectively.

<Main processing>
The main process will be described with reference to FIG. The main process is executed by FPGA55. The FPGA 55 receives an instruction capable of specifying the circuit condition (the i-condition) for determining the first threshold value and the second threshold value (S11). For example, the FPGA 55 may directly accept circuit conditions via the input device 17. Further, for example, the FPGA 55 may indirectly accept the circuit condition by accepting the setting information of the setting switch (DIP switch or the like) (not shown). The FPGA 55 may accept the setting information of the setting switch as an instruction that can specify the circuit condition and specify the circuit condition. The FPGA 55 determines the first threshold value (i) and the second threshold value (i) corresponding to the received circuit conditions based on the threshold value table 14A (S11).

The FPGA 55 receives the pulse information of the RST phase (S13). The pulse information is pulse information output by the R-phase reference circuit 51, the S-phase reference circuit 52, and the T-phase reference circuit 53, respectively. Next, the FPGA 55 measures the pulse width and the pulse period for each phase based on the pulse information (S15). As shown in FIG. 6, the pulse is repeated at regular intervals. t7 is the time when the pulse rises from the reference voltage. The reference voltage is, for example, a constant voltage of 152.5V. t8 is the time when the pulse reaches the maximum voltage. t9 is the time when the pulse starts to drop from the maximum voltage. t10 is the time when the pulse drops to the reference voltage. t11 is the time when the next pulse rises from the reference voltage. The pulse width is the time from t7 to t10. The pulse period is the time from t7 to t11. The pulse width may be the time from t8 to t9.

As shown in FIG. 5, the FPGA 55 calculates the frequency of the three-phase AC power supply 19 for each phase based on the pulse period measured for each phase (S17). The FPGA 55 specifies the frequency range including the calculated frequency from the plurality of frequency ranges of the threshold table 14A for each phase. Of the first threshold value (i) and the second threshold value (i) determined by S11, the FPGA 55 has a first threshold value (i) (referred to as “first threshold value Th1”) and a second threshold value corresponding to the specified frequency range. (I) (referred to as "second threshold Th2") is specified for each phase (S19). The FPGA 55 calculates the ratio of the pulse width to the pulse period as the duty ratio for each phase of the RST (S21).

The FPGA 55 executes a first determination process (see FIG. 7) in order to determine whether or not an overvoltage has occurred (S23). The first determination process will be described with reference to FIG. 7. The FPGA 55 determines whether the duty ratio of two or more phases is larger than the first threshold Th1 (S41). When the FPGA 55 determines that the duty ratio of two or more phases is larger than the first threshold Th1 (S41: YES), it determines that an overvoltage has occurred in the AC voltage (S45). The FPGA 55 ends the first determination process and returns the process to the main process (see FIG. 5). When the FPGA 55 determines that the duty ratio of two or more phases is not larger than the first threshold value (S41: NO), the processing proceeds to S43. The FPGA 55 determines whether the duty ratio of any of the three phases has become larger than the first threshold Th1 three times in a row (S43). When it is determined that the duty ratio of any one of the three phases is not larger than the first threshold Th1 three times in a row (S43: NO), the FPGA 55 ends the first determination process and mainly performs the process. Return to processing (see FIG. 5).

As shown in FIG. 5, after the completion of the first determination process (S23), the FPGA 55 executes a second determination process (see FIG. 8) in order to determine whether or not a voltage drop has occurred (S25). The second determination process will be described with reference to FIG. The FPGA 55 determines whether or not the reference circuit having two or more phases among the reference circuits 51 to 53 continuously outputs a pulse for 50 ms or more (S61). When the FPGA 55 determines that the reference circuit having two or more phases does not continuously output a pulse for 50 ms or more (S61: YES), it determines that a voltage drop has occurred in the AC voltage (S71). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5). When the FPGA 55 determines that the two-phase or more reference circuit outputs a pulse within 50 ms (S61: NO), the FPGA 55 advances the process to S63.

The FPGA 55 determines whether the frequency of each phase calculated by the process of S17 (see FIG. 6) is closer to 50 Hz than 60 Hz (S63). When the FPGA 55 determines that the frequency is close to 50 Hz (S63: YES), the processing proceeds to S65. The FPGA 55 determines whether all the duty ratios of the three phases have become smaller than the second threshold Th2 three times in a row (S65). When the FPGA 55 determines that all the duty ratios of the three phases are not smaller than the second threshold Th2 three times in a row (S65: NO), the second determination process is terminated and the process is the main process (FIG. 5). See).

On the other hand, when the FPGA 55 determines that the frequency of each phase is closer to 60 Hz than 50 Hz (S63: NO), the processing proceeds to S67. The FPGA 55 determines whether all the duty ratios of the three phases have become smaller than the second threshold Th2 four times in a row (S67). When the FPGA 55 determines that all the duty ratios of the three phases are not smaller than the second threshold Th2 four times in a row (S67: NO), the second determination process is terminated and the process is the main process (FIG. 5). See).

As shown in FIG. 5, after the completion of the second determination process (S25), the FPGA 55 undergoes at least one of an overvoltage and a voltage drop in the AC voltage by the first determination process (S23) and the second determination process (S25). It is determined whether or not it has occurred (S27). When the FPGA 55 determines that neither an overvoltage nor a voltage drop has occurred in the AC voltage (S27: NO), the processing is returned to S13. The FPGA 55 repeats the processes of S13 to S25.

When the FPGA 55 repeats the first determination process (S23) shown in FIG. 7 and determines that the duty ratio of any one of the three phases becomes larger than the first threshold Th1 three times in a row (S43: YES). , It is determined that an overvoltage has occurred in the AC voltage (S45). The FPGA 55 ends the first determination process and returns the process to the main process (see FIG. 5).

The FPGA 55 repeats the second determination process (S25) shown in FIG. 8, the frequency calculated by the process of S17 (see FIG. 6) is closer to 50 Hz than 60 Hz (S63: YES), and all the duty ratios of the three phases are set. When it is determined that the second threshold value Th2 is smaller than the second threshold value Th2 three times in a row (S65: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5). Further, when the FPGA 55 determines that the frequency calculated by the processing of S17 is closer to 60 Hz than 50 Hz (S63: NO) and the duty ratios of all three phases are smaller than the second threshold Th2 four times in a row ( S67: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). The FPGA 55 ends the second determination process and returns the process to the main process (see FIG. 5).

As shown in FIG. 5, when the FPGA 55 determines that at least one of an overvoltage and a voltage drop has occurred in the AC voltage by the first determination process (S23) and the second determination process (S25) (S27: YES). , The process proceeds to S29. The FPGA 55 outputs the determination result to the CPU 11 (S29). Based on the output determination result, the CPU 11 displays the notification information notifying the occurrence of overvoltage and voltage drop on the display device 18. The FPGA 55 ends the main process.

<Action and effect of this embodiment>
The voltage abnormality detection circuit 15 has bypass capacitors 65, 75, 85 connected in parallel to resistors 62, 72, 82 provided in the voltage signal line of each phase of the three-phase AC power supply 19. The non-volatile storage device 14 of the numerical control device 1 corresponds to a plurality of frequency ranges of the first threshold value (i) and the second threshold value (i) for each circuit condition (i-th condition) of the bypass capacitors 65, 75, 85. The threshold table 14A attached and stored is stored. The numerical control device 1 directly or indirectly accepts the circuit conditions, and determines the first threshold value (i) and the second threshold value (i) corresponding to the accepted circuit conditions based on the threshold value table 14A (S11). .. The numerical control device 1 identifies the frequencies of each phase (R phase, S phase, T phase) of the three-phase AC voltage (S17), and sets the corresponding first threshold Th1 and second threshold Th2 based on the threshold table 14A. (S19). The numerical control device 1 determines whether an overvoltage and a voltage drop occur in the three-phase AC voltage according to the relationship between the specified first threshold Th1 and second threshold Th2 and the duty ratio of the three-phase AC voltage (S23, S25). At this time, even when the frequency of the three-phase AC voltage fluctuates according to the circuit conditions of the bypass capacitors 65, 75, 85, the numerical control device 1 sets the first threshold Th1 and the second threshold Th2 corresponding to the fluctuated frequencies. Based on this, it can be determined whether or not there is an abnormality in the three-phase AC voltage. Therefore, the numerical control device 1 can accurately detect whether or not there is an abnormality in the three-phase AC voltage.

The three-phase AC power supply 19 is a three-phase (R-phase, S-phase, T-phase) AC power supply. The reference circuits 51 to 53 divide the three-phase AC voltage into the R phase, the S phase, and the T phase. Therefore, the numerical control device 1 can accurately determine whether or not there is an abnormality in the voltage of the three-phase AC power supply 19 based on the voltage of each phase.

In the numerical control device 1, when the duty ratio of two or more phases among the R phase, S phase, and T phase divided by the reference circuits 51 to 53 is larger than the first threshold Th1 (S41: YES), the AC voltage has an overvoltage. It is determined that it has occurred (S45). At this time, the numerical control device 1 can accurately determine the overvoltage of the AC voltage. In the numerical control device 1, when the duty ratio of two or more of the three phases is not larger than the first threshold Th1 (S41: NO), and the duty ratio of any one of the three phases is greater than the first threshold Th1. When it is large three times or more continuously (S43: YES), it is determined that an overvoltage has occurred in the AC voltage (S45). At this time, the numerical control device 1 can determine the overvoltage of the AC voltage with higher accuracy.

The reference circuits 51 to 53 output a pulse signal when the potential difference between the divided R phase, S phase, and T phase and the other two phases having the smaller voltage is equal to or greater than a predetermined voltage. The numerical control device 1 determines that a voltage drop has occurred in the AC voltage when the pulse signals of two or more phases among the pulse signals corresponding to the three phases are not transmitted from the reference circuits 51 to 53 for 50 ms or more (S61: YES). (S71). At this time, the numerical control device 1 can accurately determine the voltage drop of the AC voltage. When the numerical control device 1 determines that the reference circuit of two or more phases outputs a pulse within 50 ms (S61: NO), and the duty ratio of the three phases is a predetermined number of times (three or four times) from the second threshold Th2. ) When it is continuously small (S65: YES, S67: YES), it is determined that a voltage drop has occurred in the AC voltage (S71). At this time, the numerical control device 1 can determine the voltage drop of the AC voltage with higher accuracy.

The numerical control device 1 is used when the frequency of each phase of the AC voltage is closer to 50 Hz than 60 Hz (S63: YES), and when all the duty ratios of the three phases are smaller than the second threshold Th2 three times in a row (S65). : YES), it is determined that there is an abnormality in the AC voltage (S71). The numerical controller 1 is when the frequency of each phase of the AC voltage is closer to 60 Hz than 50 Hz (S63: NO), and when all the duty ratios of the three phases are smaller than the second threshold Th2 four times in a row (S67: YES). ), It is determined that there is an abnormality in the AC voltage (S71). That is, the numerical control device 1 increases the number of times of comparison with the second threshold value Th2 as the frequency of each phase of the AC voltage is relatively large. The time until the determination by the above method is completed corresponds to a value obtained by multiplying the reciprocal of the frequency by the number of comparisons with the second threshold Th2. Therefore, the numerical control device 1 can equalize the time until the determination of whether or not there is an abnormality in the AC voltage is completed regardless of the frequency of each phase of the AC voltage.

The FPGA 55 outputs to the CPU 11 a determination result of whether an overvoltage and a voltage drop have occurred in the AC voltage (S29). Based on the output determination result, the CPU 11 displays the notification information notifying the occurrence of overvoltage and voltage drop on the display device 18. At this time, the numerical control device 1 can notify the outside of the occurrence of a voltage abnormality.

<Modification example>
The present invention is not limited to the above embodiment. Although the numerical control device 1 has detected an abnormality in the three-phase AC voltage, it may detect an abnormality in the two-phase AC voltage or an abnormality in the AC voltage of three or more phases. The numerical control device 1 may include another light receiving element device (for example, an optical MOSFET) instead of the photocouplers 64, 74, 84 of each reference circuit 51 to 53. The CPU 11 may stop the operation of the machine tool 2 based on the determination result output by the FPGA 55. Although the FPGA 55 calculates the duty ratio from the pulse width and the pulse period, the overvoltage or voltage drop may be determined only by the pulse width. The threshold table 14A may store the first threshold and the second threshold of the maximum value of the divided voltage. The FPGA 55 may determine the occurrence of overvoltage and voltage drop by comparing the maximum voltage of the voltage with the first threshold and the second threshold instead of the duty ratio. In the above embodiment, the numerical control device 1 has been described as an embodiment of the voltage abnormality detection device of the present invention, but the voltage abnormality detection device may be independent of the numerical control device 1. Various parameters (three times, four times, 50 ms, etc.) in the first determination process and the second determination process can be changed even if they are examples.

In the threshold value table 14A, the first threshold value (i) and the second threshold value (i) are associated with the circuit conditions (the i-th condition) corresponding to the parameters of the bypass capacitors 65, 75, and 85, and stored for each frequency range. The threshold table 14A may associate the first threshold (i) and the second threshold (i) with circuit conditions different from the parameters of the bypass capacitors 65, 75, 85. For example, the reference circuits 51 to 53 may include a low-pass filter and a high-pass filter that suppress fluctuations in the divided voltage. In the threshold value table 14A, the first threshold value (i) and the second threshold value (i) may be associated with the frequency characteristics of the low-pass filter and the high-pass filter as circuit conditions.

The FPGA 55 may determine that the AC voltage is abnormal only when the duty ratio of two or more phases out of the three phases is larger than the first threshold Th1 (S41: YES) (S45). At that time, the FPGA 55 does not have to execute the process of S43. The FPGA 55 may determine that the AC voltage is abnormal only when the duty ratio of any of the three phases is continuously larger than the first threshold Th1 three times or more (S43: YES) (S45). .. At that time, the FPGA 55 does not have to execute the process of S41.

The FPGA 55 may determine that a voltage drop has occurred in the AC voltage only when the reference circuits 51 to 53 do not output a pulse signal of two or more phases for 50 ms or more (S61: YES). At this time, the FPGA 55 does not have to execute the processes of S65 and S67. The FPGA 55 determines that a voltage drop has occurred in the AC voltage only when the duty ratio of the three phases is continuously smaller than the second threshold Th2 a predetermined number of times (three or four times) (S65: YES, S67: YES). It may be done (S71). At that time, the FPGA 55 does not have to execute the process of S61.

The FPGA 55 may have the same number of determinations at the time of determination by the processing of S65 or S67. That is, the FPGA 55 may have a common number of determinations when the duty ratios of all three phases are smaller than the second threshold Th2, regardless of the frequency of each phase of the AC voltage.

<Others>
Reference circuits 51 to 53 are examples of the voltage dividing means and the pulse output means of the present invention. The first threshold value and the second threshold value are examples of the reference information of the present invention. The non-volatile storage device 14 that stores the threshold table 14A is an example of the “storage unit” of the present invention. The FPGA 55 that executes the process of S11 is an example of the determination means of the present invention. The FPGA 55 that executes the process of S17 is an example of the first specific means of the present invention. The FPGA 55 that executes the process of S19 is an example of the second specific means of the present invention. The FPGA 55 that executes the processes of S23 and S25 is an example of the determination means of the present invention. The FPGA 55 that performs the processing of S29 is an example of the result output means of the present invention.

14: Non-volatile storage device 14A: Threshold table 15: Voltage abnormality detection circuit 19: Three-phase AC power supply 51, 52, 53: Reference circuit 55: FPGA
65, 75, 85: Bypass capacitor

Claims (7)

A voltage abnormality detection device that detects abnormalities in the voltage of a three-phase AC power supply including R-phase, S-phase, and T-phase.
It is a voltage dividing means including a first set resistor, a second set resistor, and a third set resistor that divides the three-phase AC power supply into R phase, S phase, and T phase, and is composed of three reference circuits .
The first set resistor, the second set resistor, and the third set resistor each include two resistors connected in series.
The potential difference between the first set resistor, the bypass capacitor connected in parallel to one of the two resistors included in the first set resistor, and the lower of the other S phase and T phase based on the R phase. An R-phase reference circuit that includes at least a pulse output unit that outputs a pulse signal when the voltage exceeds a predetermined voltage, and
The potential difference between the second set resistor, the bypass capacitor connected in parallel to one of the two resistors included in the second set resistor, and the lower of the other R phase and T phase based on the S phase. An S-phase reference circuit that includes at least a pulse output unit that outputs a pulse signal when the voltage exceeds a predetermined voltage, and
The potential difference between the third set resistor, the bypass capacitor connected in parallel to one of the two resistors included in the third set resistor, and the lower of the other R phase and S phase based on the T phase. A voltage dividing means including at least a T-phase reference circuit including a pulse output unit that outputs a pulse signal when the voltage exceeds a predetermined voltage , and
The bypass capacitor provides reference information that defines the duty ratio threshold, which is the ratio of the pulse width to the pulse period of the pulse signal output by the pulse output unit of each of the three reference circuits, for each frequency of the three-phase AC power supply. A storage unit that stores a table associated with each circuit condition showing the frequency characteristics of
Identifiable indication the circuit condition, directly or accepted through the input device, or, indirectly accepted on the basis of the setting information of the setting switch, accepted among the tables stored in the storage unit determining means for determining the reference information for each of the frequency which is correlated to the circuit condition in which the instruction is identified,
Based on said pulse signal, each output of the three reference circuit measures the pulse width and the pulse period for each phase, based on the pulse period measured for each phase, the said frequency of the three-phase AC power supply for each phase The first specific means to identify and
Among the reference information for each of the frequency determined by the determination unit, a second specifying unit that specific for each phase of the reference information that is correlated to the frequency identified by said first identifying means,
The ratio of the pulse width to the pulse period of the pulse signal output by the pulse output unit of each of the three reference circuits and the threshold defined by the reference information specified for each phase by the second specific means. A voltage abnormality detecting device provided with a determination means for determining whether or not there is an abnormality in the voltage of the three-phase AC power supply based on a magnitude relationship with a certain duty ratio. The determination means of the pulse signal the pulse output unit of each of the three criteria circuit outputs the duty ratio of the pulse signal on the two or more is detected an overvoltage of defined the threshold by the reference information the first time threshold is greater than for, the abnormal voltage detecting apparatus according to claim 1, overvoltage voltage of the three-phase AC power source and judging to have occurred. The determination means
The duty ratio of the pulse signal output by the pulse output unit of each of the three reference circuits is repeatedly compared with the first threshold value for detecting an overvoltage among the threshold values defined by the reference information.
When the duty ratio of any of the pulse signals output by each of the three reference circuits is continuously larger than the first threshold value by a predetermined number of times or more, it is determined that an overvoltage has occurred in the voltage of the three-phase AC power supply. The voltage abnormality detecting device according to claim 1. Said determining means, on the two or more of the pulse outputs of each of the three reference circuits, when no output pulse signal for a predetermined time or more, it is determined that the voltage drop in the voltage of the three-phase AC power supply occurs The voltage abnormality detecting device according to claim 1. The determination means
The duty ratio of the pulse signal output by the pulse output unit of each of the three reference circuits is repeatedly compared with the second threshold value for detecting a voltage drop among the threshold values defined by the reference information.
When the duty ratio of the pulse signal output by each of the three reference circuits is continuously smaller than the second threshold value by a predetermined number of times or more, it is determined that a voltage drop has occurred in the voltage of the three-phase AC power supply. The voltage abnormality detection device according to claim 1. The higher the pulse output unit is large the frequency of the pulse signal output, voltage abnormality detection device according to claim 5, wherein the predetermined number of times is larger. The voltage abnormality detecting device according to any one of claims 1 to 6 , further comprising a result output means for outputting a determination result by the determination means.

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