JP6061536B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a display device having a top gate thin film transistor.

  In a thin film transistor having a top gate structure using polysilicon (p-Si), an end portion of a semiconductor film containing polysilicon is generally tapered. Since the semiconductor film is thin at this end, the threshold voltage is low. For this reason, in the drain current-gate voltage curve, a stepped hump characteristic occurs at a voltage lower than the threshold voltage of the central portion other than the end portion, making it difficult to manage the threshold voltage of the transistor.

  Patent Document 1 discloses a technique for suppressing the hump characteristics by increasing the dopant concentration of the semiconductor film as it goes down.

JP 2002-343976 A

  It is not always easy to suppress the hump characteristics by the method shown in Patent Document 1. This is because it is difficult to control the dopant concentration in the height direction. Further, when a plurality of dopants are implanted by ion doping, there is a problem that the cost increases.

  The present application has been made in view of the above problems, and an object thereof is to provide a technique for suppressing the hump characteristics of a thin film transistor having a top gate structure using polysilicon (p-Si) by a method different from the conventional one. is there.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A gate electrode including a first side and a second side opposite to each other in plan view, a source electrode, a drain electrode, and the gate electrode provided below the gate electrode. A first portion that overlaps with the first portion, a second portion that is connected to the first portion below the first side and connected to the source electrode, and a first portion that is connected to the source electrode A semiconductor film including a third portion connected to the drain electrode and connected to the drain electrode, and an insulating film provided between the gate electrode and the semiconductor film. A portion of the outer periphery of the semiconductor film that overlaps with the gate electrode is connected to the first side and the second side and has an electric field direction from one of the first side and the second side toward the other side. A display device characterized by not being an extended line segment.

  (2) In the display device according to (1), the gate electrode has a hole, and the hole overlaps with an outer periphery of the semiconductor film in a plan view.

  (3) In (1), the length of the line connecting the first side and the second side of the outer periphery of the first portion in plan view is the first side and the second side A display device characterized in that it is longer than the distance to the side.

  (4) In (3), a line connecting the first side and the second side of the outer periphery of the first portion is orthogonal to the first side and the second side in plan view. A display device characterized by not.

  (5) In (3), the line connecting the first side and the second side of the outer periphery of the first part in plan view is the line between the first side and the second side. A display device characterized by bending between.

  (6) In (5), the width of the first portion in the direction orthogonal to the direction of the electric field is maximum between the first side and the second side. Display device.

  (7) In (5), the width of the first portion in the direction orthogonal to the direction of the electric field is minimal between the first side and the second side. Display device.

  (8) In the display in (5), the line connecting the first side and the second side of the outer periphery of the first portion in plan view is a step-like line. apparatus.

  (9) A gate electrode including a first side and a second side opposite to each other in plan view, a source electrode, a drain electrode, a channel semiconductor film, and a protruding semiconductor provided below the gate electrode A semiconductor layer having a film, and an insulating film provided between the gate electrode and the semiconductor layer, and the channel semiconductor layer includes a first portion overlapping the gate electrode in plan view, A second portion connected to the first portion and connected to the source electrode below the first side, and a drain portion connected to the first portion and connected to the source electrode below the second side. And the protruding semiconductor film is disposed at a predetermined distance from or in contact with the first portion. .

  (10) The display device according to (9), wherein the protruding semiconductor film is provided between the first side and the second side.

  (11) In (9), the protruding semiconductor film intersects the first side and the second side in a plan view and is arranged at a predetermined interval from the outer periphery of the channel semiconductor film. A display device characterized by that.

  According to the present invention, the hump characteristics of a top-gate thin film transistor using polysilicon can be suppressed by a method different from the conventional one.

It is a circuit diagram which shows an example of the equivalent circuit of the liquid crystal display device concerning 1st Embodiment. It is a top view which shows an example of the thin-film transistor concerning 1st Embodiment. It is sectional drawing in the III-III cut line of the thin-film transistor shown in FIG. It is a top view which shows the comparative example of a thin-film transistor. FIG. 5 is a diagram showing drain current-gate voltage characteristics of the thin film transistor shown in FIG. 4. It is a top view which shows an example of the thin-film transistor concerning 2nd Embodiment. It is a top view which shows another example of the thin-film transistor concerning 2nd Embodiment. It is a top view which shows another example of the thin-film transistor concerning 2nd Embodiment. It is a top view which shows another example of the thin-film transistor concerning 2nd Embodiment. It is a top view which shows an example of the thin-film transistor concerning 3rd Embodiment. It is sectional drawing in the XI-XI cutting line of the thin-film transistor shown in FIG. It is a top view which shows another example of the thin-film transistor concerning 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Of the constituent elements that appear, those having the same function are given the same reference numerals, and the description thereof is omitted. Hereinafter, a case where the present invention is applied to an IPS liquid crystal display device which is a kind of display device will be described.

[First Embodiment]
In the first and second embodiments of the present invention, the planar positional relationship between the semiconductor film SF and the gate electrode GE constituting the channel of the thin film transistor TR having the top gate structure using polysilicon is humped. The characteristic is suppressed.

  A liquid crystal display device according to a first embodiment includes an array substrate, a filter substrate facing the array substrate and provided with a color filter, a liquid crystal material sealed in a region sandwiched between these substrates, an array And a backlight that emits light from the outside of the substrate.

  FIG. 1 is a circuit diagram illustrating an example of an equivalent circuit of the liquid crystal display device according to the first embodiment. The array substrate includes a plurality of gate signal lines GL, a plurality of video signal lines DL, a plurality of common lines CL, a plurality of pixel electrodes PT, a plurality of common electrodes CT, a plurality of thin film transistors TR, a video signal line drive circuit XDV, a gate. A scanning circuit YDV and the like are arranged. The plurality of gate signal lines GL extend in the horizontal direction side by side in the display area on the array substrate, and the plurality of video signal lines DL extend in the vertical direction side by side in the display area. One end of these video signal lines DL is connected to the video signal line drive circuit XDV, and one end of the gate signal line GL is connected to the gate scanning circuit YDV. Each of the common lines CL has a one-to-one correspondence with the gate signal line GL, and the common line CL extends in the lateral direction above the corresponding gate signal line GL.

  A portion surrounded by the gate signal line GL, the common line CL corresponding to the gate signal line GL, and the adjacent video signal line DL is a pixel circuit. The plurality of pixel circuits are arranged in a matrix. Each pixel circuit includes a thin film transistor TR, a pixel electrode PT, and a common electrode CT. The thin film transistor TR includes a source electrode SE, a drain electrode DE, and a gate electrode GE. The drain electrode DE is connected to the video signal line DL, and the source electrode SE is connected to the pixel electrode PT. The common electrode CT is connected to the common line CL. The pixel electrode PT and the common electrode CT constitute a capacitor via a liquid crystal. The gate electrode GE of the thin film transistor TR is connected to the gate signal line GL via the wiring WL. When the on voltage of the scanning pulse is supplied from the gate scanning circuit YDV, the thin film transistor TR is turned on and the video signal line driving circuit XDV is turned on. The above-described capacitor stores a potential difference based on the potential of the video signal supplied through the video signal line DL. The transmittance of the liquid crystal is changed by the electric field generated by this potential difference, and the light quantity of each pixel is controlled. Note that the thin film transistor TR has no polarity, and the names of the source electrode SE and the drain electrode DE are determined by the direction of the voltage for convenience. Therefore, the connection destinations may be reversed.

  FIG. 2 is a plan view showing an example of the thin film transistor TR according to the first embodiment. 3 is a cross-sectional view taken along the line III-III of the thin film transistor TR shown in FIG. Here, the thin film transistor TR according to the first embodiment has a top gate structure in which the polysilicon semiconductor film SF is used as a channel and the gate electrode GE is above the semiconductor film SF constituting the channel.

  A semiconductor film SF is provided on the array substrate, and a gate insulating film GI is provided over the semiconductor film SF so as to cover the semiconductor film SF. The upper surface of the semiconductor film SF has a region connected to the source electrode SE and a region connected to the drain electrode DE. When the semiconductor film SF is viewed in a plan view, a band shape is formed so as to connect the source electrode SE and the drain electrode DE. It extends to. The gate electrode GE is in an upper layer of the gate insulating film GI and extends in a band shape so as to intersect the semiconductor film SF between the source electrode SE and the drain electrode DE in a plan view. To the gate signal line GL.

  In plan view, a side near the source electrode SE on the outer periphery of the gate electrode GE is called a first side, and a side near the drain electrode DE is called a second side. The first side and the second side are parallel. In addition, the outer periphery of the portion of the semiconductor film SF extending in a strip shape so as to connect the source electrode SE and the drain electrode DE includes two sides orthogonal to the first side and the second side. In the following description, a portion of the semiconductor film SF that overlaps the gate electrode GE in a plan view is connected to the first portion and the first portion below the first side and extends to connect to the source electrode SE. The second part and the part extending below the second side so as to connect to the first part and connect to the drain electrode DE are referred to as a third part.

  The gate electrode GE has two slit holes SL in the central portion between the first side and the second side. Here, a portion whose distance from the outer periphery of the semiconductor film SF is equal to or less than a constant and has a tapered cross section is a side portion SP, and a portion inside the side portion SP is a main body portion MP. In a plan view, each of the slit holes SL has a portion that overlaps the side portion SP and a portion that does not overlap the semiconductor film SF. Therefore, each of the slit holes SL also overlaps a part of the outer periphery of the semiconductor film SF. Thereby, only the side portion SP has a multi-gate structure.

  In the semiconductor film SF serving as the channel of the thin film transistor TR, the electric field E is directed from the second side toward the first side (or the opposite direction). Further, when an on-voltage is applied to the gate electrode GE, the resistance of the portion overlapping the gate electrode GE is reduced in plan view. For these reasons, the portion where the current easily flows in the first portion of the semiconductor film SF is the portion of the channel width W of FIG. 2 corresponding to the main body portion MP among the portions where the gate electrode GE and the semiconductor film SF overlap. It becomes. In this portion, since the current flows along a line that connects the first side and the second side and extends in the direction of the electric field E, the on-resistance becomes the lowest. On the other hand, the side portion SP does not have the gate electrode GE above a part thereof, and a portion where the first side and the second side are connected and the gate electrode GE and the side portion SP are planarly overlapped in the direction of the electric field E. There are no extending line segments. For this reason, the on-resistance becomes larger than that of the main body portion MP.

  FIG. 4 is a plan view showing a comparative example of the thin film transistor TR. Since the gate electrode GE of the thin film transistor TR shown in FIG. 4 does not have the slit hole SL, the ON resistance of the side portion SP is smaller than the example of FIG. FIG. 5 is a graph showing drain current (ID) -gate voltage (VG) characteristics of the thin film transistor TR shown in FIG. In this example, since the threshold voltage of the side portion SP is lower than that of the main body portion MP, the side MOS component ES indicating that the drain current flows through the side portion SP and the main body MOS component EM indicating that the drain current flows through the main body portion MP. Are clearly separated, and hump h is observed at the gate voltage VG therebetween.

  On the other hand, in the thin film transistor TR according to the first embodiment, the on-resistance of the side portion SP is increased, and the current flowing due to the hump h is reduced and the threshold current is shifted in the positive direction. Thereby, the hump characteristic of the thin film transistor TR can be suppressed.

  Next, a manufacturing process of a liquid crystal display device including the above-described thin film transistor TR will be described. First, a contamination prevention film, a light shielding film, and a semiconductor layer are sequentially laminated on a transparent substrate. Next, the semiconductor layer is patterned into the shape of the semiconductor film SF by dry etching using a resist pattern. A gate insulating film GI is laminated on the upper layer by, for example, silicon dioxide, and a gate electrode GE is formed on the upper layer through film formation and patterning by a conductive metal sputtering method. Next, ion doping of impurities such as phosphorus and boron is performed on the semiconductor film SF. Here, even if ions are implanted into the side portion SP below the slit hole SL, the on-resistance increasing effect by the multi-gate can be obtained with respect to the characteristics of the thin film transistor TR. However, when a low ion concentration region for the purpose of electric field relaxation is formed in the vicinity of the gate electrode at the time of ion doping for forming the source / drain, it is desirable that the slit hole SL is also ion-doped after being covered with a photoresist.

  Thereafter, an interlayer insulating film made of silicon dioxide or the like is laminated by a CVD method. In the interlayer insulating film, a contact hole is provided in a portion connecting the semiconductor film SF and the source electrode SE or the drain electrode DE, and the source electrode SE and the drain electrode DE are formed thereon. More specifically, the source electrode SE and the drain electrode DE are formed by a step of sequentially stacking a barrier metal layer, a main wiring layer, and a cap metal layer, and a step of patterning the three stacked layers by photolithography and etching. The

[Second Embodiment]
The liquid crystal display device according to the second embodiment is different from the first embodiment in the shapes of the gate electrode GE and the semiconductor film SF. Below, it demonstrates centering on a different part from 1st Embodiment.

  FIG. 6 is a plan view showing an example of a thin film transistor TR according to the second embodiment. In a plan view, a portion of the semiconductor film SF extending in a strip shape so as to connect the source electrode SE and the drain electrode DE crosses the gate electrode GE obliquely, and that portion (including the first portion). The outer periphery is two line segments that intersect with the first side and the second side in a direction that is not orthogonal. Note that the slit hole SL does not exist in a portion where the gate electrode GE and the semiconductor film SF overlap in plan view.

  In such a thin film transistor TR, the portion where the current is most likely to flow out of the first portion is the two line segments out of the perpendicular lines extending from the intersection of the first side and the above-described two line segments to the second side. 6 and a portion between the second line and the line between the two line segments out of the perpendicular lines extending from the intersection of the second line and the above-mentioned two line segments, that is, FIG. This is the portion indicated by the channel width W. The side portion SP does not exist at least in a portion where the current flows most easily. Further, the path b from the first side to the second side of the side portion SP (the outer periphery of the first portion) is larger than the channel length a that is the distance between the first side and the second side. That is, since the path b of the side portion SP is longer than the channel length a where the current flows most easily, the resistance of the side portion SP is larger than the portion where the current mainly flows. For these reasons, the on-resistance of the side portion SP is larger than that of the main body portion MP. As a result, the on-resistance of the thin film transistor TR shown in FIG. As a result, the current flowing by hump h decreases and the threshold current shifts in the positive direction, and the hump characteristics can be suppressed.

  The shape of the semiconductor film SF may be different from that shown in FIG. FIG. 7 is a plan view showing another example of the thin film transistor TR according to the second embodiment. In a plan view, a line connecting the first side and the second side in the outer periphery of the first portion is a line that bends between the first side and the second side. Further, the width of the first portion of the semiconductor film SF as viewed in the direction of the electric field E is maximized between the first side and the second side. More specifically, the width at the center between the first side and the second side is larger than the width of the first side and the width of the second side.

  In such a thin film transistor TR, the portion where the current flows most easily in the first portion is the portion having the smallest width, that is, the portion indicated by the channel width W in FIG. Also in this case, at least a part of the side portion SP does not exist in the portion where the current flows most easily, and the path b from the first side to the second side of the outer periphery of the first portion (corresponding to the side portion SP) b. Is larger than the channel length a. Therefore, the hump characteristic can be suppressed as in the case of FIG.

  FIG. 8 is a plan view showing still another example of the thin film transistor TR according to the second embodiment. The width of the first portion of the semiconductor film SF viewed in the direction of the electric field E is minimal between the first side and the second side. More specifically, the width at the center between the first side and the second side is smaller than the width of the first side and the width of the second side. In such a thin film transistor TR, the portion where the current flows most easily in the first portion is the portion having the smallest width, that is, the portion indicated by the channel width W in FIG. Also in this case, at least a part of the side portion SP does not exist in the portion where the current flows most easily, and the path b from the first side to the second side of the outer periphery of the first portion is the first side. And the channel length a which is the interval between the second sides. Therefore, the hump characteristic can be suppressed as in the case of FIG.

  FIG. 9 is a plan view showing still another example of the thin film transistor TR according to the second embodiment. Each of the two lines connecting the first side and the second side of the outer periphery of the first portion in a plan view is a step-like line. That is, each of these lines extends from the first side in the direction of the electric field E to the center of the first side and the second side, from there to some direction in the direction perpendicular to the electric field, and further to the second side. It extends in the direction of the electric field E. In such a thin film transistor TR, the portion of the first portion where the current is most likely to flow is on the second side along the direction of the electric field E from the intersection of the left end of the first portion and the first side in FIG. The portion between the line going to the first line and the line extending from the intersection of the right edge of the first portion and the second side along the direction of the electric field E and toward the first side, that is, the portion indicated by the channel width W in FIG. . Also in this case, at least a part of the side portion SP does not exist in the portion where the current flows most easily, and the path b from the first side to the second side of the outer periphery of the first portion is the first side. And the channel length a which is the interval between the second sides. Therefore, the hump characteristic can be suppressed as in the case of FIG.

[Third Embodiment]
The third embodiment is different from the first embodiment in that the gate electrode GE has a shape and a semiconductor block SB. Below, it demonstrates centering around difference with 1st Embodiment.

  FIG. 10 is a plan view showing an example of a thin film transistor TR according to the third embodiment. In plan view, a portion of the semiconductor film SF that extends in a strip shape so as to connect the source electrode SE and the drain electrode DE intersects the gate electrode GE at a right angle. Further, the slit hole SL does not exist in a portion where the gate electrode GE and the semiconductor film SF overlap in plan view.

  Under the gate electrode GE and in the same layer as the layer of the semiconductor film SF, the semiconductor blocks SB are arranged on the right side and the left side of the first part with a certain distance e. In the example of FIG. 10, the semiconductor blocks SB are rectangular in plan view, and the entire semiconductor block SB overlaps the gate electrode GE. Also, in plan view, one side of the semiconductor block SB is parallel to the outer peripheral side of the adjacent semiconductor film SF (especially the first portion).

  11 is a cross-sectional view taken along the line XI-XI of the thin film transistor TR shown in FIG. The semiconductor block SB is a projecting structure. The gate insulating film GI is easily volumed between the semiconductor block SB and the semiconductor film SF when stacked. Accordingly, the film thickness c on the end of the semiconductor film SF on the semiconductor block SB side is thicker than the film thickness d of the gate insulating film GI on the main body portion MP of the semiconductor film SF. Therefore, the distance between the side portion SP and the gate electrode GE is longer than that of the main body portion MP, the electric field applied from the gate electrode GE to the side portion SP is reduced, and the side portion SP is difficult to turn on. As a result, the on-resistance of the side portion SP becomes larger than that of the main body portion MP. Therefore, the hump characteristics of the thin film transistor TR can be suppressed. Note that the taper at the end of the side portion SP and the taper at the end of the semiconductor block SB may be connected, that is, the interval e = 0.

  FIG. 12 is a plan view showing another example of the thin film transistor TR according to the third embodiment. As shown in FIG. 12, the semiconductor block SB may have a portion that intersects the first side and the second side in a plan view and does not overlap with the gate electrode GE in a plan view. In this case, the interval e is preferably larger than zero. This is because if the taper at the end of the side portion SP and the taper at the end of the semiconductor block SB are connected, the semiconductor block SB functions as a channel, and the hump characteristics due to the side portion SP of the semiconductor block SB become a problem.

  Although the embodiment of the present invention has been described so far, the present invention is not limited to the above-described configuration. For example, the present invention may be applied to a liquid crystal display device or an organic EL display device of another method such as a TN method or a VA method instead of the IPS method. This is because the above-described thin film transistor TR can also be used for these. Moreover, you may combine the structure shown in 1st Embodiment, 2nd Embodiment, and 3rd Embodiment.

  CL common line, CT common electrode, DL video signal line, GL gate signal line, PT pixel electrode, TR thin film transistor, XDV video signal line driving circuit, YDV gate scanning circuit, DE drain electrode, GE gate electrode, GI gate insulating film, MP body part, SB semiconductor block, SE source electrode, SF semiconductor film, SL slit hole, SP side part, WL wiring, EM body MOS component, ES side MOS component, h hump.

Claims (3)

A gate electrode including a first side and a second side opposite to each other in a plan view, and
A source electrode;
A drain electrode;
A first portion provided below the gate electrode and overlapping the gate electrode in plan view, and a second portion connected to the first portion below the first side and connected to the source electrode And a third portion connected to the first portion and connected to the drain electrode below the second side, and a semiconductor film,
An insulating film provided between the gate electrode and the semiconductor film,
A portion of the outer periphery of the semiconductor film that overlaps the gate electrode in a plan view connects the first side and the second side and extends from one of the first side and the second side to the other side. rather than a line segment extending in the electric field direction of going,
In plan view, the length of the line connecting the first side and the second side of the outer periphery of the first part is longer than the distance between the first side and the second side. ,
A line connecting the first side and the second side of the outer periphery of the first portion in a plan view is in the first direction and the first direction in which the drain electrode or the source electrode extends. Extending in a direction different from the orthogonal second direction,
The distance between the lines connecting the first side and the second side of the outer periphery of the first portion in plan view is equal.
A display device characterized by that. A gate electrode including a first side and a second side opposite to each other in a plan view, and
A source electrode;
A drain electrode;
A first portion provided below the gate electrode and overlapping the gate electrode in plan view, and a second portion connected to the first portion below the first side and connected to the source electrode And a third portion connected to the first portion and connected to the drain electrode below the second side, and a semiconductor film,
An insulating film provided between the gate electrode and the semiconductor film,
A portion of the outer periphery of the semiconductor film that overlaps the gate electrode in a plan view connects the first side and the second side and extends from one of the first side and the second side to the other side. Not a line that extends in the direction of the electric field
The length of the path of two lines connecting the first side and the second side of the outer periphery of the first portion in plan view is the distance between the first side and the second side. Longer,
Each of the two lines connecting the first side and the second side of the outer periphery of the first portion in plan view is a third direction from the first side to the second side. A first line segment extending in a direction of a predetermined length and a second line segment bent from an end of the first line segment and extending in a fourth direction different from the first line segment,
A display device characterized by that. The width in the direction perpendicular to the direction of the electric field of the first portion is minimized at a portion where the two lines extend in the fourth direction.
The display device according to claim 2.

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