JP2010205850A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device with a thin-film transistor which suppresses a cost increase by a production process, while securing a necessary on current and simultaneously suppressing an off current. <P>SOLUTION: The display device having the thin-film transistor TFT includes: a gate electrode GT; a drain electrode DT and a source electrode ST stacked on the upper side of the gate electrode GT; a semiconductor film S stacked on the upper side of the gate electrode GT and on the lower side of the drain electrode DT and the source electrode ST; and an insulating film ES which comes into contact with the upper side of the semiconductor film S, and is formed in a tapering shape to expose a first end DR on the drain electrode DT side and a second end SR on the source electrode ST side in the semiconductor film S. The drain electrode DT is arranged so as to coat the first end DR from the upper side astride a part of the insulating film ES, the source electrode ST is arranged so as to coat the second end SR from the upper side astride a part of the insulating film ES, and the semiconductor film S and the gate electrode GT are overlapped in a planar manner in a region apart at predetermined intervals from the first end DR. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device that performs display control of a pixel using a thin film transistor (TFT).

  Conventionally, it has been studied to improve performance such as electrical characteristics of a thin film transistor formed using amorphous silicon (a-Si). Here, in order to obtain desired electrical characteristics, for example, the manufacturing process designed by maintaining the structure of a thin film transistor using amorphous silicon as much as possible is utilized, and the crystal grain size of silicon is increased. Thus, studies have been made with a direction of improving electron mobility and the like.

  Patent Document 1 is an example of such a conventional technique, and FIG. 11 is a diagram showing a thin film transistor having a bottom gate structure similar to that described in Patent Document 1. In Patent Document 1, as shown in the figure, polycrystalline silicon (p-Si) is laminated below amorphous silicon for reasons of manufacturing a display device.

JP-A-5-55570

  When attention is paid to the thin film transistor shown in FIG. 11, the on-current flows through the polycrystalline silicon layer SP having a high electron mobility, but the off-current becomes a problem. This is because when a negative voltage is applied to the gate electrode GT, holes are induced in the polycrystalline silicon layer SP, and there is no potential barrier between the drain electrode DT, the source electrode ST, and the polycrystalline silicon layer SP. This is because the current due to the holes flows directly to the drain electrode DT and the source electrode ST.

  Moreover, FIG. 12 is a figure which shows the structure which this inventor examined. In the thin film transistor shown in the figure, a portion where the drain electrode DT and the source electrode ST and the semiconductor film S are connected is widely formed to reduce the contact resistance. Here, FIG. 6A is a graph showing characteristics of gate voltage and drain current in the thin film transistor shown in FIG. In the graph of the figure, it is shown that the on-state current is sufficiently secured and the off-state current is suppressed at the drain voltage of 1V, and the off-state current cannot be suppressed and the leakage current flows at the drain voltage of 10V. It is shown. Therefore, in the case of using the thin film transistor shown in FIG. 12, it is necessary to provide a restriction such that the drain voltage is set to 5 V or less, for example, and it becomes a problem to suppress the off current when the drain voltage is set to a higher voltage.

  An object of the present invention is to propose a display device including a thin film transistor in which off current is suppressed while securing a necessary on current while suppressing an increase in cost due to a manufacturing process.

  In order to solve the above problems, a display device according to the present invention includes a gate electrode laminated on a transparent substrate, and a drain electrode laminated on the gate electrode and supplied with a signal from a connected signal line. A source electrode stacked on the gate electrode; and an upper side of the gate electrode and on the drain electrode and the source electrode, and the drain electrode is generated by the electric field generated by the gate electrode. And a semiconductor film for controlling a current between the source electrodes, and a tapered shape in contact with an upper side of the semiconductor film, and a first end portion on the drain electrode side of the semiconductor film and a first electrode on the source electrode side. An insulating film that exposes two ends, and the drain electrode is disposed so as to cover the first end from above over a part of the insulating film, and the source electrode The semiconductor film and the gate electrode are arranged so as to cover the second end portion from the upper side across a part of the semiconductor substrate, and the semiconductor film and the gate electrode overlap in a plane in a region separated from the first end portion by a predetermined distance. A thin film transistor characterized by

  In one embodiment of the display device according to the present invention, the gate electrode is disposed so that the center of the gate electrode is positioned on the second end side with respect to the center of the semiconductor film. Features.

  In the display device according to the aspect of the invention, the semiconductor film and the gate electrode may include at least a part of the second end portion from a region sandwiched between the first end portion and the second end portion. It is characterized by overlapping two-dimensionally over the two.

  In the display device according to the aspect of the invention, the gate electrode may protrude from a region overlapping the second end portion in a plan view to a side opposite to the side where the first end portion is provided. It is extended, and it is characterized by the above-mentioned.

  In the display device according to the aspect of the invention, the semiconductor film and the gate electrode may be configured such that the gate electrode and the second end portion overlap in a planar manner, It overlaps planarly in a part of area | region pinched | interposed with a 2nd edge part, It is characterized by the above-mentioned.

  In the display device according to the aspect of the invention, the semiconductor film and the gate electrode may overlap in a plane in a region separated from the first end and the second end by the predetermined distance. It is characterized by.

  In one embodiment of the display device according to the present invention, the gate electrode is arranged so that the drain electrode overlaps in plan with a portion straddling the insulating film.

  In one embodiment of the display device according to the present invention, the semiconductor film is formed of microcrystalline silicon.

  In one embodiment of the display device according to the present invention, a region where the semiconductor film and the gate electrode overlap in a plane is separated from the first end by 0.5 μm or more.

  In one embodiment of the display device according to the present invention, an ohmic contact layer is formed between the first end and the drain electrode, and between the second end and the source electrode so as to make an ohmic contact therebetween. It is characterized by that.

  In the display device according to the aspect of the invention, the drain electrode is connected to a video signal line, the source electrode is connected to a pixel electrode, the gate electrode is connected to a scanning signal line, and the thin film transistor Is formed in a pixel region in which the video signal line and the scanning signal line are laid in a grid pattern.

  In one embodiment of the display device according to the present invention, the thin film transistor is formed in the periphery of a pixel region, and when the thin film transistor is turned off, a potential difference between the drain electrode and the gate electrode is And the potential difference between the gate electrodes becomes higher.

  According to the present invention, it is possible to suppress the off current while securing the necessary on current of the thin film transistor in the display device.

It is an equivalent circuit diagram of a TFT substrate constituting an IPS liquid crystal display device. It is an enlarged plan view which shows the mode of the pixel of the TFT substrate which concerns on 1st Embodiment. It is sectional drawing in the III-III line of FIG. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a figure which shows a mode that the thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a top view which shows a mode that thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a top view which shows a mode that thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. It is a top view which shows a mode that thin-film transistor TFT in the display apparatus which concerns on 1st Embodiment is manufactured. 13 is a graph showing characteristics of gate voltage and drain current in the thin film transistor of FIG. 12. 4 is a graph showing characteristics of gate voltage and drain current in the thin film transistor of FIG. 3. It is a figure which shows sectional drawing of the thin-film transistor concerning 2nd Embodiment. It is a figure which shows sectional drawing of the thin-film transistor concerning 3rd Embodiment. It is a figure which shows an example of the equivalent circuit schematic of the TFT substrate which comprises the display apparatus of a VA system and a TN system. It is an enlarged plan view showing an example of a pixel formed on a VA type and TN type TFT substrate. It is a figure which shows the thin-film transistor by the same bottom gate structure as what is described in patent document 1. FIG. It is a figure which shows the structure which inventors of this application examined.

[First embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The display device according to the present embodiment is an IPS (In-Plane Switching) liquid crystal display device, and includes a TFT substrate on which scanning signal lines, video signal lines, thin film transistors, pixel electrodes, and counter electrodes are arranged, and It includes a filter substrate facing the TFT substrate and provided with a color filter, a liquid crystal material sealed in a region sandwiched between both substrates, and a backlight that provides light to the TFT substrate and the filter substrate. The In this TFT substrate, a thin film transistor is disposed on a transparent substrate formed of glass or the like.

  FIG. 1 is an equivalent circuit diagram of the TFT substrate SUB of the liquid crystal display device. FIG. 2 is an enlarged plan view showing an enlarged state of one pixel of the TFT substrate SUB.

  In these drawings, on the TFT substrate SUB, a large number of scanning signal lines GL extend in the horizontal direction in the drawing at equal intervals, and a large number of video signal lines DL extend in the vertical direction in the drawing at equal intervals. ing. Each of the pixels arranged in a matrix is defined by the scanning signal lines GL and the video signal lines DL. Further, the reference signal line CL extends in the horizontal direction in the drawing in parallel with each scanning signal line GL. A scanning signal line driving circuit GDR that provides a scanning signal to the scanning signal line GL and a video signal line driving circuit that provides a video signal to the video signal line DL are arranged around a region (pixel region) where pixels are partitioned in a matrix. DDR is arranged.

  The pixel region is formed by dividing the scanning signal line GL and the video signal line DL in a grid pattern. As shown in FIG. 2, a thin film transistor TFT having a MIS (Metal-Insulator-Semiconductor) structure is formed at the corner of each pixel, the gate electrode GT is connected to the scanning signal line GL, and the drain electrode DT is It is connected to the video signal line DL. Each pixel is provided with a pair of pixel electrodes PX and a counter electrode CT. The pixel electrode PX is connected to the source electrode ST of the thin film transistor TFT, and the counter electrode CT is connected to the reference signal line CL.

  In the above circuit configuration, the reference voltage is applied to the counter electrode CT of each pixel via the reference signal line CL, and the scanning signal line GL is sequentially provided with the scanning signal from the scanning signal line driving circuit GDR. A pixel row is selected. Then, at the timing of selecting the pixel row, the video signal line driving circuit DDR supplies the video signal to each video signal line DL, whereby the voltage of the video signal is applied to the pixel electrode PX of each pixel. Thereby, horizontal electrolysis with an intensity corresponding to the voltage of the video signal is generated between the pixel electrode PX and the counter electrode CT, and the orientation of the liquid crystal molecules is determined according to the intensity of the horizontal electrolysis.

  Here, as shown in FIG. 2, an insulating film ES is formed above the gate electrode GT connected to the scanning signal line GL, and the drain electrode DT and the source electrode ST straddle the insulating film ES. , Is formed so as to overlap a part thereof.

  3 is a cross-sectional view taken along line III-III shown in FIG. 2, and is a cross section perpendicular to the direction in which the video signal line DL extends. As shown in the figure, in the thin film transistor TFT on the TFT substrate SUB, the semiconductor film S is disposed above the gate electrode GT via the gate insulating film GI1. On the upper side of the semiconductor film S, the insulating film ES is disposed in contact with the semiconductor film S, and both ends of the semiconductor film S are exposed from the insulating film ES. Further, the drain electrode DT and the source electrode ST are disposed on both sides of the insulating film ES. The first end DR exposed from the insulating film ES in the semiconductor film S is electrically connected to the drain electrode DT via the ohmic contact layer DS, and the second end SR is similarly sourced via the ohmic contact layer DS. It is electrically connected to the electrode ST. The ohmic contact layer DS is a layer formed by depositing amorphous silicon while impurities are added, and the first end DR and the second end SR have an ohmic contact as shown in FIG. Layer DS is coated. The ohmic contact refers to a contact whose voltage-current characteristics are linear in an electrical contact portion such as a wiring layer and a semiconductor layer.

  In particular, in this embodiment, the region of the semiconductor film S (first end DR) exposed from the insulating film ES on the drain electrode DT side and the gate electrode GT are prevented from overlapping in plan view. A region where the gate electrode GT and the semiconductor film S overlap is located at a predetermined interval from the first end DR. Further, the insulating film ES is disposed at a position that is substantially the center of the semiconductor film S, and in the region of the semiconductor film S that is covered by the insulating film ES (the region sandwiched between the first end DR and the second end SR), A channel region for controlling the current between the drain electrode DT and the source electrode ST is formed by the electric field generated by the gate electrode GT. The gate electrode GT overlaps in a planar manner in at least a part of a region sandwiched between the first end DR and the second end SR of the semiconductor film S. Then, the insulating film ES, the semiconductor film S, and the gate electrode GT are arranged so as to avoid the gate electrode GT from overlapping the first end portion DR in a planar manner. Since the first end DR is arranged in a plane away from the gate electrode GT, an electric field between the gate electrode GT and the drain electrode DT that is likely to have a larger potential difference than that between the gate electrode GT and the source electrode ST when the switch is turned off. The concentration is relaxed and the leakage current is suppressed (FIG. 6B). The distance D between the first end DR and the region of the semiconductor film S that overlaps the gate electrode GT in a plane is preferably 0.5 μm or more. When the distance D is increased, the on-current decreases. Therefore, the length is about several μm.

  Further, in the thin film transistor TFT according to the present embodiment, the gate electrode GT and the semiconductor film S are arranged such that the center of the gate electrode GT is positioned on the second end SR side (source electrode ST side) with respect to the center of the semiconductor film S. Each is arranged. As shown in FIG. 3, the gate electrode GT has a planar surface extending from the semiconductor film S across a region sandwiched between the first end DR and the second end SR and a partial region in the second end SR. Overlapping. Since the gate electrode GT and the partial region of the second end SR overlap in a planar manner, a decrease in on-current is suppressed.

  Hereinafter, the reason why the current (off-leakage current) flowing when the switch is turned off can be reduced by the structure of the thin film transistor TFT in the present embodiment will be described in detail. For the data signal applied to the drain electrode DT, in order to extend the life of the liquid crystal molecules, for example, a frame inversion driving method is used in which the polarity of the voltage applied to the liquid crystal molecules is inverted every frame. Therefore, when the drain electrode DT is higher than the reference potential (hereinafter, drain electrode high potential state), and when the drain electrode DT is lower than the reference potential (hereinafter drain electrode low potential state). Exists.

  When attention is paid to the source electrode ST, when the thin film transistor TFT is turned on, the capacitance is accumulated in the pixel electrode PX through the source electrode ST. The capacitance accumulated in the pixel electrode PX is retained even when the thin film transistor TFT is turned off, and the capacitance potential associated with the pixel electrode PX is applied to the source electrode ST. The source electrode ST in a state where the capacitance is accumulated in the pixel electrode PX in the drain electrode high potential state (hereinafter referred to as the source electrode high potential state) causes a voltage drop through the semiconductor film S and the like, and charges are accumulated in the pixel electrode PX. Therefore, the potential of the drain electrode DT is lower than that of the drain electrode DT in the high potential state. Further, the source electrode ST in the state where the capacitance is accumulated in the pixel electrode PX in the drain electrode low potential state (hereinafter, the source electrode low potential state) is more than the potential of the drain electrode DT in the drain electrode low potential state due to the voltage drop. Although it becomes higher, the potential becomes lower than the reference potential.

  In the present embodiment, a negative potential is applied to the gate electrode GT when the thin film transistor TFT is off, and a positive potential is applied to the drain electrode DT and the source electrode ST in each of the above states. In addition, among the above four states, the potential of the drain electrode DT in the high potential state of the drain electrode becomes the highest, and at this time, the potential difference from the gate electrode GT at the time of OFF becomes maximum and the off-leakage current is generated most. It becomes easy. As described above, by avoiding the planar overlap between the gate electrode GT and the first end DR, the electric field concentration is reduced and the off-leakage current is suppressed.

  As shown in FIG. 3, since the second end SR and the gate electrode GT overlap in a plane, electric field concentration is likely to occur between them in the high potential state of the source electrode. The potential difference is smaller than that of the drain electrode DT in the high potential state. Further, even if a leak current occurs between the source electrode ST and the gate electrode GT, the electric potential accumulated in the pixel electrode PX flows out to lower the potential of the source electrode ST, so that the off-leak current is limited. It will be something.

  The semiconductor film S is formed of amorphous silicon by a CVD method or the like, and crystallized into crystalline silicon such as microcrystalline silicon (μc-Si) by laser annealing or the like. In general, as the crystallinity of silicon in the semiconductor film S improves, the crystal size increases, so that the electron mobility improves. However, the required process temperature becomes high, and the process cost increases. The semiconductor film S in this embodiment is microcrystalline silicon having a crystal grain size in the range of about 10 nm to about 100 nm, but may be polycrystalline silicon. The crystal grain size in the semiconductor film S is confirmed by reflected electron diffraction, Raman spectroscopy, or the like.

On the upper side of the semiconductor film S, an insulating film ES is formed of, for example, silicon dioxide (SiO ₂ ) in contact with the semiconductor film S. This insulating film plays a role of preventing the etching from reaching the portion of the semiconductor film S where the channel region is formed when the drain electrode DT or the like is etched and processed. Further, since the insulating film ES is processed into a tapered shape as shown in FIG. 3 by wet etching as will be described later, the insulating film ES is formed at a position substantially at the center of the semiconductor film S, and the first end DR and the first The two end portions SR are formed to be substantially symmetrically exposed from the insulating film ES. Note that N-type impurities such as phosphorus (P) may be implanted into the first end DR and the second end SR using the insulating film ES as a mask. In this way, a depletion layer is formed at the boundary between the first end DR and the second end SR and the region of the semiconductor film S covered with the insulating film ES from above when no gate voltage is applied. It will be.

  The ohmic contact layer DS and the drain electrode DT are provided so as to extend over a part of the insulating film ES having a trapezoidal cross section and the first end DR. A source electrode ST is also provided in the same manner. The drain electrode DT and the source electrode ST are mainly formed of a metal such as aluminum and are formed so as to cover the upper side of the ohmic contact layer DS. As shown in FIG. 3 and the like, if the gate electrode GT overlaps the semiconductor film S at a predetermined interval from the first end DR, the portion where the drain electrode DT overlaps the insulating film ES in a plane. May be duplicated. Note that an amorphous silicon layer may be formed in the layer between the ohmic contact layer DS and the first end DR and the second end SR in the present embodiment. In this case, the amorphous silicon layer is first formed with a predetermined thickness, and then an impurity such as phosphorus is added while the amorphous silicon film is continuously formed, so that the ohmic contact layer DS is formed. It is formed. The amorphous silicon layer provided in the lower layer functions as a resistor between the semiconductor film S, the drain electrode DT, and the source electrode ST, and alleviates electric field concentration that may occur when the thin film transistor TFT is turned off.

  In the above, the thin film transistor TFT on the TFT substrate SUB in the present embodiment has been described. Hereinafter, a method for manufacturing the thin film transistor TFT will be described with reference to FIGS. 4A to 4J and FIGS. 5A to 5C.

  First, a contamination prevention film GN is formed on a transparent substrate GA such as a glass substrate to form a gate electrode GT (FIG. 4A). As the contamination prevention film GN, silicon nitride (SiN) is formed by, for example, a CVD method. Further, the gate electrode GT is formed of a conductive metal such as molybdenum, for example, and is processed through a known lithography process and etching process as shown in FIG.

  Next, the gate insulating film GI1 is formed so as to cover the gate electrode GT, and the semiconductor film S is formed on the gate insulating film GI1 (FIG. 4B). The gate insulating film GI1 is, for example, silicon dioxide, and is formed by a CVD method. The semiconductor film S is first crystallized into microcrystalline silicon by forming amorphous silicon by a CVD method and performing heat treatment. At this time, it may be crystallized into polycrystalline silicon using an excimer laser or RTA (Rapid Thermal Anneal) method. Thereafter, silicon dioxide is deposited on the upper side of the crystallized semiconductor film S by the CVD method, and the insulating film ES is stacked (FIG. 4C). Then, a resist pattern RP is formed on the insulating film ES through a known lithography process (FIG. 4D). In this known lithography process, first, a photoresist is applied on the insulating film ES, and ultraviolet rays or the like are irradiated onto the photoresist through a photomask in which a predetermined pattern is formed. When the pattern corresponding to the pattern on the photomask is transferred onto the photoresist, a portion irradiated with the excimer laser and a portion not irradiated are generated, and a chemical reaction occurs in the irradiated portion of the photoresist. Then, the development process removes the portion where the chemical reaction in the photoresist has occurred or the portion where the chemical reaction has not occurred to form the resist pattern RP. The resist pattern RP is formed in a shape for processing the semiconductor film S.

  Then, using the resist pattern RP as a mask, wet etching is performed using hydrofluoric acid to process the laminated insulating film ES (FIG. 4E). At this time, the insulating film ES is side-etched so that the insulating film ES is formed inside the resist pattern RP. After the insulating film ES is processed by wet etching, the semiconductor film S is processed into the same shape as the resist pattern RP by dry etching according to the resist pattern RP (FIG. 4F). The insulating film ES is formed by being eroded substantially uniformly from the outer extension of the resist pattern RP to the inside thereof. On the other hand, the semiconductor film S is formed in substantially the same shape as the resist pattern RP. Therefore, since the insulating film ES is side-etched almost uniformly from both sides of the resist pattern RP, the insulating film ES is formed in a region centered at a position that is substantially the center of the semiconductor film S.

  Thereafter, the resist pattern RP is removed by ashing using oxygen plasma or the like (FIG. 4G). Here, FIG. 5A is a top view showing how each layer in FIG. 4G is processed. As shown in FIG. 5A, the region NR of the semiconductor film S exposed from the insulating film ES is formed so as to surround the insulating film ES.

  From the state of FIG. 4G, the ohmic contact layer DS and the metal film for forming the drain electrode DT and the source electrode ST are formed (FIG. 4H). First, the ohmic contact layer DS is formed by depositing amorphous silicon by PECVD while adding impurities such as phosphorus at a high concentration. For the drain electrode DT and the source electrode ST, a barrier metal layer MB, a main wiring layer MM, and a cap metal layer MC are formed by sputtering. At this time, the barrier metal layer MB and the cap metal layer MC are formed of a conductive metal thin film made of a high melting point metal such as titanium, tungsten, chromium or molybdenum. The main wiring layer MM is formed of aluminum or an alloy containing aluminum. Note that aluminum or an aluminum-based alloy has a high-quality ohmic contact with amorphous silicon formed with impurities such as phosphorus.

  Then, the cap metal layer MC, the main wiring layer MM, the barrier metal layer MB, and the ohmic contact layer DS are processed into the shape of the drain electrode DT and the source electrode ST by a known lithography process and etching process (FIG. 4I). ). Here, FIG. 5B and FIG. 5C are top views showing how each layer in FIG. 4I is processed. First, a resist pattern for forming the drain electrode DT and the source electrode ST is formed on the cap metal layer MC, and the cap metal layer MC, the main wiring layer MM, and the barrier metal layer MB are wet-etched according to the resist pattern. The drain electrode DT and the source electrode ST are formed. Further, the ohmic contact layer DS is dry-etched using the drain electrode DT and the source electrode ST whose shape has been processed as a mask, and processed into the same shape as the drain electrode DT and the source electrode ST (FIG. 5B). As a result, the ohmic contact layer DS (not shown in FIG. 5B) is processed in the same pattern as the drain electrode DT and the like, and is formed so as to be covered therewith. Further, the dry etching for processing the ohmic contact layer DS is continued as it is, the region NR is processed, and the first end DR and the second end SR are formed (FIG. 5C). At this time, the insulating film ES serves as an etching stopper that prevents the semiconductor film S from being dry-etched. Finally, a passivation film PA is formed on the entire structure with silicon nitride by plasma CVD (FIG. 4J). The passivation film PA protects the thin film transistor TFT formed as described above.

  In this embodiment, the polarity of the voltage related to the liquid crystal molecules is inverted for each frame by the frame inversion driving circuit. However, the polarity may be inverted by line inversion driving or dot inversion driving.

  In this embodiment, the thin film transistor TFT is a pixel transistor formed in a pixel as shown in FIG. 2, but is formed around a pixel region such as a video signal line driving circuit DDR or a scanning signal line driving circuit GDR. It may be a thin film transistor in a circuit (peripheral circuit). In the case of the thin film transistor in the peripheral circuit, similarly to the pixel transistor, a signal having a potential that is alternately inverted with respect to a predetermined potential may be provided to the element connected to the source electrode ST from the drain electrode DT. In addition, unlike a pixel transistor, a signal based on a potential that does not invert alternately may be provided to an element connected to the source electrode ST from the drain electrode DT. Even in the case of a thin film transistor in a peripheral circuit, the gate voltage at the time of switch-off is set so that the potential difference generated between the electrodes at the time of switch-off is larger between the drain electrode DT and the gate electrode GT than between the source electrode ST and the gate electrode GT. The potential of the signal provided from the drain electrode DT is set.

[Second Embodiment]
In the first embodiment, as shown in FIGS. 2 and 3, the gate electrode GT includes a part of the region sandwiched between the first end DR and the second end SR and one of the second ends SR. It overlaps planarly in the region of the part. However, in the second embodiment, the gate electrode GT is overlapped with a part of the region sandwiched between the first end DR and the second end SR, avoiding planar overlap with the second end SR. Since the other points are substantially the same, the description thereof is omitted. In the second embodiment, as shown in FIG. 7, the gate electrode GT is formed symmetrically with respect to the semiconductor film S at a position spaced apart from the first end DR and the second end SR at equal intervals. However, the gate electrode GT may be disposed asymmetrically toward the second end SR side. Since the gate electrode GT does not overlap with the second end SR, the off-leakage current is further suppressed.

[Third embodiment]
In the first embodiment, as shown in FIGS. 2 and 3, the gate electrode GT includes a part of the region sandwiched between the first end DR and the second end SR and one of the second ends SR. It overlaps planarly in the region of the part. However, in the third embodiment, as shown in FIG. 8, the gate electrode GT overlaps in plan with the part of the region sandwiched between the first end DR and the second end SR at the second end SR. In addition, it extends from the second end SR so as to protrude to the side opposite to the side where the first end DR is provided. Since the gate electrode GT is further extended to the source electrode ST side beyond the region overlapping the second end SR in plan view, the decrease in on-current is further suppressed.

  In the liquid crystal display device according to each of the embodiments described above, the liquid crystal driving method is described as the IPS method. However, the present invention is not limited to the VA (Vertically Aligned) method or the TN (Twisted Nematic) method. It may be a drive system of the system. FIG. 10 is a diagram showing an equivalent circuit of a TFT substrate SUB constituting a display device of VA mode and TN mode, and FIG. 11 is an enlarged plan view showing one pixel in the TFT substrate SUB of the display device of these types. It is. In the case of the VA method and the TN method, instead of providing the counter electrode CT and the reference signal line CL on the TFT substrate SUB, the counter electrode CT is provided on the counter substrate provided with the color filter facing the TFT substrate SUB. It has been.

  In each of the above embodiments, the display device according to the present invention is described as a liquid crystal display device. However, the present invention is not limited to this, and for example, other display devices such as an organic EL (Electro Luminescence) element. Is still not applicable. Since the organic EL display device does not require a backlight, it is not necessary to shield the semiconductor film S from the backlight in the pixel transistor provided in the pixel region. Therefore, the configurations of the above embodiments are particularly suitable.

  The display device according to each embodiment of the present invention described above is not limited by each of the above embodiments, and may be implemented in different forms within the scope of the technical idea.

  SUB TFT substrate, GL scanning signal line, CL reference signal line, PX pixel electrode, CT counter electrode, TFT thin film transistor, DT drain electrode, ST source electrode, GT gate electrode, ES insulating film, DS ohmic contact layer, S semiconductor film, GA transparent substrate, GN contamination prevention film, GI1 gate insulating film, DR first end, SR second end, MB barrier metal layer, MM main wiring layer, MC cap metal layer, RP resist pattern, NR region, PA passivation Film, SA amorphous silicon layer, SP polycrystalline silicon layer, GDR scanning signal line driving circuit, DDR video signal line driving circuit.

Claims (12)

A gate electrode laminated on the upper side of the transparent substrate;
A drain electrode stacked on the gate electrode and supplied with a signal from a connected signal line;
A source electrode laminated on the gate electrode;
A semiconductor film that is over the gate electrode and under the drain electrode and the source electrode, and controls a current between the drain electrode and the source electrode by an electric field generated by the gate electrode;
An insulating film formed in a tapered shape in contact with an upper side of the semiconductor film and exposing a first end portion on the drain electrode side and a second end portion on the source electrode side of the semiconductor film;
The drain electrode is arranged so as to cover the first end portion from above over a part of the insulating film,
The source electrode is disposed so as to cover the second end portion from the upper side across a part of the insulating film,
The semiconductor film and the gate electrode overlap in a plane in a region spaced a predetermined distance from the first end,
A display device having a thin film transistor. The display device according to claim 1,
The gate electrode is disposed such that the center of the gate electrode is located on the second end side with respect to the center of the semiconductor film.
A display device characterized by that. The display device according to claim 2,
The semiconductor film and the gate electrode overlap in a plane over a region sandwiched between the first end and the second end and at least a part of the second end.
A display device characterized by that. The display device according to claim 3,
The gate electrode extends from a region overlapping the second end portion in a plan view so as to protrude to a side opposite to the side where the first end portion is provided.
A display device characterized by that. The display device according to claim 1,
In the semiconductor film and the gate electrode, in a part of a region sandwiched between the first end and the second end, avoiding the planar overlap between the gate electrode and the second end. Overlapping in plane,
A display device characterized by that. The display device according to claim 5,
The semiconductor film and the gate electrode overlap in a planar manner in a region spaced from the first end and the second end by the predetermined distance.
A display device characterized by that. The display device according to claim 1,
The gate electrode is disposed so that the drain electrode overlaps in a plane with a portion straddling the insulating film,
A display device characterized by that. The display device according to claim 1,
The semiconductor film is formed of microcrystalline silicon;
A display device characterized by that. The display device according to claim 1,
The region where the semiconductor film and the gate electrode overlap in plan is separated from the first end by 0.5 μm or more.
A display device characterized by that. The display device according to claim 1,
Between the first end and the drain electrode, and between the second end and the source electrode, an ohmic contact layer is formed for ohmic contact therebetween.
A display device characterized by that. The display device according to claim 1,
The drain electrode is connected to a video signal line;
The source electrode is connected to a pixel electrode;
The gate electrode is connected to a scanning signal line;
The thin film transistor is formed in a pixel region in which the video signal line and the scanning signal line are laid in a grid pattern.
A display device characterized by that. The display device according to claim 1,
The thin film transistor is formed around a pixel region,
When the thin film transistor is turned off, a potential difference between the drain electrode and the gate electrode is higher than a potential difference between the source electrode and the gate electrode.
A display device characterized by that.

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