JP6049304B2 - Solid-state imaging device and imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device in which a plurality of pixels having photoelectric conversion units are arranged, and an imaging device having the solid-state imaging device.

  Imaging devices such as digital still cameras use solid-state imaging devices that convert light into electrical signals and output pixel signals. As one type of solid-state imaging device, there is a CMOS-type solid-state imaging device (hereinafter referred to as “CMOS image sensor”) that takes advantage of the features that can be manufactured in the same process as a CMOS (including MOS) integrated circuit.

  Conventionally, a general CMOS image sensor employs a rolling shutter system that sequentially reads out signal charges generated by photoelectric conversion units of pixels arranged in a two-dimensional matrix for each row. In this method, since the exposure timing in the photoelectric conversion unit of each pixel is determined by the start and end of reading of the signal charge, the exposure timing is different for each row. For this reason, when a fast-moving subject is imaged using such a CMOS image sensor, there is a problem that the subject is distorted in the captured image. Therefore, in recent years, a CMOS image sensor with a signal storage unit in the pixel has been proposed in order to realize a simultaneous imaging function (global shutter function) that realizes the same time accumulation of signal charges in each pixel of the CMOS image sensor. (For example, refer to Patent Document 1).

JP 2010-219339

  However, an image taken using a CMOS image sensor having a signal storage unit in a pixel tends to be inferior in quality to an image taken using a conventional rolling shutter system. This is because a variation in signal charge leakage that occurs during a signal holding period from when the signal charge is transferred to the signal storage unit until the pixel signal based on the signal charge is read out deteriorates the image quality. As a cause of this signal charge leakage, charge leakage through a MOS transistor connected to a signal storage portion which is a capacitor for holding the signal charge can be cited.

  Hereinafter, charge leakage through a MOS transistor connected to a capacitor for holding signal charges will be described using the configuration of Patent Document 1. Here, a sample-and-hold unit (second transfer transistor Tr2 in FIG. 9 of Patent Document 1) will be described as a transistor connected to a capacitor for holding signal charges (charge storage capacitor unit 61 in FIG. 9 of Patent Document 1). To do. Hereinafter, the relationship between the voltage of the gate / back gate / drain of the sample hold unit during the signal holding period and the charge leakage will be described.

  In Patent Document 1, the signal holding period is read from the end of “accumulation exposure time” (FIG. 11 of Patent Document 1) (in FIG. 11 of Patent Document 1, reading of the first pixel row is “first pixel row reading”). The readout of the second pixel row is a period until the start of “second pixel row readout”). In this signal holding period, the gate voltage (the voltage of the second transfer pulse φTRG2 in FIGS. 9 and 11) is 0 (L level).

  In a normal NMOS, the back gate voltage is 0 because the back gate is connected to the ground. The drain voltage is the same as the voltage of the capacitor holding the signal charge. If there is no charge transferred to the capacitor that holds the signal charge, the voltage of the capacitor is the power supply voltage VDD that is a clamp voltage, and the voltage of the capacitor decreases as the transferred signal charge increases.

  Next, the relationship between the gate / back gate / drain voltage and charge leakage will be described. The charge leak is a leak of charge from the gate / back gate to the drain, and increases as the potential difference between the gate / back gate and the drain increases. Since the gate-back gate voltage is 0, the potential difference between the gate-back gate and the drain is the same as the voltage of the capacitor holding the signal charge. Accordingly, a drain voltage is high in a pixel having a smaller amount of signal charge accumulation, and more leakage occurs. Then, more variation in leak occurs in the pixel region where the amount of leak is larger, and this variation is a main cause of image quality deterioration due to the leak.

  Especially when shooting with a digital camera, etc., when shooting in a dark place or performing a short exposure to shoot a fast-moving subject, the signal charge obtained from the pixel is small, so the signal in the subsequent circuit Need to be set, that is, to set a high ISO sensitivity. As described above, in the pixel region where the signal charge accumulation amount is smaller, the potential difference between the gate / back gate and the drain is larger, and more variation in leakage occurs. When the signal amplification process is performed, the deterioration of the image quality due to this leak appears more remarkably.

  The present invention has been made in view of the above-described problems, and provides a solid-state imaging device and an imaging device capable of suppressing deterioration in image quality caused by variations in leakage of signal charges held in a signal storage unit. The purpose is to provide.

  The present invention has been made to solve the above-described problem, and has a plurality of pixels. The pixels include a photoelectric conversion unit, a signal storage unit that stores signal charges generated in the photoelectric conversion unit, and An output unit that outputs from the pixel a pixel signal based on the signal charge stored in the signal storage unit, and a clamp unit that resets the signal charge stored in the signal storage unit with a clamp voltage, The solid-state imaging device further includes a clamp voltage control unit that controls the clamp voltage based on imaging conditions.

  In the solid-state imaging device of the present invention, the pixel has a MOS transistor in which one of a source and a drain is connected to the signal storage unit, and the imaging is performed under a shooting condition in which the output range of the output unit is narrower. The clamp voltage control unit controls the clamp voltage so that a potential difference between a back gate potential of the MOS transistor and a potential of the gate of the MOS transistor in the off state and the clamp voltage is small. And

  In the solid-state imaging device according to the present invention, when the MOS transistor is an NMOS transistor and photographing is performed under a photographing condition in which the output range of the output unit is narrower, the clamp voltage control unit lowers the clamp voltage. It is characterized by that.

  Further, in the solid-state imaging device of the present invention, when the MOS transistor is a PMOS transistor and shooting is performed under a shooting condition in which the output range of the output unit is narrower, the clamp voltage control unit increases the clamp voltage. It is characterized by that.

  Further, the solid-state imaging device of the present invention is a solid-state imaging device having a plurality of pixels and electrically connecting a first substrate and a second substrate on which circuit elements constituting the pixels are arranged. The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit is disposed on the first substrate, and the signal storage unit is disposed on the second substrate.

  In addition, the solid-state imaging device of the present invention further includes a signal amplification circuit that amplifies the pixel signal output from the output unit, and a gain control unit that controls the gain of the signal amplification circuit based on imaging conditions. It is characterized by.

  In the solid-state imaging device of the present invention, when the gain control unit controls the gain of the signal amplification circuit so as to increase the amplification amount of the pixel signal, the clamp voltage control unit is configured to output the output range of the output unit. The clamp voltage is controlled so as to be narrower.

  In the solid-state imaging device according to the present invention, the pixel further includes a transfer unit that transfers the signal charge generated in the photoelectric conversion unit to the signal storage unit, and the transfer units of all the pixels collectively include the transfer unit. A signal charge is transferred.

  In addition, the present invention includes a solid-state imaging device having a plurality of pixels and a clamp voltage control unit that controls a clamp voltage based on imaging conditions. The pixels are generated by the photoelectric conversion unit and the photoelectric conversion unit. A signal storage unit for storing the signal charge, an output unit for outputting a pixel signal based on the signal charge stored in the signal storage unit from the pixel, and the clamp for the signal charge stored in the signal storage unit An imaging apparatus comprising: a clamp portion that is reset by voltage.

  According to the present invention, by controlling the clamp voltage based on the imaging conditions, it is possible to suppress image quality degradation caused by variations in leakage of signal charges held in the signal storage unit.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. 1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a pixel included in the solid-state imaging device according to the first embodiment of the present invention. 3 is a timing chart showing the operation of the solid-state imaging device according to the first embodiment of the present invention. 3 is a timing chart showing a time change of a voltage applied to a sample hold capacitor included in the solid-state imaging device according to the first embodiment of the present invention. 5 is a reference diagram illustrating gate, back gate, and drain voltages during a signal holding period of a sample and hold transistor included in the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a control system of a gain control signal transmitted to the solid-state imaging device according to the first embodiment of the present invention. FIG. FIG. 5 is a reference diagram illustrating control for each ISO sensitivity setting of a clamp voltage / gain control unit included in the solid-state imaging device according to the first embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration of a pixel included in a solid-state imaging device according to a second embodiment of the present invention. 6 is a timing chart showing the operation of the solid-state imaging device according to the second embodiment of the present invention. 6 is a timing chart showing a time change of a voltage applied to a sample hold capacitor included in the solid-state imaging device according to the second embodiment of the present invention. FIG. 7 is a reference diagram showing gate, back gate, and drain voltages during a signal holding period of a sample hold transistor included in a solid-state imaging device according to a second embodiment of the present invention. FIG. 10 is a reference diagram illustrating control for each ISO sensitivity setting of a clamp voltage / gain control unit included in the solid-state imaging device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view of a solid-state imaging device according to a third embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration of a pixel included in a solid-state imaging device according to a third embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration of a pixel included in a solid-state imaging device according to a fourth embodiment of the present invention. 10 is a timing chart showing the operation of the solid-state imaging device according to the fourth embodiment of the present invention. 9 is a timing chart showing a change with time of a voltage applied to a sample hold capacitor included in a solid-state imaging device according to a fourth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the imaging apparatus according to the present embodiment. The imaging apparatus according to the present embodiment may be an electronic device having an imaging function, and may be a digital video camera, an endoscope, or the like in addition to a digital still camera.

  The imaging device 100 according to the present embodiment includes an optical lens 1, a solid-state imaging device 2, a solid-state imaging device driving unit 3, and an image signal processing unit 4. The optical lens 1 forms an image of light incident on the subject (subject light) on the imaging surface of the solid-state imaging device 2. As a result, signal charges are accumulated in the solid-state imaging device 2 for a certain period. The solid-state imaging device 2 is a MOS type imaging device that is driven and controlled by the solid-state imaging device driving unit 3 and converts subject light incident on the solid-state imaging device 2 via the optical lens 1 into a pixel signal.

  The solid-state imaging device driving unit 3 receives a drive control signal that controls the transfer operation and shutter operation of the solid-state imaging device 2, and a gain control signal that controls the gain of the pixel signal output from the solid-state imaging device 2. To supply. The solid-state imaging device 2 is controlled by the drive control control signal and the gain control signal supplied from the solid-state imaging device drive circuit 3. The image signal processing unit 4 performs various image signal processing. The pixel signal subjected to the image signal processing is stored in a storage medium such as a memory or output to a monitor.

  FIG. 2 shows a configuration of the solid-state imaging device 2. The solid-state imaging device 2 includes a vertical scanning circuit 21, a pixel unit 22, a column processing unit 24, a horizontal scanning circuit 25, an output terminal 26, and a clamp voltage / gain control unit 27.

  The vertical scanning circuit 21 includes a shift register, an address decoder, and the like, and drives the pixels 23 of the pixel unit 22 in units of rows based on a drive control signal given from the solid-state image pickup device driving unit 3 outside the solid-state image pickup device 2. Take control. This drive control includes a reset operation, an accumulation operation, a signal readout operation, and the like of the pixel 23. In order to perform this drive control, the vertical scanning circuit 21 outputs a control signal to each pixel 23 and controls the pixel 23 independently for each row. When the vertical scanning circuit 21 performs drive control, a pixel signal is output from the pixel 23 to the vertical signal line VTL.

  The pixel unit 22 is configured by arranging a plurality of pixels 23 in a two-dimensional manner in the row direction and the column direction. The pixel 23 converts the optical image of the subject imaged by the optical lens 1 into a pixel signal by photoelectric conversion, and passes through the vertical signal line VTL provided for each column based on the control performed by the vertical scanning circuit 21. The pixel signal is output to the column processing unit 24. In FIG. 2, nine pixels 23 in 3 rows and 3 columns are arranged. However, the pixel arrangement shown in FIG. 2 is an example, and the number of rows and the number of columns may be two or more.

  The column processing unit 24 performs predetermined signal processing on the pixel signal output from the pixel unit 22 to the vertical signal line VTL, and temporarily holds the pixel signal after the signal processing. Specifically, the column processing unit 24 performs signal removal such as noise removal by CDS (Correlated Double Sampling), signal amplification, and AD (analog-digital) conversion on the pixel signal of the unit pixel. Process. Noise removal processing removes fixed pattern noise unique to each pixel. The signal processing illustrated here is only an example, and the signal processing is not limited to these.

  The horizontal scanning circuit 25 reads out the pixel signals by sequentially outputting the pixel signals for one row output from the column processing unit 24 in the horizontal direction. The read pixel signal is output from the output terminal 26 to the outside of the solid-state imaging device 2. The clamp voltage / gain control unit 27 performs drive control of the pixel unit 22 and the column processing unit 24 based on the gain control signal given from the solid-state imaging device drive control unit 3.

  FIG. 3 shows a circuit configuration of the pixel 23. Each transistor shown in FIG. 3 is an NMOS transistor. The pixel 23 includes a photoelectric conversion unit PD, a transfer transistor Mtx (transfer unit), a first amplification transistor Ma1, a first current source IDD1, a reset transistor Mrst, a clamp transistor Mcl (clamp unit), and a clamp capacitor. Ccl, a sample hold transistor Msh, a sample hold capacitor Csh (signal storage unit), a second amplification transistor Ma2 (output unit), and a selection transistor Msel (selection unit).

  The photoelectric conversion unit PD stores signal charges generated by photoelectrically converting incident light. Based on the control signal φTX from the vertical scanning circuit 21, the transfer transistor Mtx transfers the signal charge accumulated in the photoelectric conversion unit PD from the photoelectric conversion unit PD to the gate of the first amplification transistor Ma1. The first amplification transistor Ma1 outputs an amplification signal corresponding to the signal charge transferred to the gate from the source.

  The first current source IDD1 functions as a load of the amplification transistor Ma1, and supplies a current for driving the first amplification transistor Ma1 to the amplification transistor Ma1. The first amplification transistor Ma1 and the first current source IDD1 constitute a source follower circuit.

  The reset transistor Mrst, based on the control signal φRST from the vertical scanning circuit 21, converts the signal charge accumulated in the photoelectric conversion unit PD and the signal charge accumulated in the gate of the first amplification transistor Ma1 at the power supply voltage VDD. Reset. Based on the control signal φCL from the vertical scanning circuit 21, the clamp transistor Mcl clamps (resets) the clamp capacitor Ccl and the sample hold capacitor Csh with the clamp voltage VCL.

  The clamp capacitor Ccl removes noise of the amplified signal output from the first amplification transistor Ma1 by performing a clamping process using the sample hold transistor Msh and the clamp transistor Mcl. The sample hold transistor Msh switches the connection between the clamp capacitor Ccl and the sample hold capacitor Csh based on the control signal φSH from the vertical scanning circuit 21, samples the voltage level at the other end of the clamp capacitor Ccl, and sets the voltage level to that voltage level. The corresponding signal charge is accumulated in the sample and hold capacitor Csh.

  The sample hold capacitor Csh holds the signal charge from which noise has been removed. The second amplification transistor Ma2 outputs a pixel signal corresponding to the signal charge held in the sample hold capacitor Csh from the source. The second amplification transistor Ma2 and the second current source IDD2 connected to the vertical signal line VTL outside the pixel 23 form a source follower circuit. The selection transistor Msel reads out the pixel signal output from the second amplification transistor Ma2 to the vertical signal line VTL based on the control signal φSEL from the vertical scanning circuit 21.

  Next, the operation of the solid-state imaging device 2 will be described. FIG. 4 shows the operation of the solid-state imaging device 2. First, when the control signals φTX and φRST of all the pixels simultaneously become H level, the transfer transistor Mtx and the reset transistor Mrst are turned on. Thereby, the signal charges of the photoelectric conversion units PD of all the pixels are reset. Subsequently, when the control signals φTX and φRST are simultaneously set to the L level, accumulation of signal charges in the photoelectric conversion units PD of all the pixels is started.

  After a certain period of time has elapsed from the start of signal charge accumulation (after an arbitrary exposure time has elapsed), the control signals φSH and φCL of all the pixels simultaneously become H level, so that the sample hold transistor Msh and the clamp transistor Mcl Is turned on. As a result, the clamp capacitor Ccl and the sample hold capacitor Csh of all the pixels are clamped by the clamp voltage VCL.

  Subsequently, when the control signal φRST of all the pixels changes in a pulse shape such as an H level and an L level, the reset transistor Mrst changes between an on state and an off state. As a result, the signal charges accumulated in the gates of the first amplification transistors Ma1 of all the pixels are reset. In this state, when the control signal φCL of all the pixels becomes L level, the clamp transistor Mcl is turned off. Furthermore, the transfer signal Mtx changes between an on state and an off state when the control signal φTX of all the pixels changes in a pulse shape such as an H level and an L level.

  Thus, in all pixels, the first amplification transistor Ma1 amplification signal based on the signal charge of the photoelectric conversion unit PD when the photoelectric conversion unit PD is reset and the first signal based on the signal charge accumulated in the photoelectric conversion unit PD. The amplified signal of the amplifier transistor Ma1 is output to the clamp capacitor Ccl, and noise is removed by taking the difference between these amplified signals by the clamp capacitor Ccl, and the amplified signal after noise removal is transferred to the sample hold capacitor Csh Is done. Thereafter, when the control signal φSH of all the pixels becomes L level, the sample hold transistor Msh is turned off. As a result, the amplified signal after noise removal is held in the sample hold capacitor Csh in all pixels.

  Subsequently, pixel signals are read out as follows. The selection transistor Msel is turned on when the control signal φSEL of the target row from which the pixel signal is read becomes H level. As a result, the pixel signal based on the signal held in the sample hold capacitor Csh is read out to the vertical signal line VTL via the selection transistor Msel. Furthermore, when the control signal φCL of the row from which the pixel signal is read changes in order from the H level to the L level, the clamp transistor Mcl changes from the on state to the off state. As a result, the pixel signal based on the clamp signal (clamp voltage VCL) of the sample hold capacitor Csh is read out to the vertical signal line VTL via the selection transistor Msel.

  Noise is removed by taking the difference between the two signals read out to the vertical signal line VTL in the column processing unit 24 as described above. Then, when the control signal φSEL of the row from which the pixel signal is read becomes L level, the selection transistor Msel is turned off, and the reading of the pixel signal is completed. By sequentially performing this operation row by row, the pixel signals of all the pixels are read out. In the above operation, the signal charges accumulated in the photoelectric conversion parts PD of all the pixels are transferred in a lump, so that the signal charges can be accumulated simultaneously.

  FIG. 5 shows the voltage applied to the sample and hold capacitor Csh during the signal holding period from when the clamp capacitor Ccl and the sample and hold capacitor Csh are clamped until the pixel signal based on the signal held in the sample and hold capacitor Csh is read (FIG. 3). The voltage of the signal line A of FIG. Times T1 to T4 in FIG. 5 correspond to times T1 to T4 in FIG. When the control signal φCL becomes H level at time T1, the voltage applied to the sample hold capacitor Csh becomes the clamp voltage VCL.

  After that, when the control signal φCL becomes L level and the control signal φTX becomes H level at time T2, the voltage applied to the sample hold capacitor Csh corresponds to the signal charge accumulated in the photoelectric conversion unit PD from the clamp voltage VCL. The voltage VPIX (after noise removal) decreases. At time T3, when the control signal φSH becomes L level, the sample hold transistor Msh is turned off and the signal holding period starts. After that, when the control signal φCL becomes H level again at time T4, the voltage applied to the sample and hold capacitor Csh becomes the clamp voltage VCL, and the signal holding period ends.

  Here, VMIN in FIG. 5 represents the lower limit of the voltage applied to the sample-and-hold capacitor Csh corresponding to the voltage that can be output from the second amplification transistor Ma2. Since the upper limit of the voltage applied to the sample-and-hold capacitor Csh is the clamp voltage VCL, the output range (= pixel output range) of the second amplification transistor Ma2 is VCL−VMIN. That is, as the clamp voltage VCL becomes smaller, the output range becomes narrower.

  FIG. 6 shows the voltages of the gate, back gate, and drain of the sample hold transistor Msh during the signal holding period. During the signal holding period, since the control signal φSH is at the L level, the gate voltage is 0. Further, since the back gate of the NMOS transistor is connected to the ground, the voltage of the back gate is also zero.

  The drain voltage connected to the sample-and-hold capacitor Csh is VCL−VPIX, which is lower than the clamp voltage VCL by the voltage VPIX corresponding to the signal charge accumulated in the photoelectric conversion unit PD. Therefore, in the signal holding period, a potential difference VCL−VPIX is generated between the gate and drain of the sample hold transistor Msh and between the back gate and drain. When the potential difference VCL−VPIX is larger, more charge leaks from the gate or back gate to the drain.

  Although the sample hold transistor Msh has been described in FIG. 6, the same applies to the clamp transistor Mcl whose drain is connected to the sample hold capacitor Csh, and between the gate and drain and between the back gate and drain during the signal holding period. A potential difference VCL−VPIX is generated. The smaller the signal charge stored in the photoelectric conversion unit PD, the larger the potential difference VCL−VPIX between the gate and drain of the clamp transistor Mcl and between the back gate and drain, and the more the charge leakage.

  On the other hand, by reducing the clamp voltage VCL, the potential difference between the gate and the drain and between the back gate and the drain can be reduced, and charge leakage can be reduced. In this case, as described above with reference to FIG. 5, since the output range of the pixel is VCL−VMIN, the output range becomes narrower when the clamp voltage VCL is reduced.

  In general, when shooting with a short exposure using a digital camera or when shooting in a dark place, the image is displayed at an appropriate brightness by amplifying the pixel signal by setting a high ISO sensitivity. . Further, when the high ISO sensitivity is set, the amount of charge to be handled is smaller than when the low ISO sensitivity is set. Therefore, the output range of the pixel signal may be narrow at the high ISO sensitivity.

  In the present embodiment, the output range of the pixel signal is determined from the set value of the ISO sensitivity determined according to the shooting conditions, and the clamp voltage is determined accordingly. That is, the clamp voltage is controlled in accordance with the amplification amount of the pixel signal.

  FIG. 7 shows a control system of a gain control signal sent from the solid-state imaging device driving unit 3 outside the solid-state imaging device 2 to the solid-state imaging device 2. The clamp voltage / gain control unit 27 includes a clamp voltage control unit 27-1 that controls the clamp voltage and a gain control unit 27-2 that controls the gain of the pixel signal output from the pixel unit 22. The column processing unit 24 includes a signal amplification circuit 24-1 that amplifies the pixel signal output from the pixel unit 22 to the column processing unit 24.

  The gain control signal output from the solid-state imaging device driving unit 3 is a control signal based on the ISO sensitivity determined by the imaging conditions, and is received by the clamp voltage / gain control unit 27 in the solid-state imaging device 2. The clamp voltage control unit 27-1 in the clamp voltage / gain control unit 27 determines the output range of the pixel signal output from the pixel 23 based on the received gain control signal, and based on the output range, the pixel unit Sets the clamp voltage VCL supplied to 22. At the same time, the gain control unit 27-2 in the clamp voltage / gain control unit 27 sets the gain of the signal amplification circuit 24-1 in the column processing unit based on the received gain control signal.

  FIG. 8 shows control for each ISO sensitivity setting of the clamp voltage / gain control unit 27. At the time of setting the low ISO sensitivity, the gain control unit 27-2 sets the gain of the signal amplification circuit 24-1 low and sets the output range of the pixel signal output from the pixel unit 22 wide. When setting the output range wide, the clamp voltage control unit 27-1 sets the clamp voltage VCL high. By setting the clamp voltage VCL high, the output range VCL−VMIN of the pixel becomes wide.

  When setting the high ISO sensitivity, the gain control unit 27-2 sets the gain of the signal amplification circuit 24-1 high and sets the output range of the pixel signal output from the pixel unit 22 narrow. When the output range is set narrow, the clamp voltage control unit 27-1 sets the clamp voltage VCL low. By setting the clamp voltage VCL low, the output range VCL−VMIN of the pixel is narrowed. However, since a high gain is applied by the signal amplification circuit 24-1, the range of the signal output from the output terminal 26 is widened. In addition, the potential difference VCL−VPIX between the gate and drain of the sample hold transistor Msh (clamp transistor Mcl) and the back gate and drain during the signal holding period can be lowered, and leakage can be suppressed. By suppressing the leak for each pixel, it is possible to suppress the variation in the leak that occurs in the image.

  As described above, in this embodiment, not only the signal amplification gain but also the clamp voltage is controlled, so that deterioration in image quality due to variation in charge leakage during the signal holding period can be suppressed. .

  In this embodiment, the signal amplification circuit is provided in the column processing unit. However, there may be a signal amplification circuit in another place such as between the horizontal scanning circuit and the output terminal. Also good. In the present embodiment, the clamp voltage control unit is provided in the solid-state imaging device. However, the clamp voltage may be controlled outside the solid-state imaging device and supplied to the solid-state imaging device. For example, the solid-state imaging device driving unit 3 in FIG. 1 may have a clamp voltage control unit. The above may be the same in the following embodiments.

(Second embodiment)
Next, a second embodiment of the present invention will be described. The configuration of the imaging device according to the present embodiment is the same as the configuration of the imaging device according to the first embodiment except for the pixel unit 22. In the first embodiment, an NMOS transistor is used as a transistor in a circuit constituting a pixel. However, in this embodiment, a PMOS transistor is used.

  FIG. 9 shows a circuit configuration of the pixel 23 in the present embodiment. Each transistor shown in FIG. 9 is a PMOS transistor.

  Similarly to the pixel 23 (FIG. 3) in the first embodiment, the pixel 23 includes a photoelectric conversion unit PD, a transfer transistor Mtx (transfer unit), a first amplification transistor Ma1, and a first current source IDD1. , Reset transistor Mrst, clamp transistor Mcl (clamp unit), clamp capacitor Ccl, sample hold capacitor Csh (signal storage unit), sample hold transistor Msh, and second amplification transistor Ma2 (output unit) A transistor Msel (selection unit) is included. The functions of the components in FIG. 9 are the same as the functions described in the first embodiment, and thus description thereof is omitted.

  FIG. 10 shows the operation of the solid-state imaging device 2. Since the transistor constituting the circuit of the pixel 23 is a PMOS transistor, each transistor is turned on when the control signal applied to the gate is L level, and is turned off when the control signal applied to the gate is H level. And the ON / OFF relationship is reversed from that of the NMOS transistor. Therefore, the timing chart of this embodiment is obtained by switching the L level and the H level in the timing chart shown in FIG. The rest is the same as FIG. 4 of the first embodiment, and a description thereof will be omitted.

  FIG. 11 shows the voltage applied to the sample and hold capacitor Csh during the signal holding period from when the clamp capacitor Ccl and the sample and hold capacitor Csh are clamped until the pixel signal based on the signal held in the sample and hold capacitor Csh is read (FIG. 9). The voltage of the signal line B of FIG. Times T1 to T4 in FIG. 11 correspond to times T1 to T4 in FIG. When the control signal φCL becomes L level at time T1, the voltage applied to the sample hold capacitor Csh becomes the clamp voltage VCL.

  After that, when the control signal φCL becomes H level and the control signal φTX becomes L level at time T2, the voltage applied to the sample hold capacitor Csh corresponds to the signal charge accumulated in the photoelectric conversion unit PD from the clamp voltage VCL. The voltage increases by VPIX (after noise removal). At time T3, when the control signal φSH becomes H level, the sample hold transistor Msh is turned off and the signal holding period starts. Thereafter, when the control signal φCL becomes L level again at time T4, the voltage applied to the sample hold capacitor Csh becomes the clamp voltage VCL, and the signal holding period ends.

  Here, VMAX in FIG. 11 represents the upper limit of the voltage applied to the sample-and-hold capacitor Csh corresponding to the voltage that can be output from the second amplification transistor Ma2. Since the lower limit of the voltage applied to the sample hold capacitor Csh is the clamp voltage VCL, the output range (= pixel output range) of the second amplification transistor Ma2 is VMAX−VCL. That is, as the clamp voltage VCL increases, the output range becomes narrower.

  FIG. 12 shows the voltages of the gate, back gate, and drain of the sample hold transistor Msh during the signal holding period. Since the control signal φSH is at the H level during the signal holding period, the gate voltage is the power supply voltage VDD. Further, since the back gate of the PMOS transistor is connected to the power supply voltage VDD, the voltage of the back gate is also VDD.

  The drain voltage connected to the sample-and-hold capacitor Csh is VCL + VPIX, which is higher than the clamp voltage VCL by a voltage VPIX corresponding to the signal charge accumulated in the photoelectric conversion unit PD. Therefore, in the signal holding period, a potential difference VDD− (VCL + VPIX) is generated between the gate and drain of the sample hold transistor Msh and between the back gate and drain. If this potential difference is larger, more charge leaks from the gate or back gate to the drain.

  In FIG. 12, the sample-and-hold transistor Msh has been described, but the same applies to the clamp transistor Mcl whose drain is connected to the sample-and-hold capacitor Csh. During the signal holding period, between the gate and drain and between the back gate and drain. A potential difference VDD− (VCL + VPIX) is generated.

  Also in this embodiment, as in the first embodiment, the output range is reduced by reducing the potential difference VDD− (VCL + VPIX) between the gate and drain of the sample hold transistor Msh and between the back gate and drain in order to reduce charge leakage. VMAX-VCL becomes narrower. However, in the first embodiment, the charge leakage and the output range are reduced by reducing the clamp voltage VCL. However, in this embodiment, the charge leakage and the output range are reduced by increasing the clamp voltage. Is different.

  The control system of the gain control signal sent from the solid-state imaging device driving unit 3 outside the solid-state imaging device 2 to the solid-state imaging device 2 is the same as that in FIG.

  FIG. 13 shows control for each ISO sensitivity setting of the clamp voltage / gain control unit 27 when a PMOS transistor is used. At the time of setting the low ISO sensitivity, the gain control unit 27-2 sets the gain of the signal amplification circuit 24-1 low and sets the output range of the pixel signal output from the pixel unit 22 wide. When setting the output range wide, the clamp voltage control unit 27-1 sets the clamp voltage VCL low. By setting the clamp voltage VCL low, the output range VMAX−VCL of the pixel is widened.

  When setting the high ISO sensitivity, the gain control unit 27-2 sets the gain of the signal amplification circuit 24-1 high and sets the output range of the pixel signal output from the pixel unit 22 narrow. When setting the output range narrow, the clamp voltage control unit 27-1 sets the clamp voltage VCL high. By setting the clamp voltage VCL high, the output range VMAX−VCL of the pixel is narrowed, but since a high gain is applied by the signal amplification circuit 24-1, the range of the signal output from the output terminal 26 is widened. Further, the potential difference VDD− (VCL + VPIX) between the gate and the drain of the sample hold transistor Msh (clamp transistor Mcl) and the back gate and the drain during the signal holding period can be lowered to suppress the leakage. By suppressing the leak for each pixel, it is possible to suppress the variation in the leak that occurs in the image.

  As described above, when using a solid-state imaging device in which a pixel is configured by a PMOS transistor, the same effect as that of the first embodiment can be obtained by setting the clamp voltage to be low when setting the low gain and high when setting the high gain. (Suppression of deterioration in image quality due to variation in charge leakage during the signal holding period) can be obtained.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 13 shows a cross-sectional structure of the solid-state imaging device 2 in the present embodiment. The solid-state imaging device 2 has a structure in which two substrates (a first substrate 201 and a second substrate 202) on which circuit elements (a photoelectric conversion unit, a transistor, a capacitor, and the like) constituting the pixel 23 are arranged overlap each other. Have. Circuit elements constituting the pixel 23 are distributed and arranged on the first substrate 201 and the second substrate 202. The first substrate 201 and the second substrate 202 are electrically connected so that an electric signal can be exchanged between the two substrates when the pixel 23 is driven.

  Of the two main surfaces of the first substrate 201 (surface having a relatively larger surface area than the side surface), the photoelectric conversion part is formed on the main surface side on which the light L is irradiated, and the first substrate The light irradiated on 201 enters the photoelectric conversion unit. Of the two main surfaces of the first substrate 201, a connecting portion 203 for connecting the second substrate 202 is disposed on the main surface opposite to the main surface on which the light L is irradiated. ing.

  The vertical scanning circuit 21, the column processing unit 24, and the horizontal scanning circuit 25 other than the pixel 23 may be disposed on either the first substrate 201 or the second substrate 202, respectively. In addition, circuit elements constituting each of the vertical scanning circuit 21, the column processing unit 24, and the horizontal scanning circuit 25 may be distributed on the first substrate 201 and the second substrate 202.

  FIG. 15 shows a circuit configuration of the pixel 23. FIG. 15 shows a circuit configuration of the pixel 23 in the first substrate 201 and a circuit configuration of the pixel 23 in the second substrate 202. Both of them are electrically connected to each other by a connection unit 203 on a pixel basis.

  The pixel 23 on the first substrate 201 side includes a photoelectric conversion unit PD, a transfer transistor Mtx, a first amplification transistor Ma1, a first current source IDD1, and a reset transistor Mrst. Since the details of the photoelectric conversion unit PD, the transfer transistor Mtx (transfer unit), the first amplification transistor Ma1, the first current source IDD1, and the reset transistor Mrst are the same as those in the first embodiment, the description will be given. Omitted.

  The pixel 23 on the second substrate 202 side includes a clamp transistor Mcl (clamp unit), a clamp capacitor Ccl, a sample hold capacitor Csh (signal storage unit), a sample hold transistor Msh, and a second amplification transistor Ma2 (output) Part) and a selection transistor Msel (selection part). The details of the clamp transistor Mcl, the clamp capacitor Ccl, the sample hold capacitor Csh, the sample hold transistor Msh, the second amplification transistor Ma2, and the selection transistor Msel are the same as those in the first embodiment, and thus the description thereof is omitted. To do.

  The source of the first amplification transistor Ma1 disposed on the first substrate 201 and the clamp capacitor Ccl disposed on the second substrate 202 are connected via a connection unit 203. The pixel signal obtained by the photoelectric conversion unit PD on the first substrate 201 side is transferred to the sample and hold capacitor Csh through the connection unit 203.

  In this manner, the photoelectric conversion unit is formed on the main surface side of the first substrate 201 where the light is irradiated, and the signal storage unit is formed on the second substrate 202, thereby reducing the light receiving area of the photoelectric conversion unit. It is possible to secure and improve the light receiving sensitivity. For this reason, in the present embodiment in which the light receiving sensitivity is improved, it is possible to obtain the same effect as the first embodiment (suppression of image quality deterioration due to variation in charge leakage during the signal holding period). In addition, since the circuit elements constituting the pixel are distributed and arranged on the two stacked substrates, an increase in the chip area can be suppressed.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. The configuration of the imaging device according to the present embodiment is the same as the configuration of the imaging device according to the first embodiment except for the pixel unit 22. The pixel in the fourth embodiment has fewer transistors and capacitors than the pixel shown in the first embodiment.

  FIG. 16 shows a circuit configuration of the pixel 23 in the present embodiment. All the transistors shown in FIG. 16 are NMOS transistors as in the first embodiment. The pixel 23 includes a photoelectric conversion unit PD, a transfer transistor Mtx (transfer unit), a clamp transistor Mcl (clamp unit), a sample hold capacitor Csh (signal storage unit), and a second amplification transistor Ma2 (output unit). And a selection transistor Msel (selection unit). The configuration of the pixel 23 shown in FIG. 16 is the same as that of the pixel 23 (FIG. 3) shown in the first embodiment, but the first amplification transistor Ma1, the first current source IDD1, the reset transistor Mrst, and the clamp capacitor This is a configuration excluding Ccl and the sample hold transistor Msh.

  The photoelectric conversion unit PD stores signal charges generated by photoelectrically converting incident light. The transfer transistor Mtx transfers the signal charge accumulated in the photoelectric conversion unit from the photoelectric conversion unit PD to the sample hold capacitor Csh based on the control signal φTX from the vertical scanning circuit 21. The clamp transistor Mcl clamps (resets) the sample and hold capacitor Csh with the clamp voltage VCL based on the control signal φCL from the vertical scanning circuit 21.

  The sample hold capacitor Csh holds the signal charge transferred from the photoelectric conversion unit PD. The second amplification transistor Ma2 outputs a pixel signal corresponding to the signal charge held in the sample hold capacitor Csh from the source. The second amplification transistor Ma2 and the second current source IDD2 connected to the vertical signal line VTL outside the pixel 23 form a source follower circuit. The selection transistor Msel reads out the pixel signal output from the second amplification transistor Ma2 to the vertical signal line VTL based on the control signal φSEL from the vertical scanning circuit 21.

  FIG. 17 shows the operation of the solid-state imaging device 2. First, when the control signals φTX and φCL of all the pixels are simultaneously set to the H level, the transfer transistor Mtx and the clamp transistor Mcl are turned on. Thereby, the signal charges of the photoelectric conversion units PD of all the pixels are reset. Subsequently, when the control signals φTX and φCL of all the pixels simultaneously become L level, the transfer transistor Mtx and the clamp transistor Mcl are turned off. Thereby, accumulation of signal charges in the photoelectric conversion units PD of all pixels is started.

  After a certain period of time has elapsed from the start of signal charge accumulation (after an arbitrary exposure time has elapsed), the control signal φCL of all the pixels changes in a pulse shape such as an H level and an L level. It changes between on state and off state. As a result, the sample and hold capacitors Csh of all the pixels are clamped to the clamp voltage VCL. Furthermore, the transfer signal Mtx changes between an on state and an off state when the control signal φTX of all the pixels changes in a pulse shape such as an H level and an L level. As a result, the signal charges accumulated in the photoelectric conversion units PD of all the pixels are transferred to and held in the sample and hold capacitor Csh.

  Subsequently, pixel signals are read out as follows. The selection transistor Msel is turned on when the control signal φSEL of the target row from which the pixel signal is read becomes H level. As a result, the pixel signal based on the signal held in the sample hold capacitor Csh is read out to the vertical signal line VTL via the selection transistor Msel. Furthermore, when the control signal φCL of the row from which the pixel signal is read changes in order from the H level to the L level, the clamp transistor Mcl changes from the on state to the off state. As a result, the pixel signal based on the clamp signal (clamp voltage VCL) of the sample hold capacitor Csh is read out to the vertical signal line VTL via the selection transistor Msel.

  Noise is removed by taking the difference between the two signals read out to the vertical signal line VTL in the column processing unit 24 as described above. Then, when the control signals φCL and φSEL of the row from which the pixel signal is read are set to the L level, the clamp transistor Mcl and the selection transistor Msel are turned off, and the reading of the pixel signal is completed. By sequentially performing this operation row by row, the pixel signals of all the pixels are read out. In the above operation, the signal charges accumulated in the photoelectric conversion parts PD of all the pixels are transferred in a lump, so that the signal charges can be accumulated simultaneously.

  FIG. 18 shows the voltage applied to the sample hold capacitor Csh during the signal holding period from when the sample hold capacitor Csh is clamped until the pixel signal based on the signal held in the sample hold capacitor Csh is read (signal line D in FIG. 16). Voltage). Times T1 to T4 in FIG. 18 correspond to times T1 to T4 in FIG. When the control signal φCL becomes H level at time T1, the voltage applied to the sample hold capacitor Csh becomes the clamp voltage VCL.

  After that, when the control signal φCL becomes L level and the control signal φTX becomes H level at time T2, the voltage applied to the sample hold capacitor Csh corresponds to the signal charge accumulated in the photoelectric conversion unit PD from the clamp voltage VCL. The voltage to be reduced is VPIX. At time T3, the control signal φTX becomes L level, so that the transfer transistor Mtx is turned off and a signal holding period starts. After that, when the control signal φCL becomes H level again at time T4, the voltage applied to the sample and hold capacitor Csh becomes the clamp voltage VCL, and the signal holding period ends.

  Also in this embodiment, as in the first embodiment, the output range VCL−VMIN is narrowed by reducing the clamp voltage VCL, but the back gate and drain of the transfer transistor Mtx or the back gate of the clamp transistor Mcl. -Since the potential difference VCL-VPIX between the drains can be reduced, charge leakage and the output range can be reduced.

  As described above, even in a solid-state imaging device having pixels with a simple configuration as shown in FIG. 16, by controlling the clamp voltage, it is possible to suppress deterioration in image quality due to variation in charge leakage during the signal holding period. be able to. In this embodiment, an NMOS transistor is used as a transistor in a circuit constituting a pixel. However, even if a PMOS transistor is used, the same effect as in this embodiment can be obtained.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  DESCRIPTION OF SYMBOLS 1 ... Optical lens, 2 ... Solid-state imaging device, 3 ... Solid-state imaging device drive part, 4 ... Image signal processing part, 21 ... Vertical scanning circuit, 22 ... Pixel part, 23 ... Pixels, 24 ... Column processing section, 24-1 ... Signal amplification circuit, 25 ... Horizontal scanning circuit, 26 ... Output terminal, 27 ... Clamp voltage / gain control section, 27 -1 ... Clamp voltage control unit, 27-2 ... Gain control unit, 201 ... First substrate, 202 ... Second substrate, 203 ... Connection unit

Claims (9)

Having a plurality of pixels,
The pixel is
A photoelectric conversion unit;
A signal accumulating unit for accumulating signal charges generated in the photoelectric conversion unit;
An output unit for outputting a pixel signal based on the signal charge accumulated in the signal accumulation unit from the pixel;
A clamp unit that resets the signal charge stored in the signal storage unit with a clamp voltage;
In addition,
A solid-state imaging device comprising: a clamp voltage control unit that controls the clamp voltage based on imaging conditions. The pixel includes a MOS transistor in which one of a source and a drain is connected to the signal storage unit,
When shooting under a shooting condition in which the output range of the output unit is narrower, the clamp voltage control unit is configured such that the potential of the back gate of the MOS transistor, the potential of the gate of the MOS transistor in the off state, and the clamp voltage The solid-state imaging device according to claim 1, wherein the clamp voltage is controlled so as to reduce a potential difference between the two.   3. The clamp voltage control unit according to claim 2, wherein the MOS transistor is an NMOS transistor and the clamp voltage control unit lowers the clamp voltage when shooting is performed under a shooting condition in which the output range of the output unit is narrower. Solid-state imaging device.   3. The clamp voltage control unit according to claim 2, wherein the MOS transistor is a PMOS transistor, and the clamp voltage control unit increases the clamp voltage when shooting is performed under a shooting condition in which an output range of the output unit is narrower. Solid-state imaging device. A solid-state imaging device having a plurality of pixels, wherein a first substrate on which circuit elements constituting the pixels are arranged and a second substrate are electrically connected,
The photoelectric conversion unit is disposed on the first substrate,
The solid-state imaging device according to claim 1, wherein the signal storage unit is disposed on the second substrate. A signal amplifying circuit for amplifying the pixel signal output from the output unit;
A gain control unit that controls the gain of the signal amplification circuit based on imaging conditions;
The solid-state imaging device according to claim 1, further comprising:   When the gain control unit controls the gain of the signal amplification circuit so as to increase the amplification amount of the pixel signal, the clamp voltage control unit sets the clamp voltage so that the output range of the output unit becomes narrower. The solid-state imaging device according to claim 6, wherein the solid-state imaging device is controlled. The pixel further includes a transfer unit that transfers the signal charge generated in the photoelectric conversion unit to the signal storage unit,
8. The solid-state imaging device according to claim 1, wherein the transfer units of all the pixels transfer the signal charges in a lump. A solid-state imaging device having a plurality of pixels, and a clamp voltage control unit that controls a clamp voltage based on imaging conditions;
The pixel is
A photoelectric conversion unit;
A signal accumulating unit for accumulating signal charges generated in the photoelectric conversion unit;
An output unit for outputting a pixel signal based on the signal charge accumulated in the signal accumulation unit from the pixel;
A clamp unit that resets the signal charge stored in the signal storage unit with the clamp voltage;
An imaging device comprising:

Images