JP2013168720A - Solid-state imaging device and imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device and an imaging device that are capable of suppressing a change in characteristics at a connection part connecting two substrates.SOLUTION: A first substrate 20 has a connection part 250a, a second substrate 21 has a connection part 250b, and the first substrate 20 and the second substrate 21 are electrically connected via the connection parts. The area of a portion where the connection part 250a and the connection part 250b overlap each other when being viewed in a direction perpendicular to a main surface of the first substrate 20 or a main surface of the second substrate 21 is maintained almost equal between a case where a relative displacement between the connection part 250a and the connection part 250b occurs and a case where it does not occur.

Description

  The present invention relates to a solid-state imaging device and an imaging device in which a first substrate on which circuit elements constituting pixels are arranged and a second substrate are electrically connected.

  In recent years, video cameras, electronic still cameras, and the like have been widely used. For these cameras, CCD (Charge Coupled Device) type and amplification type solid-state imaging devices are used. An amplification type solid-state imaging device guides signal charges generated and accumulated by a photoelectric conversion unit of a pixel on which light is incident to an amplification unit provided in the pixel, and outputs a signal amplified by the amplification unit from the pixel. In an amplification type solid-state imaging device, a plurality of such pixels are arranged in a two-dimensional matrix. Examples of the amplification type solid-state imaging device include a CMOS-type solid-state imaging device using a complementary metal oxide semiconductor (CMOS) transistor.

  Conventionally, a general CMOS-type solid-state imaging device employs a method of sequentially reading out signal charges generated by photoelectric conversion units of pixels arranged in a two-dimensional matrix for each row. In this method, since the exposure timing in the photoelectric conversion unit of each pixel is determined by the start and end of reading of the signal charge, the exposure timing is different for each row. For this reason, when a fast moving subject is imaged using such a CMOS solid-state imaging device, the subject is distorted in the captured image.

  In order to eliminate the distortion of the subject, a simultaneous imaging function (global shutter function) that realizes the simultaneous accumulation of signal charges has been proposed. In addition, applications of CMOS solid-state imaging devices having a global shutter function are increasing. In a CMOS type solid-state imaging device having a global shutter function, it is usually necessary to have a storage capacitor unit having a light shielding property in order to store signal charges generated by a photoelectric conversion unit until reading is performed. . In such a conventional CMOS type solid-state imaging device, after exposing all pixels simultaneously, the signal charges generated by each photoelectric conversion unit are simultaneously transferred to each storage capacitor unit by all pixels and temporarily stored. The charges are sequentially converted into pixel signals at a predetermined readout timing and read out.

  However, in a conventional CMOS solid-state imaging device having a global shutter function, the photoelectric conversion unit and the storage capacitor unit must be formed on the same plane of the same substrate, and an increase in chip area is inevitable. In addition, during the standby period until the signal charge accumulated in the storage capacitor section is read, the signal quality deteriorates due to noise caused by light and noise caused by leakage current (dark current) generated in the storage capacitor section. There is a problem that it ends up.

  In order to solve this problem, a MOS image sensor chip in which a micropad is formed on the wiring layer side for each unit cell, and a signal processing in which a micropad is formed on the wiring layer side at a position corresponding to the micropad of the MOS image sensor chip Patent Document 1 discloses a solid-state imaging device in which a chip is connected by micro bumps. Further, Patent Document 2 discloses a method of preventing an increase in chip area by a solid-state imaging device in which a first substrate on which a photoelectric conversion unit is formed and a second substrate on which a plurality of MOS transistors are formed are bonded. ing.

  FIG. 13 (a) shows a cross-sectional configuration of a solid-state imaging device configured by bonding the two substrates described above. The first substrate 90 and the second substrate 91 are electrically connected by a connection part 900 including micropads and microbumps. FIG. 13B shows a planar configuration of the first substrate 90 of the solid-state imaging device. Pixels 910 are arranged in a two-dimensional matrix on the first substrate 90.

JP 2006-49361 A JP 2010-219339 A

  However, when the two substrates are bonded together, it is difficult to align the connecting portions due to the influence of the warp of the wafer. FIG. 14 schematically shows the state of the connecting portion when the wafer is warped. As shown in FIG. 14, two substrates are connected via a connection portion 900 a provided on the first substrate 90 and a connection portion 900 b provided on the second substrate 91. When the wafer is warped in this state, even if the connection portions are aligned at a certain position in the substrate, the relative positions of the connection portions are shifted at other positions in the substrate. When the relative positions of the connection portions are shifted, the area of the portion where the connection portions are in contact changes according to the shift, and characteristics (for example, electrical resistance such as resistance value) in the connection portions 900a and 900b connected to each other are changed. Characteristics) may change.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device and an imaging device that can suppress a change in characteristics at a connection portion that connects two substrates. .

  The present invention has been made to solve the above-described problems, and includes a first substrate having a first circuit element and a first connection part constituting a pixel, and a second circuit constituting the pixel. A second substrate having an element and a second connection portion, wherein the first substrate and the second substrate are electrically connected via the first connection portion and the second connection portion. The main surface of the first substrate or the main surface of the second substrate depending on whether or not the relative displacement between the first connection portion and the second connection portion occurs. The solid-state imaging device is characterized in that the area of the overlapping portion of the first connection portion and the second connection portion is kept substantially the same when viewed in a direction perpendicular to the vertical direction.

  In the solid-state imaging device of the present invention, the shape of the first connection portion is parallel to the first direction when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. Two first long sides and two first short sides shorter than the two first long sides, and the main surface of the first substrate or the second substrate. The shape of the second connection portion when viewed in the direction perpendicular to the main surface is two second long sides parallel to the second direction and two second long sides shorter than the two second long sides. The first direction is different from the second direction.

  In the solid-state imaging device of the present invention, the shape of the first connection portion is parallel to the first direction when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. A first rectangular side having two first long sides and two first short sides shorter than the two first long sides, and the main surface of the first substrate or the second substrate. The shape of the second connection portion when viewed in the direction perpendicular to the main surface is two second long sides parallel to the second direction and two second long sides shorter than the two second long sides. The rectangle has a short side, and the first direction and the second direction are different.

  In the solid-state imaging device of the present invention, the first direction and the second direction are orthogonal to each other.

  In the solid-state imaging device according to the present invention, the position of the center of gravity of the first connection portion and the second connection portion when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. It is characterized in that the position of the center of gravity coincides.

  In the solid-state imaging device of the present invention, the first substrate includes a plurality of the first connection portions, the second substrate includes a plurality of the second connection portions, and a plurality of the first connection portions. In one connection portion, the first direction is the same, and in the plurality of second connection portions, the second direction is the same.

  In the solid-state imaging device of the present invention, the first substrate has a plurality of the first connection portions, the second substrate has a plurality of the second connection portions, and the first substrate The plurality of first connection portions have the same shape and the plurality of second connection portions have the same shape when viewed in a direction perpendicular to the main surface of the substrate or the main surface of the second substrate. And

  In the solid-state imaging device of the present invention, the first substrate has a plurality of the first connection portions, the second substrate has a plurality of the second connection portions, and the first substrate The areas of the plurality of first connection portions are the same and the areas of the plurality of second connection portions are the same when viewed in a direction perpendicular to the main surface of the substrate or the main surface of the second substrate. And

  In addition, the present invention provides a first substrate having a first circuit element and a first connection portion constituting a pixel, and a second substrate having a second circuit element and a second connection portion constituting the pixel. Two substrates, and the first substrate and the second substrate are electrically connected via the first connection portion and the second connection portion, and the first connection portion and Whether the relative displacement of the second connection portion occurs or not occurs, the first substrate viewed in the direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. The imaging device is characterized in that the area of the overlapping portion of the connecting portion and the second connecting portion is kept substantially the same.

  According to the present invention, the first connecting portion and the second connecting portion are perpendicular to the main surface of the first substrate or the main surface of the second substrate depending on whether or not the relative displacement occurs. Since the area of the portion where the first connection portion and the second connection portion overlap is kept substantially the same when viewed in any direction, it is possible to suppress changes in characteristics at the connection portion connecting the two substrates.

It is a block diagram which shows the structure of the imaging device to which the solid-state imaging device by one Embodiment of this invention is applied. It is a block diagram which shows the structure of the solid-state imaging device by one Embodiment of this invention. It is sectional drawing of the solid-state imaging device by one Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is a timing chart which shows operation | movement of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is a timing chart which shows operation | movement of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is the top view and sectional view which show the state of the connection part with which the solid-state imaging device by one Embodiment of this invention is provided. It is the top view and sectional view which show the state of the connection part with which the solid-state imaging device by one Embodiment of this invention is provided. It is a reference figure showing the state of the connection part with which the solid imaging device by one embodiment of the present invention is provided. It is a reference figure showing the state of the connection part with which the solid imaging device by one embodiment of the present invention is provided. It is a reference figure showing the state of the connection part with which the solid imaging device by one embodiment of the present invention is provided. It is a reference figure showing the shape of the connection part with which the solid-state imaging device by one embodiment of the present invention is provided. It is sectional drawing and a top view of the conventional solid-state imaging device. FIG. 6 is a reference diagram illustrating a state of a connection portion when a wafer warps.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a digital camera as an example of an imaging apparatus to which the solid-state imaging apparatus according to the present embodiment is applied. The imaging device according to one embodiment of the present invention may be an electronic device having an imaging function, and may be a digital video camera, an endoscope, or the like in addition to a digital camera. A digital camera 10 shown in FIG. 1 includes a lens unit 1, a lens control device 2, a solid-state imaging device 3, a drive circuit 4, a memory 5, a signal processing circuit 6, a recording device 7, a control device 8, and a display device 9.

  The lens unit 1 includes a zoom lens and a focus lens, and forms light from the subject as a subject image on the light receiving surface of the solid-state imaging device 3. The lens control device 2 controls zoom, focus, aperture, and the like of the lens unit 1. The light taken in via the lens unit 1 is imaged on the light receiving surface of the solid-state imaging device 3. The solid-state imaging device 3 converts the subject image formed on the light receiving surface into an image signal and outputs the image signal. On the light receiving surface of the solid-state imaging device 3, a plurality of pixels are two-dimensionally arranged in the row direction and the column direction.

  The drive circuit 4 drives the solid-state imaging device 3 and controls its operation. The memory 5 temporarily stores image data. The signal processing circuit 6 performs a predetermined process on the image signal output from the solid-state imaging device 3. The processing performed by the signal processing circuit 6 includes amplification of an image signal, various corrections of image data, compression of image data, and the like.

  The recording device 7 includes a semiconductor memory for recording or reading image data, and is built in the digital camera 10 in a detachable state. The display device 9 displays a moving image (live view image), displays a still image, displays a moving image and a still image recorded in the recording device 7, displays a state of the digital camera 10, and the like.

  The control device 8 controls the entire digital camera 10. The operation of the control device 8 is defined by a program stored in a ROM built in the digital camera 10. The control device 8 reads this program and performs various controls according to the contents defined by the program.

  FIG. 2 shows the configuration of the solid-state imaging device 3. The solid-state imaging device shown in FIG. 2 includes a pixel unit 200 (pixel array), a vertical scanning circuit 300, a column processing circuit 350, a horizontal scanning circuit 400, and an output amplifier 410. The arrangement position of each circuit element shown in FIG. 2 does not necessarily coincide with the actual arrangement position.

  The pixel unit 200 includes pixels 100 arranged in a two-dimensional matrix and a current source 130 provided for each column. In the present embodiment, the area composed of all pixels of the solid-state imaging device 3 is set as a pixel signal readout target area, but a part of the area composed of all pixels of the solid-state imaging apparatus 3 may be set as the readout target area. It is desirable that the read target area includes at least all pixels in the effective pixel area. Further, the read target area may include an optical black pixel (a pixel that is always shielded from light) arranged outside the effective pixel area. The pixel signal read from the optical black pixel is used for correcting a dark current component, for example.

  The vertical scanning circuit 300 performs drive control of the pixel unit 200 in units of rows. In order to perform this drive control, the vertical scanning circuit 300 includes unit circuits 301-1, 301-2,..., 301-n (n is the number of rows) as many as the number of rows.

  Each unit circuit 301-i (i = 1, 2,..., N) outputs a control signal for controlling the pixels 100 for one row to the signal line 110 provided for each row. The signal line 110 is connected to the pixel 100, and supplies the control signal output from the unit circuit 301-i to the pixel 100. In FIG. 2, each signal line 110 corresponding to each row is represented by one line, but each signal line 110 includes a plurality of signal lines. The signal of the pixel 100 in the row selected by the control signal is output to the vertical signal line 120 provided for each column.

  The current source 130 is connected to the vertical signal line 120, and forms a source follower circuit with amplification transistors (second amplification transistors 241, 242, 243, and 244 described later) in the pixel 100. The column processing circuit 350 performs signal processing such as noise suppression on the pixel signal output to the vertical signal line 120. The horizontal scanning circuit 400 outputs the pixel signals of one row of pixels 100 output to the vertical signal line 120 and processed by the column processing circuit 350 to the output amplifier 410 in time series in the order of horizontal alignment. The output amplifier 410 amplifies the pixel signal output from the horizontal scanning circuit 400 and outputs it as an image signal to the outside of the solid-state imaging device 3.

  FIG. 3 shows a cross-sectional structure of the solid-state imaging device 3. The solid-state imaging device 3 has a structure in which two substrates (first substrate 20 and second substrate 21) on which circuit elements (photoelectric conversion elements, transistors, capacitors, etc.) constituting the pixel 100 are arranged overlap each other. Circuit elements constituting the pixel 100 are distributed and arranged on the first substrate 20 and the second substrate 21. The first substrate 20 and the second substrate 21 are electrically connected so that an electric signal can be exchanged between the two substrates when the pixel 100 is driven.

  Of the two main surfaces of the first substrate 20 (surface having a relatively larger surface area than the side surface), a photoelectric conversion element is formed on the main surface side on which the light L is irradiated. The irradiated light enters the photoelectric conversion element. Of the two main surfaces of the first substrate 20, a connecting portion 250 for connecting to the second substrate 21 is formed on the main surface opposite to the main surface on which the light L is irradiated. A signal based on the signal charge generated by the photoelectric conversion element disposed on the first substrate 20 is output to the second substrate 21 via the connection unit 250. In the example shown in FIG. 3, the areas of the main surfaces of the first substrate 20 and the second substrate 21 are different, but the areas of the main surfaces of the first substrate 20 and the second substrate 21 may be the same.

  The vertical scanning circuit 300, the column processing circuit 350, the horizontal scanning circuit 400, and the output amplifier 410 other than the pixel 100 may be arranged on either the first substrate 20 or the second substrate 21, respectively. Further, the circuit elements constituting each of the vertical scanning circuit 300, the column processing circuit 350, the horizontal scanning circuit 400, and the output amplifier 410 may be distributed on the first substrate 20 and the second substrate 21.

  FIG. 4 shows a circuit configuration of a pixel cell composed of four pixels 100. In the present embodiment, an example in which some circuit elements are shared by four pixels arranged in the vertical direction will be described. A pixel cell composed of four pixels 100 includes photoelectric conversion elements 201, 202, 203, 204, first transfer transistors 211, 212, 213, 214, a charge holding unit 230 (floating diffusion), 1 reset transistor 220, first amplification transistor 240, current source 280, clamp capacitor 260, second transfer transistors 271, 272, 273, 274, second reset transistors 221, 222, 223, 224, analog Memory 231, 232, 233, 234, second amplification transistor 241, 242, 243, 244 and selection transistor 291, 292, 293, 294. The arrangement position of each circuit element shown in FIG. 4 does not necessarily coincide with the actual arrangement position.

  The pixel cell includes circuit elements of four pixels 100. The first pixel includes a photoelectric conversion element 201, a first transfer transistor 211, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, a current source 280, a clamp capacitor 260, a second capacitor It includes a transfer transistor 271, a second reset transistor 221, an analog memory 231, a second amplification transistor 241, and a selection transistor 291. The second pixel includes a photoelectric conversion element 202, a first transfer transistor 212, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, a current source 280, a clamp capacitor 260, a second capacitor A transfer transistor 272, a second reset transistor 222, an analog memory 232, a second amplification transistor 242 and a selection transistor 292 are included.

  The third pixel includes a photoelectric conversion element 203, a first transfer transistor 213, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, a current source 280, a clamp capacitor 260, a second capacitor It includes a transfer transistor 273, a second reset transistor 223, an analog memory 233, a second amplification transistor 243, and a selection transistor 293. The fourth pixel includes a photoelectric conversion element 204, a first transfer transistor 214, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, a current source 280, a clamp capacitor 260, a second capacitance, It has a transfer transistor 274, a second reset transistor 224, an analog memory 234, a second amplification transistor 244, and a selection transistor 294. The charge holding unit 230, the first reset transistor 220, the first amplification transistor 240, the current source 280, and the clamp capacitor 260 are shared by the four pixels 100.

  One ends of the photoelectric conversion elements 201, 202, 203, and 204 are grounded. The drain terminals of the first transfer transistors 211, 212, 213, and 214 are connected to the other ends of the photoelectric conversion elements 201, 202, 203, and 204. The gate terminals of the first transfer transistors 211, 212, 213, and 214 are connected to the vertical scanning circuit 300, and transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 are supplied.

  One end of the charge holding unit 230 is connected to the source terminals of the first transfer transistors 211, 212, 213, and 214, and the other end of the charge holding unit 230 is grounded. The drain terminal of the first reset transistor 220 is connected to the power supply voltage VDD, and the source terminal of the first reset transistor 220 is connected to the source terminals of the first transfer transistors 211, 212, 213, and 214. The gate terminal of the first reset transistor 220 is connected to the vertical scanning circuit 300, and a reset pulse ΦRST1 is supplied.

  The drain terminal of the first amplification transistor 240 is connected to the power supply voltage VDD. A gate terminal which is an input portion of the first amplification transistor 240 is connected to the source terminals of the first transfer transistors 211, 212, 213 and 214. One end of the current source 280 is connected to the source terminal of the first amplification transistor 240, and the other end of the current source 280 is grounded. As an example, the current source 280 may be configured by a transistor whose drain terminal is connected to the source terminal of the first amplification transistor 240, whose source terminal is grounded, and whose gate terminal is connected to the vertical scanning circuit 300. One end of the clamp capacitor 260 is connected to the source terminal of the first amplification transistor 240 and one end of the current source 280 via the connection portion 250.

  The drain terminals of the second transfer transistors 271, 272, 273, 274 are connected to the other end of the clamp capacitor 260. The gate terminals of the second transfer transistors 271, 272, 273, and 274 are connected to the vertical scanning circuit 300, and are supplied with transfer pulses ΦTX2-1, ΦTX2-2, ΦTX2-3, and ΦTX2-4. The drain terminals of the second reset transistors 221, 222, 223, 224 are connected to the power supply voltage VDD, and the source terminals of the second reset transistors 221, 222, 223, 224 are the second transfer transistors 271, 272, 273, 274. Connected to the source terminal. The gate terminals of the second reset transistors 221, 222, 223, and 224 are connected to the vertical scanning circuit 300, and reset pulses ΦRST2-1, ΦRST2-2, ΦRST2-3, and ΦRST2-4 are supplied.

  One end of the analog memories 231, 232, 233, and 234 is connected to the source terminals of the second transfer transistors 271, 272, 273, and 274, and the other ends of the analog memories 231, 232, 233, and 234 are grounded. The drain terminals of the second amplification transistors 241, 242, 243, and 244 are connected to the power supply voltage VDD. The gate terminals constituting the input parts of the second amplification transistors 241, 242, 243, 244 are connected to the source terminals of the second transfer transistors 271, 272, 273, 274. The drain terminals of the selection transistors 291, 292, 293 and 294 are connected to the source terminals of the second amplification transistors 241, 242, 243 and 244, and the source terminals of the selection transistors 291, 292, 293 and 294 are the vertical signal line 120. It is connected to the. The gate terminals of the selection transistors 291, 292, 293, and 294 are connected to the vertical scanning circuit 300 and are supplied with selection pulses ΦSEL 1, ΦSEL 2, ΦSEL 3, and ΦSEL 4. For each of the transistors described above, the polarity may be reversed, and the source terminal and the drain terminal may be reversed.

  The photoelectric conversion elements 201, 202, 203, and 204 are, for example, photodiodes, generate (generate) signal charges based on incident light, and hold and store the generated (generated) signal charges. The first transfer transistors 211, 212, 213, and 214 are transistors that transfer signal charges accumulated in the photoelectric conversion elements 201, 202, 203, and 204 to the charge holding unit 230. On / off of the first transfer transistors 211, 212, 213, and 214 is controlled by transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 from the vertical scanning circuit 300. The charge holding unit 230 is a floating diffusion capacitor that temporarily holds and accumulates signal charges transferred from the photoelectric conversion elements 201, 202, 203, and 204.

  The first reset transistor 220 is a transistor that resets the charge holding unit 230. ON / OFF of the first reset transistor 220 is controlled by a reset pulse ΦRST1 from the vertical scanning circuit 300. It is also possible to reset the photoelectric conversion elements 201, 202, 203, and 204 by simultaneously turning on the first reset transistor 220 and the first transfer transistors 211, 212, 213, and 214. The reset of the charge holding unit 230 / photoelectric conversion elements 201, 202, 203, 204 is performed by controlling the amount of charge accumulated in the charge holding unit 230 / photoelectric conversion elements 201, 202, 203, 204. The state (potential) of the photoelectric conversion elements 201, 202, 203, 204 is set to the reference state (reference potential, reset level).

  The first amplifying transistor 240 is a transistor that outputs an amplified signal obtained by amplifying a signal based on the signal charge stored in the charge holding unit 230, which is input to the gate terminal, from the source terminal. The current source 280 functions as a load of the first amplification transistor 240 and supplies a current for driving the first amplification transistor 240 to the first amplification transistor 240. The first amplification transistor 240 and the current source 280 constitute a source follower circuit.

  The clamp capacitor 260 is a capacitor that clamps (fixes) the voltage level of the amplified signal output from the first amplification transistor 240. The second transfer transistors 271, 272, 273, and 274 are transistors that sample and hold the voltage level at the other end of the clamp capacitor 260 and store them in the analog memories 231, 232, 233, and 234. On / off of the second transfer transistors 271, 272, 273, 274 is controlled by transfer pulses ΦTX2-1, ΦTX2-2, ΦTX2-3, and ΦTX2-4 from the vertical scanning circuit 300.

  The second reset transistors 221, 222, 223, and 224 are transistors that reset the analog memories 231, 232, 233, and 234. On / off of the second reset transistors 221, 222, 223, and 224 is controlled by reset pulses ΦRST2-1, ΦRST2-2, ΦRST2-3, and ΦRST2-4 from the vertical scanning circuit 300. The analog memory 231,232,233,234 is reset by controlling the amount of charge stored in the analog memory 231,232,233,234 and the state (potential) of the analog memory 231,232,233,234 as a reference state. (Reference potential, reset level). The analog memories 231, 232, 233, and 234 hold and store analog signals sampled and held by the second transfer transistors 271, 272, 273, and 274.

  The capacity of the analog memories 231, 232, 233, and 234 is set to be larger than the capacity of the charge holding unit 230. For the analog memories 231, 232, 233, and 234, it is more preferable to use a MIM (Metal Insulator Metal) capacity or a MOS (Metal Oxide Semiconductor) capacity, which is a capacity with a small leakage current (dark current) per unit area. Thereby, resistance to noise is improved, and a high-quality signal can be obtained.

  The second amplification transistors 241, 242, 243, and 244 output from the source terminal an amplified signal obtained by amplifying a signal based on the signal charges stored in the analog memories 231, 232, 233, and 234, which is input to the gate terminal. It is a transistor. The second amplification transistors 241, 242, 243, and 244 and the current source 130 connected to the vertical signal line 120 constitute a source follower circuit. The selection transistors 291, 292, 293, and 294 are transistors that select the pixel 100 and transmit the outputs of the second amplification transistors 241, 242, 243, and 244 to the vertical signal line 120. ON / OFF of the selection transistors 291, 292, 293 and 294 is controlled by selection pulses ΦSEL 1, ΦSEL 2, ΦSEL 3 and ΦSEL 4 from the vertical scanning circuit 300.

  Among the circuit elements shown in FIG. 4, photoelectric conversion elements 201, 202, 203, 204, first transfer transistors 211, 212, 213, 214, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, a current The source 280 is disposed on the first substrate 20. In addition, a clamp capacitor 260, second transfer transistors 271, 272, 273, 274, second reset transistors 221, 222, 223, 224, analog memories 231, 232, 233, 234, second amplification transistors 241, 242, 243, 244 and selection transistors 291, 292, 293 and 294 are arranged on the second substrate 21.

  A connection portion 250 is disposed between the first substrate 20 and the second substrate 21. The amplified signal output from the first amplification transistor 240 on the first substrate 20 is output to the second substrate 21 via the connection unit 250.

  In FIG. 4, the connection part 250 is arranged on the path between the source terminal of the first amplification transistor 240 and one end of the current source 280 and one end of the clamp capacitor 260, but this is not restrictive. The connecting portion 250 may be disposed anywhere on the electrically connected path from the first transfer transistors 211, 212, 213, 214 to the second transfer transistors 271, 272, 273, 274.

  For example, it is connected to a path between the source terminals of the first transfer transistors 211, 212, 213, and 214, one end of the charge holding unit 230, the source terminal of the first reset transistor 220, and the gate terminal of the first amplification transistor 240. The part 250 may be arranged. Alternatively, the connection part 250 may be disposed in a path between the other end of the clamp capacitor 260 and the drain terminals of the second transfer transistors 271, 272, 273, and 274.

  Next, the operation of the pixel 100 will be described with reference to FIG. FIG. 5 shows control signals supplied from the vertical scanning circuit 300 to the pixels 100 for each row. Hereinafter, the operation will be described in units of pixel cells including the four pixels shown in FIG.

[Operation during period T1]
First, when the reset pulse ΦRST1 changes from “L” (Low) level to “H” (High) level, the first reset transistor 220 is turned on. At the same time, the transfer pulse ΦTX1-1 changes from the “L” level to the “H” level, whereby the first transfer transistor 211 is turned on. As a result, the photoelectric conversion element 201 of the first pixel is reset.

  Subsequently, when the reset pulse ΦRST1 and the transfer pulse ΦTX1-1 change from the “H” level to the “L” level, the first reset transistor 220 and the first transfer transistor 211 are turned off. Thereby, the reset of the photoelectric conversion element 201 of the first pixel is finished, and exposure of the first pixel (accumulation of signal charge) is started. In the same manner as described above, the photoelectric conversion element 202 of the second pixel, the photoelectric conversion element 203 of the third pixel, and the photoelectric conversion element 204 of the fourth pixel are sequentially reset, and exposure of each pixel is started. In FIG. 4, the reset pulse ΦRST1 becomes “H” level at the timing when the transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 become “H” level. , 203, and 204, the reset pulse ΦRST1 may always be at “H” level.

[Operation during period T2]
Subsequently, when the reset pulse ΦRST2-1 changes from the “L” level to the “H” level, the second reset transistor 221 is turned on. As a result, the analog memory 231 is reset. At the same time, the transfer pulse ΦTX2-1 changes from the “L” level to the “H” level, whereby the second transfer transistor 271 is turned on. As a result, the potential at the other end of the clamp capacitor 260 is reset to the power supply voltage VDD, and the second transfer transistor 271 starts to sample and hold the potential at the other end of the clamp capacitor 260.

  Subsequently, when the reset pulse ΦRST1 changes from the “L” level to the “H” level, the first reset transistor 220 is turned on. As a result, the charge holding unit 230 is reset. Subsequently, when the reset pulse ΦRST1 changes from the “H” level to the “L” level, the first reset transistor 220 is turned off. Thereby, the reset of the charge holding unit 230 is completed. The timing for resetting the charge holding unit 230 may be during the exposure period, but noise due to the leakage current of the charge holding unit 230 is further reduced by resetting the charge holding unit 230 at a timing immediately before the end of the exposure period. can do.

  Subsequently, when the reset pulse ΦRST2-1 changes from the “H” level to the “L” level, the second reset transistor 221 is turned off. Thereby, the reset of the analog memory 231 is completed. At this time, the clamp capacitor 260 clamps the amplified signal (the amplified signal after resetting the charge holding unit 230) output from the first amplification transistor 240.

[Operation during period T3]
First, when the transfer pulse ΦTX1-1 changes from the “L” level to the “H” level, the first transfer transistor 211 is turned on. As a result, the signal charge accumulated in the photoelectric conversion element 201 is transferred to the charge holding unit 230 via the first transfer transistor 211 and accumulated in the charge holding unit 230. Thereby, the exposure (accumulation of signal charge) of the first pixel is completed. The period from the start of exposure of the first pixel in the period T1 to the end of exposure of the first pixel in the period T3 is an exposure period (signal accumulation period). Subsequently, when the transfer pulse ΦTX1-1 changes from the “H” level to the “L” level, the first transfer transistor 211 is turned off.

  Subsequently, when the transfer pulse ΦTX2-1 changes from “H” level to “L” level, the second transfer transistor 271 is turned off. As a result, the second transfer transistor 271 finishes sampling and holding the potential at the other end of the clamp capacitor 260.

[Operation during period T4]
The operations in the above-described periods T2 and T3 are operations of the first pixel. In the period T4, operations similar to those in the periods T2 and T3 are performed for the second pixel, the third pixel, and the fourth pixel. It is more desirable that the length of the exposure period of each pixel is the same.

  Hereinafter, a change in potential at one end of the analog memory 231 will be described. The same applies to changes in the potential at one end of the analog memories 232, 233, and 234. The change in potential at one end of the charge holding unit 230 due to the transfer of the signal charge from the photoelectric conversion element 201 to the charge holding unit 230 after the reset of the charge holding unit 230 is completed, and the gain of the first amplification transistor 240 is α1. Then, the change ΔVamp1 of the source terminal of the first amplification transistor 240 due to the transfer of the signal charge from the photoelectric conversion element 201 to the charge holding unit 230 is α1 × ΔVfd.

  Assuming that the total gain of the analog memory 231 and the second transfer transistor 271 is α2, one end of the analog memory 231 by the sample hold of the second transfer transistor 271 after the signal charge is transferred from the photoelectric conversion element 201 to the charge holding unit 230. The potential change ΔVmem is α2 × ΔVamp1, that is, α1 × α2 × ΔVfd. ΔVfd is the amount of change in the potential of one end of the charge holding unit 230 due to the transfer of signal charge, and does not include reset noise generated by resetting the charge holding unit 230. Therefore, when the second transfer transistor 271 performs sample hold, the influence of noise generated in the photoelectric conversion element 201 can be reduced.

Since the potential at one end of the analog memory 231 when the reset of the analog memory 231 is completed is the power supply voltage VDD, the signal charge is transferred from the photoelectric conversion element 201 to the charge holding unit 230 and then sampled by the second transfer transistor 271. The held potential Vmem at one end of the analog memory 231 is expressed by the following equation (1). In the equation (1), ΔVmem <0 and ΔVfd <0.
Vmem = VDD + ΔVmem
= VDD + α1 × α2 × ΔVfd (1)

  Α2 is expressed by the following equation (2). In the equation (2), CL is a capacitance value of the clamp capacitor 260, and CSH is a capacitance value of the analog memory 231. In order to further reduce the decrease in gain, it is more desirable that the capacitance CL of the clamp capacitor 260 is larger than the capacitance CSH of the analog memory 231.

[Operation during period T5]
In the period T5, signals based on the signal charges accumulated in the analog memories 231, 232, 233, and 234 are sequentially read for each row. First, a signal is read from the first pixel. When the selection pulse ΦSET1 changes from the “L” level to the “H” level, the selection transistor 291 is turned on. As a result, a signal based on the potential Vmem shown in the equation (1) is output to the vertical signal line 120 via the selection transistor 291.

  Subsequently, when the reset pulse ΦRST2-1 changes from the “L” level to the “H” level, the second reset transistor 221 is turned on. As a result, the analog memory 231 is reset, and a signal based on the potential at one end of the analog memory 231 at the time of reset is output to the vertical signal line 120 via the selection transistor 291.

  Subsequently, when the reset pulse ΦRST2-1 changes from the “H” level to the “L” level, the second reset transistor 221 is turned off. Subsequently, when the selection pulse ΦSET1 changes from the “H” level to the “L” level, the selection transistor 291 is turned off.

  The column processing circuit 350 generates a difference signal obtained by taking a difference between a signal based on the potential Vmem shown in the equation (1) and a signal based on the potential of one end of the analog memory 231 when the analog memory 231 is reset. This difference signal is a signal based on the difference between the potential Vmem and the power supply voltage VDD shown in the equation (1), and holds the charge immediately after the signal charge accumulated in the photoelectric conversion element 201 is transferred to the charge holding unit 230. This is a signal based on the difference ΔVfd between the potential at one end of the unit 230 and the potential of the charge holding unit 230 immediately after one end of the charge holding unit 230 is reset. Accordingly, it is possible to obtain a signal component based on the signal charge accumulated in the photoelectric conversion element 201, in which a noise component due to resetting the analog memory 231 and a noise component due to resetting the charge holding unit 230 are suppressed.

  The signal output from the column processing circuit 350 is output to the output amplifier 410 by the horizontal scanning circuit 400. The output amplifier 410 processes the signal output from the horizontal scanning circuit 400 and outputs it as an image signal. Thus, reading of the signal from the first pixel is completed.

[Operation during period T6]
Subsequently, the same operation as the operation of the first pixel in the period T5 is performed on each of the second pixel, the third pixel, and the fourth pixel.

  In the above operation, the signal holding unit 230 must hold the signal charge transferred from the photoelectric conversion elements 201, 202, 203, 204 to the charge holding unit 230 until the readout timing of each pixel 100. When noise is generated during the period in which the charge holding unit 230 holds the signal charge, the noise is superimposed on the signal charge held by the charge holding unit 230, and the signal quality (S / N) is deteriorated.

  The main causes of noise generated during the period in which the charge holding unit 230 holds the signal charge (hereinafter referred to as the holding period) are the charge due to the leakage current of the charge holding unit 230 (hereinafter referred to as the leakage charge) and , Charge caused by light incident on portions other than the photoelectric conversion elements 201, 202, 203, and 204 (hereinafter referred to as photocharge). Assuming that the leak charge and photocharge generated in the unit time are qid and qpn, respectively, and the length of the holding period is tc, the noise charge Qn generated during the holding period is (qid + qpn) tc.

  The capacity of the charge holding unit 230 is Cfd, the capacity of the analog memories 231, 232, 233, and 234 is Cmem, and the ratio of Cfd to Cmem (Cmem / Cfd) is A. As described above, the gain of the first amplification transistor 240 is α1, and the total gain of the analog memories 231, 232, 233, 234 and the second transfer transistors 271, 272, 273, 274 is α2. If the signal charges generated in the photoelectric conversion elements 201, 202, 203, and 204 during the exposure period are Qph, the signal charges held in the analog memories 231, 232, 233, and 234 after the end of the exposure period are A × α1 × α2. × Qph.

  Signals based on the signal charges transferred from the photoelectric conversion elements 201, 202, 203, 204 to the charge holding unit 230 are sampled and held by the second transfer transistors 271, 272, 273, 274, and analog memories 231, 232, 233, 234 Stored in Therefore, the time from when the signal charge is transferred to the charge holding unit 230 until the signal charge is stored in the analog memories 231, 232, 233, 234 is short, and noise generated in the charge holding unit 230 can be ignored. . S / N is A × α1 × α2 × Qph / Qn assuming that the noise generated during the period in which the analog memories 231, 232, 233, and 234 hold signal charges is the same Qn as described above.

  On the other hand, as in the prior art described in Patent Document 2, the S / N when the signal charge held in the capacitor storage unit is read from the pixel via the amplification transistor is Qph / Qn. Therefore, the S / N of this embodiment is A × α1 × α2 times the S / N of the prior art. The capacity values of the analog memories 231, 232, 233, and 234 are set so that A × α1 × α2 is greater than 1 (for example, the capacity values of the analog memories 231, 232, 233, and 234 are set to the capacity of the charge holding unit 230 By making it sufficiently larger than the value, it is possible to reduce degradation of signal quality.

  In the present embodiment, the operation timings of pixel cells having the same vertical position (hereinafter referred to as vertical positions) are the same, but the operation timings of pixel cells having different vertical positions are different. FIG. 6 schematically shows the operation timing of pixel cells having different vertical positions (V1, V2,..., Vn). The vertical position in FIG. 6 indicates the vertical position in the pixel cell array, and the horizontal position indicates the time position.

  The reset period corresponds to the period T1 in FIG. 5, the signal transfer period corresponds to the periods T2, T3, and T4 in FIG. 5, and the read period corresponds to the periods T5 and T6 in FIG. As shown in FIG. 6, the reset period and the signal transfer period are the same in pixel cells having different vertical positions. On the other hand, readout periods are different in pixel cells having different vertical positions. In the above-described operation, the exposure timing is different for each pixel in the same pixel cell, but it is possible to realize exposure synchronism in the entire pixel cell.

  Next, details of the connecting portion 250 that connects the first substrate 20 and the second substrate 21 will be described. FIG. 7 schematically shows the state of the connecting portion 250. FIG. 7A shows the state of the connecting portion 250 on the first substrate 20, and FIG. 7B shows the state of the connecting portion 250 on the second substrate 21. The upper side of FIGS. 7 (a) and 7 (b) is a connection portion when viewed in a direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21 (a direction parallel to the normal line of each main surface). 7 shows the state of 250, and the lower side of FIGS. 7 (a) and 7 (b) is a direction parallel to the main surfaces of the first substrate 20 and the second substrate 21 (a direction perpendicular to the normal line of each main surface). The state of the connection part 250 when seen in FIG.

  A plurality of connecting portions 250a are arranged in a two-dimensional matrix on the main surface facing the second substrate 21 of the two main surfaces of the first substrate 20. A plurality of connection portions 250b are arranged in a two-dimensional matrix on the main surface facing the first substrate 20 out of the two main surfaces of the second substrate 21. The connection parts 250a and 250b are micro bumps made of metal, for example. In FIG. 7, the arrangement of the connection portions 250a and 250b is shown as an example in which the arrangement of the pixels 100 is 2 rows and 3 columns, but the arrangement of the connection portions 250a and 250b is not limited thereto.

  The shape of each connecting portion 250a of the first substrate 20 and the shape of each connecting portion 250b of the second substrate 21 are unified with a rectangle having the same area. When viewed in a direction perpendicular to the main surface of the first substrate 20, the shape of the connecting portion 250a of the first substrate 20 is two long sides parallel to the Y direction in FIG. 7 and the X direction (in the Y direction in FIG. 7). It is a rectangle with two short sides parallel to the vertical direction. Further, when viewed in a direction perpendicular to the main surface of the second substrate 21, the shape of the connecting portion 250b of the second substrate 21 is two long sides parallel to the X direction in FIG. 7 and the Y direction (X It is a rectangle having two short sides parallel to the direction perpendicular to the direction. The directions of the long sides of the rectangles (Y direction) of all the connection portions 250a of the first substrate 20 are the same, and the directions of the long sides of the rectangles (X direction) of all the connection portions 250b of the second substrate 21 are also the same. is there. Thus, the direction of the long side of the rectangle of the connection part 250a of the first substrate 20 (Y direction) is different from the direction of the long side of the rectangle of the connection part 250b of the second substrate 21 (X direction). For all connections, these directions are orthogonal in FIG.

  FIG. 8 schematically shows the state of the connecting portion 250 when the first substrate 20 and the second substrate 21 are connected. The upper side of FIG. 8 shows the state of the connecting portion 250 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21, and the lower side of FIG. The state of the connecting portion 250 when viewed in the direction parallel to the main surfaces of the two substrates 21 is shown. When the first substrate 20 and the second substrate 21 are connected, the center of gravity of the connection portion 250a of the first substrate 20 and the second substrate 20 are viewed in a direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21, respectively. The connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 are arranged on each substrate so that the center of gravity of the connection portion 250b of the substrate 21 coincides.

  FIG. 9 shows only the connection part 250 when the first substrate 20 and the second substrate 21 are connected. FIG. 9A shows the center of gravity of the connection portion 250a of the first substrate 20 and the center of gravity of the connection portion 250b of the second substrate 21 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21, respectively. This shows a state in which the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 are aligned so as to match. The relative positional relationship between the connecting portion 250a of the first substrate 20 and the connecting portion 250b of the second substrate 21 in FIG. 9A is the same as the connecting portion 250a of the first substrate 20 and the connecting portion of the second substrate 21 in FIG. It is the same as the relative positional relationship of 250b. FIG. 9 (b) shows the main surfaces of the first substrate 20 and the second substrate 21 due to warpage of the wafer when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21, respectively. A state is shown in which the relative displacement between the connecting portion 250a of the first substrate 20 and the connecting portion 250b of the second substrate 21 occurs in a parallel direction. In FIG. 9 (b), there is a positional shift in which the connecting portion 250a of the first substrate 20 is shifted to the right side with respect to the connecting portion 250b of the second substrate 21.

  A state in which the relative displacement between the connection part 250a of the first substrate 20 and the connection part 250b of the second substrate 21 has occurred (FIG. 9B) and a state in which it has not occurred (FIG. 9A) Are compared with each other when the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 overlap each other when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21 (square shape). Area) is kept substantially the same. For this reason, it is possible to suppress a change in characteristics in the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 that are connected to each other.

  As described above, the direction of the long side of the rectangular shape of the connection portion 250a of the first substrate 20 and the connection of the second substrate 21 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. The direction of the long side of the rectangle of the portion 250b is orthogonal. The directions of the long sides of these rectangles do not have to be orthogonal, but are more preferably orthogonal. Hereinafter, the reason will be described.

  FIG. 10 shows only the connection part 250 when the first substrate 20 and the second substrate 21 are connected. FIG. 10A shows the direction of the long side of the rectangular shape of the connecting portion 250a of the first substrate 20 and the second substrate 21 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. This shows a state in which the direction of the long side of the rectangle of the connecting portion 250b is orthogonal. The relative positional relationship between the connecting portion 250a of the first substrate 20 and the connecting portion 250b of the second substrate 21 in FIG. 10 (a) is the same as the connecting portion 250a of the first substrate 20 and the connecting portion of the second substrate 21 in FIG. It is the same as the relative positional relationship of 250b. FIG. 10B shows the direction of the long side of the rectangle of the connecting portion 250a of the first substrate 20 and the second substrate 21 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. This shows a state where the direction of the long side of the rectangle of the connecting portion 250b is not orthogonal.

  Hereinafter, with respect to the relative displacement amount between the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21, the portion where the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 overlap. A positional deviation amount that falls within a range that satisfies the condition that the areas are kept substantially the same will be described. In FIG. 10 (a), when a displacement occurs in a direction parallel to the long side of the connection part 250b of the second substrate 21 (left and right direction in FIG. 10 (a)), the connection part 250b of the second substrate 21 Thus, regardless of whether the connecting portion 250a of the first substrate 20 is displaced in the left direction or the right direction, the maximum amount of positional deviation that falls within the range that satisfies the above condition is D1.

  On the other hand, in FIG. 10B, when a displacement occurs in the direction parallel to the long side of the connection part 250b of the second substrate 21 (the left-right direction of FIG. 10B), the connection part 250b of the second substrate 21. On the other hand, when the connecting portion 250a of the first substrate 20 is shifted to the left relative to the connecting portion 250b of the second substrate 21, the maximum amount of displacement that falls within the range satisfying the above condition is D2. Thus, when the connecting portion 250a of the first substrate 20 is relatively shifted to the right, the maximum amount of displacement that falls within the range satisfying the above condition is D3. Since D2 <D1 <D3, in FIG. 10B, the allowable amount of deviation (D2) with respect to the positional deviation in the left-right direction is smaller than the allowable amount of deviation (D1) in FIG. Therefore, as shown in FIG. 10 (a), each connection portion is connected to each substrate so that the directions of the long sides of the rectangles of the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 are orthogonal to each other. By disposing, the allowable amount of positional deviation can be further increased.

  As described above, the rectangular center of gravity of the connecting portion 250a of the first substrate 20 and the connecting portion 250b of the second substrate 21 are viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21, respectively. The center of gravity of the rectangle matches. The centroids of these rectangles do not need to match, but more preferably match. Hereinafter, the reason will be described.

  FIG. 11 shows only the connection part 250 when the first substrate 20 and the second substrate 21 are connected. FIG. 11A shows the connection between the second substrate 21 and the rectangular center of gravity G1 of the connecting portion 250a of the first substrate 20 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. A state in which the rectangular center of gravity G2 of the portion 250b matches is shown. The relative positional relationship between the connecting portion 250a of the first substrate 20 and the connecting portion 250b of the second substrate 21 in FIG. 11 (a) is the same as the connecting portion 250a of the first substrate 20 and the connecting portion of the second substrate 21 in FIG. It is the same as the relative positional relationship of 250b. FIG. 11B shows the connection between the second substrate 21 and the rectangular center of gravity G1 of the connecting portion 250a of the first substrate 20 when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. A state in which the rectangular center of gravity G2 of the portion 250b does not match is shown.

  Hereinafter, with respect to the relative displacement amount between the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21, the portion where the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 overlap. A positional deviation amount that falls within a range that satisfies the condition that the areas are kept substantially the same will be described. In FIG. 11 (a), when a displacement occurs in the direction parallel to the long side of the connection part 250b of the second substrate 21 (the left-right direction of FIG. 11 (a)), the connection part 250b of the second substrate 21 Thus, regardless of whether the connecting portion 250a of the first substrate 20 is displaced in the left direction or the right direction, the maximum amount of positional deviation that falls within the range that satisfies the above condition is D1.

  On the other hand, in FIG. 11 (b), when a displacement occurs in a direction parallel to the long side of the connection portion 250b of the second substrate 21 (the left-right direction of FIG. 11 (b)), the connection portion 250b of the second substrate 21. On the other hand, when the connecting portion 250a of the first substrate 20 is shifted to the left relative to the connecting portion 250b of the second substrate 21, the maximum amount of displacement that falls within the range satisfying the above condition is D4. Thus, when the connecting portion 250a of the first substrate 20 is relatively shifted to the right, the maximum amount of displacement that falls within the range satisfying the above condition is D5. Since D5 <D1 <D4, in FIG. 11 (b), the allowable displacement (D5) with respect to the lateral displacement is smaller than the allowable displacement (D1) in FIG. 11 (a). Accordingly, as shown in FIG. 11 (a), the respective connection portions are arranged on the respective substrates so that the respective rectangular centers of gravity of the connection portions 250a of the first substrate 20 and the connection portions 250b of the second substrate 21 coincide with each other. As a result, the allowable amount of positional deviation can be increased.

  As shown in FIG. 7, the shape of each connecting portion 250a of the first substrate 20 and the shape of each connecting portion 250b of the second substrate 21 are unified with a rectangle having the same area. Although the shape and area of each connection portion of each substrate need not be unified, it is more desirable that they be unified.

  Further, as shown in FIG. 7, the direction (Y direction) of the long sides of the rectangles of all the connection portions 250a of the first substrate 20 is the same, and the long sides of the rectangles of all the connection portions 250b of the second substrate 21 are the same. The direction of (X direction) is the same. The directions of the long sides of the rectangles of the respective connecting portions of the respective substrates do not have to be unified, but are preferably unified.

  As described above, by unifying the shape, area, and long side direction of each connection portion of each substrate, the allowable amount of positional deviation can be made the same for all connection portions.

  The shape of the connecting portion 250a of the first substrate 20 and the shape of the connecting portion 250b of the second substrate 21 may be other than a rectangle when viewed in the direction perpendicular to the main surfaces of the first substrate 20 and the second substrate 21. FIG. 12 shows an example of a shape other than a rectangle. The shape shown in FIG. 12 is a representative example of a shape elongated in the left-right direction.

  FIG. 12 (a) shows a connecting portion having a shape having two parallel long sides and two arc-shaped short sides. FIG. 12 (b) shows a connecting portion formed of a parallelogram having two parallel long sides and two short sides. FIG. 12 (c) shows a connecting portion formed of a trapezoid having two parallel long sides and two non-parallel short sides.

  As described above, according to the present embodiment, the first substrate 20 has a case where the relative displacement between the connection portion 250a of the first substrate 20 and the connection portion 250b of the second substrate 21 occurs or does not occur. When viewed in the direction perpendicular to the main surface or the main surface of the second substrate 21, the area where the connection part 250a and the connection part 250b overlap is kept substantially the same, so the characteristics of the connection part connecting the two substrates Can be suppressed.

  In addition, since some circuit elements are shared among a plurality of pixels, the chip area can be reduced as compared with the case where the circuit elements are not shared between the plurality of pixels. Furthermore, since the first amplification transistor 240 and the current source 280 are shared among a plurality of pixels, the number of current sources that operate simultaneously can be suppressed. For this reason, it is possible to reduce the occurrence of a power supply voltage drop or a GND (ground) voltage rise due to simultaneous operation of a large number of current sources.

  In addition, the area of the photoelectric conversion element on the first substrate 20 can be increased as compared with the case where all the circuit elements of the pixel are arranged on one substrate, so that the sensitivity is improved. Further, by using an analog memory, the area of the signal storage region provided on the second substrate 21 can be reduced.

  Further, by providing the analog memories 231, 232, 233, and 234, it is possible to reduce degradation of signal quality. In particular, the signal charge held in the analog memory by making the capacitance value of the analog memory larger than the capacitance value of the charge holding portion (for example, making the capacitance value of the analog memory more than five times the capacitance value of the charge holding portion). However, it becomes larger than the signal charge held by the charge holding unit. For this reason, it is possible to reduce the influence of signal deterioration due to the leak current of the analog memory.

  Further, by providing the clamp capacitor 260 and the second transfer transistors 271, 272, 273, and 274, the influence of noise generated in the first substrate 20 can be reduced. The noise generated in the first substrate 20 includes noise (for example, reset) generated at the input portion of the first amplification transistor 240 resulting from the operation of a circuit (for example, the first reset transistor 220) connected to the first amplification transistor 240. Noise), noise derived from the operating characteristics of the first amplification transistor 240 (for example, noise due to variations in the circuit threshold of the first amplification transistor 240), and the like.

  Further, the signal when the analog memories 231, 232, 233 and 234 are reset and the first amplification transistor 240 generated by transferring the signal charges from the photoelectric conversion elements 201, 202, 203 and 204 to the charge holding unit 230. By outputting a signal corresponding to the output fluctuation from the pixel 100 in a time-sharing manner and performing differential processing of each signal outside the pixel 100, the influence of noise generated in the second substrate 21 can be reduced. The noise generated in the second substrate 21 is derived from the operation of a circuit (for example, the second reset transistors 221, 222, 223, 224) connected to the second amplification transistors 241, 242, 243, 244. There is noise (for example, reset noise) generated at the input portion of the transistors 241, 242, 243, and 244.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. . In the above description, the configuration of the solid-state imaging device in which two substrates are connected by the connection unit is shown, but three or more substrates may be connected by the connection unit. In the case of a solid-state imaging device in which three or more substrates are connected at the connection portion, two of the three or more substrates correspond to the first substrate and the second substrate.

  DESCRIPTION OF SYMBOLS 1 ... Lens part, 2 ... Lens control apparatus, 3 ... Solid-state imaging device, 4 ... Drive circuit, 5 ... Memory, 6 ... Signal processing circuit, 7 ... Recording device , 8 ... Control device, 9 ... Display device, 100 ... Pixel, 130, 280 ... Current source, 200 ... Pixel unit, 201, 202, 203, 204 ... Photoelectric conversion element 211, 212, 213, 214 ... first transfer transistor, 220 ... first reset transistor, 221, 222, 223, 224 ... second reset transistor, 230 ... charge holding unit, 231, 232, 233, 234 ... Analog memory, 240 ... First amplification transistor, 241, 242, 243, 244 ... Second amplification transistor, 250, 250a, 250b ... Connection, 260 ... Clamp capacitance, 271, 272, 273, 274 ... second transfer transistor, 291,292,293,294 ... select transistor, 300 ... vertical scanning circuit, 350 ... column processing circuit, 40 0 ... Horizontal scanning circuit, 410 ... Output amplifier

Claims (9)

A first substrate having a first circuit element constituting the pixel and a first connection portion;
A second substrate having a second circuit element and a second connection part constituting the pixel;
Have
The first substrate and the second substrate are electrically connected via the first connection portion and the second connection portion,
A direction perpendicular to the main surface of the first substrate or the main surface of the second substrate depending on whether or not the relative displacement between the first connection portion and the second connection portion occurs. The solid-state imaging device is characterized in that the area of the portion where the first connection portion and the second connection portion overlap is kept substantially the same. The shape of the first connection portion when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate is two first long sides parallel to the first direction, and A shape having two first short sides shorter than the two first long sides;
The shape of the second connection portion when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate is two second long sides parallel to the second direction, A shape having two second short sides shorter than the two second long sides,
The solid-state imaging device according to claim 1, wherein the first direction is different from the second direction. The shape of the first connection portion when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate is two first long sides parallel to the first direction, and A rectangle having two first short sides shorter than the two first long sides;
The shape of the second connection portion when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate is two second long sides parallel to the second direction, A rectangle having two second short sides shorter than the two second long sides;
The solid-state imaging device according to claim 1, wherein the first direction is different from the second direction.   The solid-state imaging device according to claim 2, wherein the first direction and the second direction are orthogonal to each other.   The position of the center of gravity of the first connection portion and the position of the center of gravity of the second connection portion coincide with each other when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. The solid-state imaging device according to claim 2 or 3. The first substrate has a plurality of the first connection portions,
The second substrate has a plurality of the second connection portions,
In the plurality of first connection portions, the first direction is the same,
4. The solid-state imaging device according to claim 2, wherein the second direction is the same in a plurality of the second connection portions. 5. The first substrate has a plurality of the first connection portions,
The second substrate has a plurality of the second connection portions,
The plurality of first connection portions have the same shape and the plurality of second connection portions have the same shape when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided. The first substrate has a plurality of the first connection portions,
The second substrate has a plurality of the second connection portions,
The areas of the plurality of first connection portions are the same and the areas of the plurality of second connection portions are the same when viewed in a direction perpendicular to the main surface of the first substrate or the main surface of the second substrate. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided. A first substrate having a first circuit element constituting the pixel and a first connection portion;
A second substrate having a second circuit element and a second connection part constituting the pixel;
Have
The first substrate and the second substrate are electrically connected via the first connection portion and the second connection portion,
A direction perpendicular to the main surface of the first substrate or the main surface of the second substrate depending on whether or not the relative displacement between the first connection portion and the second connection portion occurs. The imaging device is characterized in that the area of the portion where the first connection portion and the second connection portion overlap is kept substantially the same.

Images