JP6040220B2 - データストリームから再生したクロック信号の調整 - Google Patents

データストリームから再生したクロック信号の調整 Download PDF

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JP6040220B2
JP6040220B2 JP2014503686A JP2014503686A JP6040220B2 JP 6040220 B2 JP6040220 B2 JP 6040220B2 JP 2014503686 A JP2014503686 A JP 2014503686A JP 2014503686 A JP2014503686 A JP 2014503686A JP 6040220 B2 JP6040220 B2 JP 6040220B2
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Prior art keywords
stream
clock signal
pulses
data
clock
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Japanese (ja)
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JP2014516489A (ja
JP2014516489A5 (enExample
Inventor
フーン チョイ
フーン チョイ
デキュン キム
デキュン キム
ジュ ファン イ
ジュ ファン イ
ヨン ドン ベ
ヨン ドン ベ
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Lattice Semiconductor Corp
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Lattice Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Synchronizing For Television (AREA)
JP2014503686A 2011-04-08 2012-03-28 データストリームから再生したクロック信号の調整 Active JP6040220B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/083,399 US8611486B2 (en) 2011-04-08 2011-04-08 Adjustment of clock signals regenerated from a data stream
US13/083,399 2011-04-08
PCT/US2012/030838 WO2012138515A2 (en) 2011-04-08 2012-03-28 Adjustment of clock signals regenerated from a data stream

Publications (3)

Publication Number Publication Date
JP2014516489A JP2014516489A (ja) 2014-07-10
JP2014516489A5 JP2014516489A5 (enExample) 2015-05-14
JP6040220B2 true JP6040220B2 (ja) 2016-12-07

Family

ID=46966131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014503686A Active JP6040220B2 (ja) 2011-04-08 2012-03-28 データストリームから再生したクロック信号の調整

Country Status (7)

Country Link
US (1) US8611486B2 (enExample)
EP (2) EP3223431B1 (enExample)
JP (1) JP6040220B2 (enExample)
KR (1) KR101889373B1 (enExample)
CN (1) CN103493424B (enExample)
TW (1) TWI536255B (enExample)
WO (1) WO2012138515A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8989277B1 (en) 2011-11-03 2015-03-24 Xilinx, Inc. Reducing artifacts within a video processing system
US9250646B2 (en) * 2012-12-19 2016-02-02 Intel Corporation Clock recovery using remote arrival timestamps
US20160142343A1 (en) * 2014-11-13 2016-05-19 Broadcom Corporation System for Recovery in Channel Bonding
KR101582171B1 (ko) * 2014-11-19 2016-01-05 서울대학교산학협력단 직접 디지털 주파수 합성기를 이용한 디스플레이포트 수신단의 비디오 클럭 생성 구조
CN110611543B (zh) * 2018-06-14 2021-04-06 扬智科技股份有限公司 定时恢复的定时锁定识别方法与信号接收电路
DE102018220301A1 (de) * 2018-11-26 2020-05-28 Festo Ag & Co. Kg Kommunikationseinheit, Steuergerät, Kommunikationssystem und Verfahren
KR102655530B1 (ko) * 2019-10-15 2024-04-08 주식회사 엘엑스세미콘 스트림 클럭 생성 장치 및 이를 포함하는 임베디드 디스플레이포트 시스템
KR102518285B1 (ko) 2021-04-05 2023-04-06 에스케이하이닉스 주식회사 PCIe 인터페이스 및 인터페이스 시스템
KR102519480B1 (ko) 2021-04-01 2023-04-10 에스케이하이닉스 주식회사 PCIe 장치 및 이를 포함하는 컴퓨팅 시스템
US11546128B2 (en) 2020-06-16 2023-01-03 SK Hynix Inc. Device and computing system including the device
KR102415309B1 (ko) * 2020-06-16 2022-07-01 에스케이하이닉스 주식회사 인터페이스 장치 및 그 동작 방법
CN115277983B (zh) * 2022-06-22 2025-08-01 江苏珞珈聚芯集成电路设计有限公司 用于dp接口的视频像素时钟恢复方法与结构
CN118250786A (zh) * 2022-12-22 2024-06-25 华为技术有限公司 时钟同步方法、装置、芯片、芯片模组、系统及存储介质
CN116580680B (zh) * 2023-07-11 2024-02-20 苏州华星光电技术有限公司 显示面板的驱动方法、亮度补偿装置及显示装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06303254A (ja) * 1993-04-19 1994-10-28 Matsushita Electric Ind Co Ltd ソースクロック再生回路
US5852630A (en) * 1997-07-17 1998-12-22 Globespan Semiconductor, Inc. Method and apparatus for a RADSL transceiver warm start activation procedure with precoding
JP3540589B2 (ja) * 1998-02-02 2004-07-07 株式会社東芝 クロック逓倍回路
JP2005079963A (ja) * 2003-09-01 2005-03-24 Pioneer Electronic Corp 映像信号伝送システム及び方法並びに送信装置及び受信装置
GB2409383B (en) * 2003-12-17 2006-06-21 Wolfson Ltd Clock synchroniser
US7738617B1 (en) * 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US7499462B2 (en) 2005-03-15 2009-03-03 Radiospire Networks, Inc. System, method and apparatus for wireless delivery of content from a generalized content source to a generalized content sink
TW200731702A (en) * 2005-07-29 2007-08-16 Koninkl Philips Electronics Nv Data stream synchronization
US7995143B2 (en) 2006-02-10 2011-08-09 Qualcomm Incorporated Wireless video link synchronization
US7956856B2 (en) 2007-02-15 2011-06-07 Parade Technologies, Ltd. Method and apparatus of generating or reconstructing display streams in video interface systems
US20090109988A1 (en) 2007-10-26 2009-04-30 Chowdhary Musunuri Video Decoder with an Adjustable Video Clock
US8111799B2 (en) * 2008-01-03 2012-02-07 Dell Products L.P. Method, system and apparatus for reducing power consumption at low to midrange resolution settings
US8391419B2 (en) * 2008-03-17 2013-03-05 Synaptics, Inc. Circuit for recovering an output clock from a source clock
US8135105B2 (en) * 2008-06-17 2012-03-13 Integraded Device Technologies, Inc. Circuit for correcting an output clock frequency in a receiving device
KR101375466B1 (ko) * 2009-01-12 2014-03-18 램버스 인코포레이티드 다중 전력 모드를 갖는 메조크로노스 시그널링 시스템
EP3664323B1 (en) * 2009-04-14 2021-07-07 ATI Technologies ULC Embedded clock recovery
JP5241638B2 (ja) * 2009-07-23 2013-07-17 川崎マイクロエレクトロニクス株式会社 表示制御装置
US8861669B2 (en) * 2009-09-30 2014-10-14 Synaptics Incorporated Stream clock recovery in high definition multimedia digital system
WO2011088610A1 (en) * 2010-01-19 2011-07-28 Integrated Device Technologies, Inc Method and circuit for displayport video clock recovery
US20110193970A1 (en) * 2010-02-11 2011-08-11 Analogix Semiconductor, Inc. Reducing Jitter in a Recovered Data Stream Clock of a Video DisplayPort Receiver

Also Published As

Publication number Publication date
TW201301124A (zh) 2013-01-01
EP2695323A4 (en) 2014-08-27
JP2014516489A (ja) 2014-07-10
CN103493424A (zh) 2014-01-01
EP2695323A2 (en) 2014-02-12
US8611486B2 (en) 2013-12-17
WO2012138515A3 (en) 2012-12-06
EP2695323B1 (en) 2017-05-10
KR101889373B1 (ko) 2018-08-17
EP3223431A1 (en) 2017-09-27
WO2012138515A2 (en) 2012-10-11
TWI536255B (zh) 2016-06-01
CN103493424B (zh) 2015-09-30
KR20140048116A (ko) 2014-04-23
US20120257699A1 (en) 2012-10-11
EP3223431B1 (en) 2018-07-25

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