JP6031650B2 - Display device, manufacturing method thereof, and electronic device - Google Patents

Description

  The present disclosure relates to a display device having a structure in which a wiring layer is laminated together with an organic insulating layer on a substrate, a manufacturing method thereof, and an electronic apparatus including the display device.

  A display device, for example, an organic EL (Electro Luminescence) display device is a display device that controls luminance by a current flowing through an organic light emitting diode. For this reason, there is a problem that characteristic unevenness of a low-temperature polysilicon thin film transistor (TFT) generally used as a switching element is likely to appear as display unevenness.

  In order to solve this problem, there has been reported a method for improving display performance in organic EL display devices by eliminating TFT characteristic unevenness by devising a drive circuit. On the other hand, the organic EL display device has a complicated circuit due to an increase in the number of TFTs and the number of wiring circuits used in comparison with a liquid crystal display device and an increase in the area of the capacitive element.

  In recent years, organic EL display devices are required to have a larger display area and higher definition. When the display area is enlarged, signal delay occurs due to a load due to wiring resistance and parasitic capacitance. In addition, when the resolution is increased, there is a problem that the wiring layer for forming the driving wiring and the signal line is increased with the increase in the number of pixels, the short circuit defect is increased, and the manufacturing yield is lowered. It was.

  In order to solve this problem, for example, in Patent Document 1, a defect part causing a line defect or a bright spot that becomes a serious defect for a display device is separated from the wiring by using a laser beam to normalize or black spot. A method for improving the manufacturing yield is disclosed. In addition, for example, in Patent Document 2, an insulating layer made of an organic resin or the like having a low dielectric constant is provided between wiring layers in order to multilayer wiring layers for forming various wirings and avoid signal delay due to the multilayering. This eliminates the increase in the density of the wiring layer. Further, in Patent Document 2, a short-circuited portion of a multilayered wiring is cut and repaired by cutting a lower layer wiring without destroying the organic resin layer using a laser beam having transparency to the organic resin. A method is disclosed.

JP 2004-342457 A JP 2012-54510 A

  However, in the method described in Patent Document 2, although good insulation can be obtained for the wiring provided in the upper layer (on the organic resin) of the organic resin, the wiring provided in the lower layer of the organic resin is desired. It was difficult to obtain insulation.

  The present technology has been made in view of such problems, and an object of the present technology is to provide a display device capable of achieving both display quality and manufacturing yield, a manufacturing method thereof, and an electronic device.

The display device of the present technology includes a first insulating layer made of an organic material on two adjacent first wirings, and a recess that penetrates between the two first wirings from the first insulating layer to the first wiring in the stacking direction. And a second insulating layer provided in the recess and on the stacked structure. The second wiring is provided between the first insulating layer and the second insulating layer, and the first insulating layer has a step between the second wiring and the other region.

The manufacturing method of the display device of the present technology includes the following steps (A) to (C).
(A) After forming a laminated structure having two adjacent first wirings and a first insulating layer made of an organic material in this order, laser light is emitted from the first insulating layer side to the short-circuit portion between the two first wirings. Irradiating and forming a recess penetrating in the stacking direction from the first insulating layer to the first wiring (B) Half ashing the peripheral region including the laser light irradiation surface (C) After the half ashing process, in the recess And forming the second insulating layer on the laminated structure

  An electronic device of the present technology includes the display device of the present technology.

  In the display device, the manufacturing method thereof, and the electronic device according to the present technology, laser light is emitted at a predetermined position of a stacked structure in which a first insulating layer (organic insulating layer) made of an organic material is formed on two adjacent first wirings. Is irradiated. Thereby, a recess penetrating from the first insulating layer to the first wiring is formed. Next, after the laser light irradiation region and its peripheral region are half-ashed, the concave portion is filled with a second insulating layer (for example, a planarization layer). Thereby, it is possible to electrically cut an arbitrary position (for example, a short-circuit portion) of the two wirings covered with the organic insulating layer.

  According to the display device, the manufacturing method thereof, and the electronic apparatus of the present technology, the peripheral region including the irradiation surface after irradiating the laser beam to a predetermined position of the laminated structure having the organic insulating layer on the two adjacent wirings The half ashing was applied to. Thus, a recess that penetrates between the two wirings from the organic insulating layer to the wirings and is electrically cut is formed. Therefore, it is possible to provide a display device that achieves both display quality and manufacturing yield, and an electronic apparatus including the display device.

It is sectional drawing showing the structure of the display apparatus which concerns on one embodiment of this indication. It is a figure showing the whole structure of the display apparatus shown in FIG. FIG. 3 is a diagram illustrating an example of a pixel drive circuit illustrated in FIG. 2 . It is a schematic diagram showing the top view (A) and sectional drawing (B) of the short circuit part of a wiring layer. It is a schematic diagram showing the top view (A) and sectional drawing (B) at the time of cut | disconnecting the short circuit part shown in FIG. It is a flowchart showing the one part process order of the manufacturing method of the display apparatus shown in FIG. It is a characteristic view showing the relationship between an applied voltage and the electric current between terminals. It is a characteristic view showing the relationship of the dielectric breakdown incidence in the cut part of the Example and comparative example of this indication. It is a characteristic view showing the relationship between half ashing time and average leak current. It is a figure showing an example of the wiring layout of the display apparatus of this indication. It is a figure showing the other example of the wiring layout of the display apparatus of this indication. It is sectional drawing of the contact part in the display apparatus of this indication. FIG. 13 is a cross-sectional view illustrating a step of cutting the contact portion illustrated in FIG. 12. FIG. 13 is a cross-sectional view in which the contact portion illustrated in FIG. 12 is filled with a pixel electrode material. FIG. 10 is a cross-sectional view illustrating a configuration of a display device according to a modified example of the present disclosure. 10 is a flowchart showing a partial process order of a method for manufacturing a display device according to a modified example of the present disclosure. It is a schematic diagram showing the process of the 1st laser irradiation shown in FIG. It is a schematic diagram showing the process of the 2nd laser irradiation shown in FIG. It is a characteristic view showing the relationship between the half ashing time and the average leakage current in the embodiments and modifications of the present disclosure. Is a perspective view illustrating an appearance viewed from the front side of Application Example 1 of Viewing device of the foregoing embodiment and the like. Is a perspective view illustrating an appearance viewed from the rear side of the application example 1 of Viewing device of the foregoing embodiment and the like. 12 is a perspective view illustrating an appearance of application example 2. FIG. 14 is a perspective view illustrating an appearance of Application Example 3 viewed from the front side. FIG. 12 is a perspective view illustrating an appearance of Application Example 3 viewed from the back side. FIG. 14 is a perspective view illustrating an appearance of application example 4. FIG. 14 is a perspective view illustrating an appearance of application example 5. FIG. FIG. 11 is a front view, a left side view, a right side view, a top view, and a bottom view of Application Example 6 in a closed state. It is the front view and side view of the application example 6 in the open state.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. Embodiment (Example of cutting the short-circuited part by laser irradiation and half ashing)
1-1. Overall configuration of display device 1-2. Manufacturing method 1-3. Action / Effect Modification (example of repeating laser irradiation multiple times)
3. Application Example (Example of Viewing device and electronic equipment)

<1. Embodiment>
(1-1. Overall configuration)
FIG. 1 illustrates a cross-sectional configuration of a display device (display device 1) according to an embodiment of the present disclosure. The display device 1 is used as, for example, an organic EL television device or the like, and a display area 110A is provided on a substrate 11 as shown in FIG. In the display area 110A, a plurality of pixels (red pixel 2R, green pixel 2G, blue pixel 2B) are arranged in a matrix. Further, a signal line driving circuit 120 and a scanning line driving circuit 130 which are drivers for video display (a peripheral circuit 12B described later) are provided in the peripheral area 110B located around the display area 110A (outer edge side, outer peripheral side). It has been.

  A pixel drive circuit 140 is provided in the display area 110A. FIG. 3 shows an example of the pixel drive circuit 140 (an example of a pixel circuit of the red pixel 2R, the green pixel 2G, and the blue pixel 2B). The pixel drive circuit 140 is an active drive circuit formed below the pixel electrode 31 described later. The pixel driving circuit 140 includes a driving transistor Tr1 and a writing transistor Tr2, and a capacitor (holding capacity) Cs between the transistors Tr1 and Tr2. The pixel drive circuit 140 also includes the light emitting element 10 connected in series to the drive transistor Tr1 between the first power supply line (Vcc) and the second power supply line (GND). That is, a corresponding light emitting element 10 (any one of the red light emitting element 10R, the green light emitting element 10G, the blue light emitting element 10B, or the white light emitting element 10W) is provided in each of the red pixel 2R, the green pixel 2G, and the blue pixel 2B. It has been. The drive transistor Tr1 and the write transistor Tr2 are configured by a general thin film transistor (TFT), and the configuration may be, for example, an inverted stagger structure (so-called bottom gate type) or a stagger structure (top gate type), and is not particularly limited.

  In the pixel driving circuit 140, a plurality of signal lines 120A are arranged in the column direction, and a plurality of scanning lines 130A are arranged in the row direction. The intersection of each signal line 120A and each scanning line 130A corresponds to any one of the red pixel 2R, the green pixel 2G, and the blue pixel 2B. Each signal line 120A is connected to the signal line drive circuit 120, and an image signal is supplied from the signal line drive circuit 120 to the source electrode of the write transistor Tr2 via the signal line 120A. Each scanning line 130A is connected to the scanning line driving circuit 130, and a scanning signal is sequentially supplied from the scanning line driving circuit 130 to the gate electrode of the writing transistor Tr2 via the scanning line 130A.

  As shown in FIG. 1, the semiconductor layer 20 and the display layer 30 are stacked in this order on the substrate 11 in the display region 110A of the display device 1 in the present embodiment. The semiconductor layer 20 includes, as a wiring layer, a wiring layer 21 including a gate electrode 21A, a channel layer 23, a wiring layer 25 including a pair of source / drain electrodes (a source electrode 25A, a drain electrode 25B, a wiring 25C), and the like. The wiring layer 25 has a multilayer wiring structure in which a wiring layer 27 is laminated with an interlayer insulating layer 26 made of an organic material interposed therebetween.

  In the present embodiment, in this multilayer wiring structure, for example, the wiring 25C together with the interlayer insulating layer 26 is connected to the wiring 25C (first wiring) of the wiring layer 25 covered with the interlayer insulating layer 26 (first insulating layer). A concave portion, that is, a cut portion A is formed by continuous cutting. The cut portion A is formed by laser irradiation and half ashing as will be described later.

FIGS. 4A and 4B respectively show a planar configuration (A) before the cutting portion A is formed and a cross-sectional configuration (B) taken along line II in FIG. 4A. Wiring 25C, for example two is constituted by linear wiring 25C ₁ and the wiring 25C ₂ adjacent, short-circuit portion 25X has occurred between the wiring 25C _1, 25C _2. FIG. 1 shows a structure in which a cut portion A is formed at a position where the wires 25C ₁ and 25C ₂ are joined by the short-circuit portion 25X.

  FIGS. 5A and 5B show a state after the cutting portion A is formed by laser irradiation and half ashing from the state of FIGS. 4A and 4B. FIG. 5A illustrates a planar configuration, and FIG. 5B illustrates a cross-sectional configuration taken along line II-II in FIG. 5A. The cut portion A is obtained by continuously cutting the upper interlayer insulating layer 26 and the wiring layer 25C as described above. Further, as shown in FIG. 1 and FIG. Specifically, it is formed as a recess that reaches the substrate 11 via the interlayer insulating layer 24 and the gate insulating layer 22. Note that as a result of forming the recesses by the laser irradiation and half ashing steps, a part of the surface of the interlayer insulating layer 26 is shaved, as is apparent from a comparison between FIGS. 4B and 5B. A step 26A is formed between the upper wiring layer 27 and the lower layer.

  Hereinafter, the semiconductor layer 20 and the display device 30 will be described.

(Configuration of semiconductor layer)
In the semiconductor layer 20 on the substrate 11, the above-described driving or writing transistors Tr1 and Tr2 and various wirings are formed, and a planarization insulating layer 28 is provided on these transistors Tr1 and Tr2 and the wirings. ing. The transistors Tr1 and Tr2 (hereinafter referred to as the thin film transistor 20A) may be either a top gate type or a bottom gate type. Here, the bottom gate type thin film transistor 20A will be described as an example. In the thin film transistor 20A, in order from the substrate 11 side, a gate electrode 21A, a gate insulating layer 22, an organic semiconductor film (channel layer 23) forming a channel region, an interlayer insulating layer 24, a pair of source / drain electrodes (source electrode 25A, drain) Electrodes 25B) are formed in this order, and an interlayer insulating layer 26 and a wiring layer 27 are provided as multilayer wiring layers.

  The substrate 11 is a glass substrate, a polyethersulfone, polycarbonate, polyimides, polyamides, polyacetals, polyethylene terephthalate, polyethylene naphthalate, polyethyl ether ketone, polyolefin Louis, etc. It is possible to use a metal foil substrate such as aluminum (Al), nickel (Ni), copper (Cu), stainless steel, or paper. Further, a functional film such as a buffer layer for improving adhesion and flatness and a barrier film for improving gas barrier properties may be formed on these substrates. Furthermore, if the channel layer 23 can be formed without heating the substrate 11 by sputtering or the like, an inexpensive plastic film can be used for the substrate 11.

  The gate electrode 21A has a role of applying a gate voltage to the thin film transistor 10 and controlling the carrier density in the channel layer 23 by the gate voltage. The gate electrode 21A is provided in a selective region on the substrate 11, for example, platinum (Pt), titanium (Ti), ruthenium (Ru), molybdenum (Mo), Cu, tungsten (W), nickel (Ni), Al And a simple metal or alloy such as tantalum (Ta). Also, two or more of these may be laminated and used.

  The gate insulating layer 22 is provided between the gate electrode 21A and the channel layer 23 in a thickness range of 50 nm to 1 μm, for example. The gate insulating layer 22 includes, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), a hafnium oxide film (HfO), an aluminum oxide film (AlO), an aluminum nitride film (AlN), By an insulating film including at least one of a tantalum oxide film (TaO), a zirconium oxide film (ZrO), a hafnium oxynitride film, a hafnium silicon oxynitride film, an aluminum oxynitride film, a tantalum oxynitride film, and a zirconium oxynitride film It is formed. The gate insulating layer 22 may have a single layer structure, or may have a laminated structure using two or more kinds of materials such as SiN and SiO. When the gate insulating layer 22 has a stacked structure, interface characteristics with the channel layer 23 can be improved, and impurities (for example, moisture) from the outside air to the channel layer 23 can be effectively suppressed. The gate insulating layer 22 is patterned into a predetermined shape by etching after coating formation, but depending on the material, the pattern may be formed by a printing technique such as inkjet printing, screen printing, offset printing, or gravure printing.

  The channel layer 23 is provided in an island shape on the gate insulating layer 22, and has a channel region 24C at a position facing the gate electrode 21A between the source electrode 25A and the drain electrode 25B. The thickness of the channel layer 23 is, for example, 5 nm to 100 nm. The channel layer 23 is made of an organic semiconductor material such as a peri-Xanthenoxanthene (PXX) derivative. Examples of the organic semiconductor material include polythiophene, poly-3-hexylthiophene having a hexyl group introduced into polythiophene [P3HT], pentacene [2,3,6,7-dibenzoanthracene], polyanthracene, naphthacene, hexacene, heptacene, Dibenzopentacene, Tetrabenzopentacene, Chrysene, Perylene, Coronene, Terylene, Ovalene, Quotylene, Circumanthracene, Benzopyrene, Dibenzopyrene, Triphenylene, Polypyrrole, Polyaniline, Polyacetylene, Polydiacetylene, Polyphenylene, Polyfuran, Polyindole, Polyvinylcarbazole, Polyseleno Phen, polytellurophene, polyisothianaphthene, polycarbazole, polyphenylene sulfide, polyphenylene vinylene, poly Phenylene sulfide, polyvinylene sulfide, polythienylene vinylene, polynaphthalene, polypyrene, polyazulene, phthalocyanine represented by copper phthalocyanine, merocyanine, hemicyanine, polyethylenedioxythiophene, pyridazine, naphthalene tetracarboxylic acid diimide, poly (3,4 Ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS], 4,4′-biphenyldithiol (BPDT), 4,4′-diisocyanobiphenyl, 4,4′-diisocyano-p-terphenyl, 2, 5-bis (5′-thioacetyl-2′-thiophenyl) thiophene, 2,5-bis (5′-thioacetoxyl-2′-thiophenyl) thiophene, 4,4′-diisocyanophenyl, benzidine (biphenyl) 4,4′-diamine), TCNQ (tetracyanoquinodimethane), tetrathiafulvalene (TTF) -TCNQ complex, bisethylenetetrathiafulvalene (BEDTTTTF) -perchloric acid complex, BEDTTTF-iodine complex, TCNQ-iodine complex Charge transfer complexes represented by: biphenyl-4,4'-dicarboxylic acid, 24-di (4-thiophenylacetylinyl) -2-ethylbenzene, 24-di (4-isocyanophenylacetylinyl) -2 -Fullerene such as ethylbenzene, dendrimer, C60, C70, C76, C78, C84, 24-di (4-thiophenylethynyl) -2-ethylbenzene, 2,2 "-dihydroxy-1,1 ': 4', 1" -Terphenyl, 4,4'-biphenyldiethanal, 4,4'-biphenyldiol, 4, 4'-biphenyl diisocyanate, 24-diacetinylbenzene, diethylbiphenyl-4,4'-dicarboxylate, benzo [22-c; 3,4-c '; 5,6-c "] tris [22] dithiol -24,7-trithione, alpha-sexithiophene, tetrathiotetracene, tetraselenotetracene, tetratellurtetracene, poly (3-alkylthiophene), poly (3-thiophene-β-ethanesulfonic acid), poly (N- Examples include alkyl pyrrole) poly (3-alkyl pyrrole), poly (3,4-dialkyl pyrrole), poly (2,2′-thienyl pyrrole), poly (dibenzothiophene sulfide), and quinacridone. In addition, a compound selected from the group consisting of condensed polycyclic aromatic compounds, porphyrin derivatives, phenylvinylidene conjugated oligomers, and thiophene conjugated oligomers may be used. Further, an organic semiconductor material and an insulating polymer material may be mixed and used.

  The channel layer 23 may be formed using a vacuum vapor deposition method. For example, the channel material 23 is preferably formed using an application / printing process, for example, by dissolving the above material in an organic solvent to form an ink solution. This is because the coating / printing process can reduce the cost as compared with the vacuum deposition method and is effective in improving the throughput. Specific examples of the coating / printing process include methods such as cast coating, spin coating, spray coating, ink jet printing, letterpress printing, flexographic printing, screen printing, gravure printing, and gravure offset printing.

  Interlayer insulating layers 24 and 26 are wirings of different layers, for example, a short circuit between wirings such as between channel layer 23 and source electrode 25A and drain electrode 25B, or between source electrode 25A and drain electrode 25B and wiring 27A. Is to prevent. Examples of the material for the interlayer insulating layers 24 and 26 include insulating materials, for example, the inorganic insulating materials described in the gate insulating layer 22. However, when the wiring layer is multi-layered as in this embodiment, it is preferable to use an insulating material having a low dielectric constant in order to avoid signal delay. Specifically, it is preferable to use a photosensitive resin material, for example, an organic material such as polyimide, polyacrylate, epoxy, cresol novolac, polystyrene, polyamide, or fluorine.

  The source electrode 25 </ b> A and the drain electrode 25 </ b> B are provided on the channel layer 23 so as to be separated from each other and are electrically connected to the channel layer 23. As a material constituting the source electrode 25A and the drain electrode 25B, a metal material, a semimetal, or an inorganic semiconductor material is used. Specifically, in addition to the conductive film materials listed in the gate electrode 21A, for example, aluminum (Al), gold (Au), silver (Ag), indium tin oxide (ITO), molybdenum oxide (MoO), or these metals. An alloy etc. are mentioned. The source electrode 25A and the drain electrode 25B are composed of these single metals or alloys, and may be used as a single layer or a stack of two or more. Examples of the laminated structure include a laminated structure such as Ti / Al / Ti and Mo / Al. The wiring 27A can have the same structure as the source electrode 25A and the drain electrode 25B.

The planarization insulating layer 28 is for planarizing the surface of the substrate 11 on which the thin film transistor 20A is formed. Examples of the constituent material of the planarization insulating layer 13 include the above organic materials such as polyimide, or inorganic materials such as silicon oxide (SiO ₂ ).

  The configuration of the semiconductor layer 20 has been described above by citing the constituent elements of the thin film transistor 20A. However, the wirings formed in the same layer as the various wirings 21A, 25A, 25B, and 27A constituting the thin film transistor 20A are the same regardless of their positions. The material and the same process are used.

(Display layer configuration)
The display layer 30 includes the light emitting element 10 and is provided on the semiconductor layer 20, specifically, the planarization insulating layer 28. The light-emitting element 10 is a light-emitting element in which a pixel electrode 31 as an anode, an interelectrode insulating film 32 (partition), an organic layer 33 including a light-emitting layer, and a counter electrode 34 as a cathode are stacked in this order from the semiconductor layer 20 side. . On the counter electrode 34, a sealing substrate 36 is bonded via a sealing layer 35. The thin film transistor 20A and the light emitting element 10 are electrically connected to the pixel electrode 31 through a connection hole 28A provided in the planarization insulating layer 28.

  The pixel electrode 31 also functions as a reflective layer, and it is desirable to increase the luminous efficiency to have as high a reflectance as possible. In particular, when the pixel electrode 31 is used as an anode, the pixel electrode 31 is preferably made of a material having a high hole injection property. Examples of the pixel electrode 31 include aluminum (Al), chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tungsten (W), and silver (Ag). And a simple substance or an alloy of a metal element such as A transparent electrode having a large work function is preferably laminated on the surface of the pixel electrode 31. In the present disclosure, the pixel electrode 31 is a layer (reflection electrode film 31A) formed of a material having a reflection function such as Al and a layer (transparent) formed of a transparent conductive material such as an oxide of indium and tin (ITO). The case of having a laminated structure with the electrode film 31B) will be described as an example.

  The interelectrode insulating film 32 is for ensuring the insulation between the pixel electrode 31 and the counter electrode 34 and for making the light emitting region have a desired shape, and is made of, for example, a photosensitive resin. The interelectrode insulating film 32 is provided only around the pixel electrode 31, and a region of the pixel electrode 31 exposed from the interelectrode insulating film 32 is a light emitting region. The organic layer 33 and the counter electrode 34 are also provided on the interelectrode insulating film 32, but light emission occurs only in the light emitting region.

  For example, the organic layer 33 has a configuration in which a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are stacked in this order from the pixel electrode 31 side. These layers may be provided as necessary. The layers constituting the organic layer 33 may have different configurations depending on the emission colors of the light emitting elements 10R, 10G, and 10B, for example. The hole injection layer is a buffer layer for improving hole injection efficiency and preventing leakage. The hole transport layer is for increasing the efficiency of transporting holes to the light emitting layer. In the light emitting layer, recombination of electrons and holes occurs when an electric field is applied to generate light. The electron transport layer is for increasing the efficiency of electron transport to the light emitting layer. The electron injection layer is for increasing electron injection efficiency.

  The counter electrode 34 is made of, for example, an alloy of aluminum (Al), magnesium (Mg), calcium (Ca), or sodium (Na). Among them, an alloy of magnesium and silver (Mg—Ag alloy) is preferable because it has both conductivity in a thin film and small absorption. The ratio of magnesium and silver in the Mg—Ag alloy is not particularly limited, but it is desirable that the film thickness ratio is in the range of Mg: Ag = 20: 1 to 1: 1. The material of the counter electrode 34 may be an alloy of aluminum (Al) and lithium (Li) (Al—Li alloy).

The sealing layer 35 has, for example, a laminated structure of a layer made of silicon nitride (SiN _x ), silicon oxide (SiO _x ), metal oxide, or the like and a layer made of a thermosetting resin, an ultraviolet curable resin, or the like. . On the sealing layer 35, for example, a sealing substrate 36 provided with a light shielding film and a color filter is bonded.

(1-2. Manufacturing method)
The semiconductor layer 20 and the display layer 30 can be formed using a general method described below. First, a metal film to be the gate electrode 21A is formed on the entire surface of the substrate 11 by using, for example, a sputtering method or a vacuum evaporation method. Next, the wiring layer 21 is formed by patterning this metal film using, for example, photolithography and etching. Subsequently, the gate insulating layer 22 and the channel layer 23 are sequentially formed on the entire surface of the substrate 11 and the gate electrode 21A. Specifically, the above-described gate insulating film material, for example, a PVP (Polyvinylpyrrolidone) solution is applied over the entire surface of the substrate 11 by, for example, spin coating, and dried. Thereby, the gate insulating layer 22 is formed. Next, an organic semiconductor material such as a PXX compound solution is applied on the gate insulating layer 22. Thereafter, the applied organic semiconductor material is heated to form the channel layer 23 on the gate insulating layer 22.

  Subsequently, after an interlayer insulating layer 24 is formed on the channel layer 23, a metal film is formed on the channel layer 23 and the interlayer insulating layer 24. Specifically, for example, a Mo / Al / Mo laminated film is formed by using, for example, a sputtering method. Next, the wiring layer 25 including the source electrode 25A, the drain electrode 25B, and the wiring 25C is formed by etching using, for example, a photolithography method.

  Next, after the interlayer insulating layer 26 is formed on the interlayer insulating layer 24 and the wiring layer 25, the wiring layer 27 including the wiring 27A is formed on the wiring layer 25 and the interlayer insulating layer 26 using the same method as described above. Subsequently, a photosensitive resin such as polyimide is applied onto the interlayer insulating layer 26 and the wiring layer 27, the planarizing insulating layer 28 is patterned into a predetermined shape by exposure and development, and a connection hole 28A is formed, Bake. Next, after a metal film made of, for example, Al / ITO is formed on the planarization insulating layer 28 by, for example, sputtering, the metal film at a predetermined position is selectively removed by, for example, wet etching, and the light emitting element 10R. , 10G and 10B are formed separately.

  Next, the organic layer 33 including the light emitting layer and the counter electrode 34 are formed using, for example, a vapor deposition method, and then a sealing substrate 36 is bonded through the sealing layer 35. Finally, the display device 1 is completed by mounting an FPC for connection to an external circuit.

As shown in FIG. 1, in a high-density wiring layer in which a plurality of wirings are provided in one layer, due to a defect in the wiring layer film forming process, between wirings (for example, wirings) 25C ₁ and 25C ₂ ), the short circuit part X (short circuit part 25X) may occur. In such a case, the wiring 25C ₁ and the wiring 25C ₂ are electrically short-circuited, causing a circuit abnormality. For this reason, it is necessary to detect the short circuit part 25X by optical inspection or the like, and to restore the circuit to a normal state by cutting and removing the detected short circuit part 25X.

  As described above, the short-circuit portion X can be cut and removed using laser light. However, in order to detect the short circuit portion X, it is preferable that the circuit including the thin film transistor 20A is completed. Therefore, the presence or absence of the short-circuit portion X is inspected in a state where all the wiring layers formed in the semiconductor layer are disposed (in the present embodiment, the state where the wiring layer 27 is disposed), and the wiring layer is insulated. It is desirable to laser-process the short circuit part X in the state covered with the layer. Therefore, as in Patent Document 2 described above, the wiring layer is covered with an organic insulating layer (organic resin), and only the lower wiring layer is destroyed without destroying the organic resin by using laser light that is transmissive to the organic resin. Although the method of cutting | disconnecting can be considered, it was difficult to obtain desired insulation. This is thought to be because the melted metal is not removed by laser irradiation because the cut portion is covered with the organic insulating layer.

  On the other hand, when the lower wiring layer is cut together with the organic insulating layer using a laser beam having a wavelength that absorbs a large amount of organic resin, a short circuit is caused by using a laser beam having a certain output or more as shown in FIG. Part X is cut. However, it is confirmed that a minute leak current is generated at the cut portion, and that dielectric breakdown occurs during driving due to a display defect such as a thin line defect or, in a severe case, insufficient breakdown voltage. This is considered to occur when wrinkles generated from the organic resin constituting the organic insulating layer adhere to the bottom and side surfaces of the cut portion A during laser irradiation.

  Therefore, in this embodiment, as shown in the flowchart of FIG. 6, after forming a laminated structure of a wiring layer and an organic insulating layer (step S101), an optical inspection or the like is performed to check for the presence of the short-circuit portion X. To do. Here, when the short-circuit portion X is detected in the wiring layer, first, the short-circuit portion X is cut together with the organic insulating layer by laser irradiation (step S102-1), and then the bottom and side surfaces of the cut portion A are, for example, oxygen Half ashing is performed by exposure to plasma (step S102-2). As the half ashing conditions, for example, RF source: 1000 W, RF bias: 0 W, pressure: 1 Pa, gas: oxygen 400 sccm, processing time: 300 seconds. By this half ashing process, leakage sources such as wrinkles attached to the bottom surface or side surface of the cut portion A are removed, and the cut portion A having high insulation is obtained (step S102). Finally, as described above, the cut portion A is embedded by the planarization insulating layer 28 disposed after the wiring layer 27 is formed on the interlayer insulating layer 26 (step S103). The optical inspection may be performed after the wiring layer is formed.

  As described above, the results of half ashing after laser irradiation (Example) are shown in FIG. Compared with the case where the cut portion is formed only by laser irradiation (Comparative Example), it was confirmed that the half-ashing after laser irradiation reduces the leakage current and the dielectric breakdown rate.

As the laser beam L used in the step of forming the cut portion A, it is preferable to use a laser beam L having a high absorption in the organic material forming the interlayer insulating layer, for example, a laser beam L of 10 nm to 400 nm. The laser beam L is preferably a pulsed laser beam having a pulse width of less than 100 ns. The reason is that since the degree of thermal influence in laser processing is proportional to the square root of the pulse width, if the pulse width becomes too long, thermal adverse effects such as excessive melting occur in the vicinity of the laser light irradiation region S _1. This is because the short-circuit portion X cannot be repaired. The laser beam L may be irradiated in a single shot (shot number: 1 pulse), or may be repeatedly irradiated (shot number: multiple pulses) with a repetition frequency of less than 1 MHz. By setting the repetition frequency to less than 1 MHz, it is possible to avoid the heat accumulation effect between pulses.

  For example, the widths D1 and D2 of the laser light irradiation region S1 are adjusted so that the laser light L is applied to a part or all of the short-circuit portion 25X. At this time, the width D1 (the length D1 in the extending direction of the short circuit portion 25X) of the laser light irradiation region S1 is preferably shorter than the width D25 of the short circuit portion 25X. However, if the width D1 is extremely narrow, the light is not correctly collected due to the diffraction limit. Therefore, it is preferable that the width D1 has the lower limit of the wavelength of the laser beam L used. The same applies to the width D2 of the laser light irradiation region S1 (the length D2 in the width direction of the short-circuit portion 25X). In addition, the width D2 of the irradiation region S1 of the laser light L is preferably the same as the width D25 of the short circuit portion 25X or larger than the width D25 of the short circuit portion 25X. This is because if the width D2 of the laser light irradiation region S1 is narrower than the width D25 of the short-circuit portion 25X, an unprocessed residue is generated and the short-circuit portion 25X cannot be repaired.

  In the present embodiment, the cutting part A is formed in a straight line, but the shape of the cutting part A is not limited to this. For example, the short circuit portion 25X may be cut in a zigzag shape. In addition, the wiring layer (for example, the wiring layer 21) below the wiring layer (for example, the wiring layer 25) cut by the laser irradiation may be formed using the same material, or different materials from each other. It may be formed using.

For half ashing, for example, oxygen plasma is preferably used. This is because soot (for example, amorphous carbon) adhering to the cut portion A can be oxidized and efficiently removed, for example, as carbon dioxide (CO ₂ ). In addition to oxygen plasma, fluorine plasma or chlorine-based plasma may be used.

FIG. 9 shows average leakage currents when cutting and repairing the short circuit portion 25X of the wirings 25C ₁ and 25C ₂ only by laser irradiation (comparative example) and when half ashing is performed after laser irradiation (example). It represents. FIG. 9 also shows that the insulation of the cut portion A is improved by half ashing. The half ashing time is preferably performed until, for example, the surface of the interlayer insulating layer 26 provided with the wiring layer 25 is scraped within a certain range. FIG. 9 also shows the amount of abrasion of the resin (for example, the interlayer insulating layer 26) every half ashing time. In the embodiment, the half ashing time is set to 60 seconds, 120 seconds, 180 seconds, 240 seconds, and 300 seconds, and the average leakage current is measured. The resin surface around the cut portion A is proportional to the length of the half ashing time. The amount of shaving increases. Specifically, they are 56 nm, 107 nm, 156 nm, 204 nm, and 253 nm, respectively. It can be seen that the average leakage current at the cut portion A decreases as the amount of resin shaving increases, that is, as the depth H of the step 26A in FIG. 5 increases. From this result, it can be seen that the half ashing time is preferably longer than the time that can sufficiently remove the wrinkles adhering to the cut portion A. Note that the upper limit of the half ashing time is determined in consideration of the film thickness at which the insulating layer covering the wiring layer (here, the interlayer insulating layer 26) can maintain the insulating performance or the surface property.

  In the present embodiment, the short-circuit portion 25X that has occurred in the wiring 25C in the same layer as the source electrode 25A and the drain electrode 25B provided on the interlayer insulating layer 24 has been described as an example. The occurrence location is not particularly limited. For example, when the short-circuit portion 25X occurs in the source electrode 25A or the drain electrode 25B, the cutting and repairing can be performed in the same manner. Further, when the short-circuit portions 21X and 27X are generated in the layer of the gate electrode 21A and the layer of the wiring layer 27, it can be similarly cut and repaired. Further, the present invention can be applied to the channel layer 23 in addition to the wiring layers 21, 25 and 27.

  Further, the manufacturing yield of the display device is improved by using the above-described method for cutting and repairing the short-circuit portion, but the manufacturing yield can be further improved by devising the wiring layout of the display device.

  Specifically, high insulation can be obtained by devising plasma treatment and cutting layout in cutting and repairing between wirings arranged in the same layer as in the cutting and repairing of the short circuit part 25X. When a portion where wiring is stacked between interlayer insulating layers is cut, interlayer leakage may occur. For this reason, it is preferable that the wirings arranged in the same layer (same-layer wirings; for example, the source electrode 25A, the drain electrode 25B, and the wiring 25C) are laid out parallel to each other. Also, the wirings arranged in different layers (different layer wirings; for example, the wiring layer 21 and the wiring layer 25, and the wiring layer 25 and the wiring layer 27) should be arranged so as to be orthogonal to each other (for example, FIGS. Is preferred.

  FIG. 10 is an example of a wiring layout in which each transistor Tr1, Tr2, signal line 120A, scanning line 130A, and power supply line (Vcc, GND) in the display device 1 is constituted by three layers of wiring layers 21 and 25 and a channel layer. is there. FIG. 11 shows a wiring layout in which each transistor Tr1, Tr2, signal line 120A, scanning line 130A and power supply line (Vcc, GND) in the display device 1 is composed of four layers of wiring layers 21, 25, 27 and a channel layer 23. It is an example.

As described above, line defects and bright spots are serious defects that greatly impair the appearance of the display device. For example, when the signal line 120A and the power supply line (GND) are short-circuited, a line defect defect occurs. In order to remedy this defect, for example, the short circuit portion X between the signal line 120A and GND is cut (cutting point A), or the GND before and after the short circuit portion X is cut (cutting point B) and a signal is output together with the short circuit portion X. A method can be considered in which a part of the line 120A is used, and the corresponding light-emitting element 10W is made into an electrically floating state to be blackened. These cut points A, B are respectively diagrams 3, O-O line in 11 (cut part A), a line P-P, Q-Q line (cut part B).

In addition, when making a black spot, a contact hole to which a common potential line such as GND is connected and a contact hole to connect the pixel driving circuit 140 and the light emitting element 10W as an anode or a cathode ( ■ in FIGS. 10 and 11) Must be disconnected from each destination. As a method of separating the contact hole, as shown in FIGS. 13A and 13B, the contact region is irradiated with laser light to form an opening P (FIG. 13A), and then an insulating material such as an organic resin is formed in the opening P. May be embedded (FIG. 13B). When the opening P is formed by laser light as shown in FIG. 13A, if the wiring layers 21, 25, 27 and the channel layer 23 are present in the lower layer of the contact hole, an interlayer short circuit occurs. Separate the wiring from the scanning line 120A. Further, in order to avoid an interlayer short circuit, a layout in which at least one of the wiring layers 21, 25, 27 and the channel layer 23 does not exist at the cut portion is provided for the part separated from the scanning line 120 A and the contact hole of the common potential line. . As a result, the light emitting element 10W becomes electrically floating and becomes a black spot.

  In this way, by laying out the same-layer wirings in parallel with each other and the different-layer wirings in orthogonal to each other, a region where the short-circuit portion X generated in the wiring in each layer can be cut and repaired is expanded. In addition, the layout is made so that at least one of the wiring layer (wiring layer 21 and wiring layer 25) and the channel layer 23 is not disposed under the common potential line, so that the OO line, PP line, Q- In addition to the Q line, the RR line, the SS line, and the like can be cut. That is, an area in which the short-circuit portion X generated in the wiring of each layer can be cut and repaired is expanded in almost the entire display area 110A (and the peripheral area 110B), and the manufacturing yield can be further improved.

(1-3. Action and effect)
As described above, in the display device 1 and the manufacturing method thereof according to the present embodiment, after irradiating the laser beam L to a predetermined position of the wiring layer in which the organic insulating layers are laminated, for example, the wiring 25C and the interlayer insulating layer 26, The peripheral region including the irradiation region S1 of the laser beam L is half-ashed. That is, for example, by applying laser light L and half ashing to the short-circuited portion 25X generated in the two adjacent wirings 25C ₁ and 25C ₂ , the short-circuited portion 25X is electrically disconnected, and the wiring from the interlayer insulating layer 26 is performed. A cut portion A penetrating through 25C ₁ and 25C ₂ is formed. Thereby, it becomes possible to electrically cut an arbitrary position of the wiring layer covered with the organic insulating layer.

  As described above, in this embodiment, after the laser beam L is irradiated to a predetermined position of the wiring layer, the peripheral region including the irradiation region S1 of the laser beam L is subjected to half ashing. It becomes possible to electrically cut the laminated wiring layer. Therefore, it is possible to provide the display device 1 that achieves both display quality and manufacturing yield.

  Hereinafter, modifications of the above embodiment will be described. In addition, the same code | symbol is attached | subjected about the component same as the said embodiment, and the description is abbreviate | omitted.

<2. Modification>
FIG. 14 illustrates a cross-sectional configuration of a display device (display device 1A) according to a modification of the above embodiment. FIG. 15 shows the flow of the wiring layer cutting process in this modification. In the present modification, a laser irradiation process for cutting and repairing a predetermined position of the wiring layer of the display device 1A, for example, the short circuit portion 25X of the wiring 25C (wirings 25C ₁ and 25C ₂ ), is performed twice (first laser irradiation and The second laser irradiation is different from the above embodiment.

  In this modification, half ashing is performed after the laser beam L1 and the laser beam L2 are continuously irradiated to the short-circuit portion 25X as described above. Specifically, as shown in FIG. 16A, after the laser beam L1 is irradiated to the short-circuit portion 25X (step S202-1) to form the cut portion B1, the laser beam L2 having a narrower irradiation width than the laser beam L1. Is irradiated to the bottom surface of the cutting part B1 and the laser irradiation start point Is and the end point Ie (step S202-2). Thereafter, the bottom and side surfaces of the cutting part B1 are exposed to oxygen plasma, for example, and half ashing is performed (step S202-3), whereby the cutting part B having high insulation is formed.

  FIG. 17 shows the relationship between the half ashing time and the average leakage current in the cut portion A (Example 1) in the above embodiment and the cut portion B (Example 2) in the present modified example in which the two laser irradiation steps are performed. It is a characteristic view showing the relationship. As can be seen from FIG. 17, in the cutting part B in this modification, even if the half ashing time is shortened in half, the average leakage current is reduced, that is, the withstand voltage performance is ensured. This is presumably because the metal powder constituting the short-circuited portion 25X remaining at the bottom of the cut portion B1 or scattered at the laser irradiation start point Is and the end point Ie by the first laser irradiation was removed by the second laser irradiation. Note that the width D3 of the irradiation region S2 of the laser light L2 is preferably shorter than the width D1 of the irradiation region S1.

  In this manner, the half ashing time is shortened by performing the laser irradiation process twice (first laser irradiation and second laser irradiation) on a predetermined position (for example, the short circuit portion 25X of the wiring 25C) of the wiring layer of the display device 1A. It becomes possible to do. Further, the amount of abrasion of the insulating layer (for example, the interlayer insulating layer 26) provided with the wiring layer can be suppressed. As a result, the utilization efficiency of the material of the insulating layer can be improved, and a display device with good appearance quality in which the surface property of the insulating layer is maintained can be provided.

<3. Application example>
The display devices 1 and 1A described in the above embodiments and modifications can be suitably used as, for example, the following electronic devices.

(Application example 1)
FIG. 18A shows the appearance of the smartphone from the front side, and FIG. 18B shows the back side. This smartphone includes, for example, a display unit 610 (display device 1), a non-display unit (housing) 620, and an operation unit 630. The operation unit 630 may be provided on the front surface of the non-display unit 620 as shown in FIG. 18A, or may be provided on the upper surface as shown in FIG. 18B.

(Application example 2)
FIG. 19 illustrates an appearance of a television device according to Application Example 2 . This television device has, for example, a video display screen unit 200 including a front panel 210 and a filter glass 220, and the video display screen 200 corresponds to the display device.

(Application example 3)
20A shows the appearance of the digital camera according to Application Example 3 from the front side, and FIG. 20B shows the back side. This digital camera has, for example, a flash light emitting unit 310, a display unit 320 as the display device, a menu switch 330, and a shutter button 340.

(Application example 4)
FIG. 21 illustrates an appearance of a notebook personal computer according to Application Example 4 . The notebook personal computer includes, for example, a main body 410, a keyboard 420 for inputting characters and the like, and a display unit 430 as the display device.

(Application example 5 )
FIG. 22 illustrates an appearance of a video camera according to Application Example 5 . This video camera has, for example, a main body 510, a subject photographing lens 520 provided on the front side surface of the main body 510, a start / stop switch 530 during photographing, and a display 540 as the display device. Yes.

(Application example 6 )
FIG. 23A illustrates a front view, a left side view, a right side view, a top view, and a bottom view of the cellular phone according to Application Example 6 in a closed state. FIG. 23B shows a front view and a side view of the mobile phone in an opened state. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. The display 740 or the sub display 750 corresponds to the display device.

  As described above, the embodiments, modifications, and application examples have been described, but the present disclosure is not limited to these embodiments and the like, and various modifications are possible. For example, the material and thickness of each layer described in the above embodiment and the like, or the film formation method and film formation conditions are not limited, and other materials and thicknesses may be used. It is good also as film | membrane conditions.

In addition, this technique can also take the following structures.
(1) Having a first insulating layer made of an organic material on two adjacent first wirings, and a recess penetrating in a stacking direction from the first insulating layer to the first wiring between the two first wirings. And a second insulating layer provided in the recess and on the stacked structure.
(2) A second wiring is provided between the first insulating layer and the second insulating layer, and the first insulating layer has a step between the second wiring and other regions. The display device according to 1).
(3) The display device according to (1) or (2), wherein the first wiring is any one of a gate electrode, a pair of source / drain electrodes, and a plurality of metal layers constituting a multilayer wiring layer. .
(4) The multilayer wiring layer includes an interlayer insulating layer made of an organic material, and the plurality of metal layers are respectively disposed so as to be orthogonal to the interlayer insulating layer. Display device.
(5) The display device according to any one of (1) to (4), wherein the concave portion is formed in a short-circuit portion between the two adjacent first wirings.
(6) The display device according to any one of (1) to (5), wherein the second insulating layer is made of an organic material.
(7) After forming a laminated structure having two adjacent first wirings and a first insulating layer made of an organic material in this order, a laser is provided from the first insulating layer side to the short-circuit portion between the two first wirings. Irradiating light, forming a recess penetrating in the stacking direction from the first insulating layer to the first wiring, half ashing a peripheral region including the laser light irradiation surface, and the half ashing step. And a step of forming a second insulating layer in the recess and on the laminated structure.
(8) The display device according to (7), wherein after forming the recess, the bottom surface of the recess, the laser irradiation start point, and the end point are irradiated with laser light having a narrower irradiation width than the laser light.
(9) The display device according to (7) or (8), wherein plasma processing is performed in the half ashing step.
(10) The display device according to (9), wherein oxygen is used in the plasma treatment.
(11) The display device according to any one of (7) to (10), wherein the laser beam has a wavelength of 10 nm to 400 nm.
(12) A display device is provided, and the display device includes a first insulating layer made of an organic material on two adjacent first wirings, and the first insulating layer is connected to the first insulating layer between the two first wirings. An electronic apparatus comprising: a laminated structure having a concave portion penetrating in the lamination direction up to one wiring; and a second insulating layer provided in the concave portion and on the laminated structure.

  DESCRIPTION OF SYMBOLS 1,1A ... Display apparatus, 2 ... Pixel, 10 ... Light emitting element, 11 ... Substrate, 20A ... Thin film transistor, 21, 25, 27 ... Wiring layer, 21A ... Gate electrode, 22 ... Gate insulating film, 23 ... Channel layer, 24 , 26 ... interlayer insulating layer, 25A ... source electrode, 25B ... drain electrode layer, 25C, 27A ... wiring, 27 ... wiring layer, short circuit part ... X, 25X, cutting part ... A, B.

Claims (10)

A laminated structure having a first insulating layer made of an organic material on two adjacent first wirings and having a recess penetrating in a laminating direction from the first insulating layer to the first wiring between the two first wirings. When,
A second insulating layer provided in the recess and on the laminated structure ,
A display device having a second wiring between the first insulating layer and the second insulating layer, wherein the first insulating layer has a step between the second wiring and other regions .   The display device according to claim 1, wherein the first wiring is any one of a gate electrode, a pair of source / drain electrodes, and a plurality of metal layers constituting a multilayer wiring layer. The first wiring is one of a plurality of metal layers constituting the multilayer wiring layer,
The display device according to claim 2 , wherein the multilayer wiring layer has an interlayer insulating layer, and each of the plurality of metal layers is disposed so as to be orthogonal to the interlayer insulating layer.   The display device according to claim 1, wherein the second insulating layer is made of an organic material. After forming a laminated structure having two adjacent first wirings and a first insulating layer made of an organic material in this order, the short-circuit portion between the two first wirings is irradiated with laser light from the first insulating layer side. Forming a recess penetrating in the stacking direction from the first insulating layer to the first wiring;
Half ashing a peripheral region including the laser light irradiation surface;
And a step of forming a second insulating layer in the recess and on the stacked structure after the half ashing step. The method for manufacturing a display device according to claim 5 , wherein after forming the recess, the bottom surface of the recess, the laser irradiation start point, and the end point are irradiated with laser light having a narrower irradiation width than the laser light. The method for manufacturing a display device according to claim 5 , wherein plasma processing is performed in the half ashing step. The method for manufacturing a display device according to claim 7 , wherein oxygen is used in the plasma treatment. The method for manufacturing a display device according to claim 5 , wherein a wavelength of the laser light is 10 nm or more and 400 nm or less. A display device,
The display device
A laminated structure having a first insulating layer made of an organic material on two adjacent first wirings and having a recess penetrating in a laminating direction from the first insulating layer to the first wiring between the two first wirings. When,
Have a second insulating layer provided on the recess and the laminated structure,
An electronic apparatus having a second wiring between the first insulating layer and the second insulating layer, wherein the first insulating layer has a step between the second wiring and a region other than the second wiring .

Images