JP6013743B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP6013743B2
JP6013743B2 JP2012040148A JP2012040148A JP6013743B2 JP 6013743 B2 JP6013743 B2 JP 6013743B2 JP 2012040148 A JP2012040148 A JP 2012040148A JP 2012040148 A JP2012040148 A JP 2012040148A JP 6013743 B2 JP6013743 B2 JP 6013743B2
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semiconductor layer
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大士 古家
大士 古家
正信 東
正信 東
只友 一行
一行 只友
成仁 岡田
成仁 岡田
啓輔 山根
啓輔 山根
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NATIONAL UNIVERSITY CORPORATION YAMAGUCHI UNIVERSITY
Tokuyama Corp
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Description

本発明は、半導体装置及びその製造方法、並びに自立基板の製造方法に関する。   The present invention relates to a semiconductor device, a method for manufacturing the same, and a method for manufacturing a free-standing substrate.

基板表面に微細凹凸を形成した加工基板の上に半導体層を形成する半導体装置の製造方法が知られている(例えば特許文献1)。   A method for manufacturing a semiconductor device is known in which a semiconductor layer is formed on a processed substrate having fine irregularities formed on the surface of the substrate (for example, Patent Document 1).

また、主面がc面であるGaN(以下「c面GaN」等のようにも表記する。)は、膜厚が10-1μmのオーダーから102μmのオーダーに渡って、膜厚が厚くなるに従って欠陥密度が小さくなることが知られている(例えば非特許文献1)。 GaN whose principal surface is c-plane (hereinafter also referred to as “c-plane GaN”) has a film thickness ranging from the order of 10 −1 μm to the order of 10 2 μm. It is known that the defect density decreases as the thickness increases (for example, Non-Patent Document 1).

ところが、c面GaNは、c面が極性面であることから、発光素子に用いた場合、自発分極やピエゾ分極のために発光効率が低く、そのため当該用途に用いるのは不利であると考えられている。   However, since the c-plane GaN is a c-polar plane, the c-plane GaN has a low luminous efficiency due to spontaneous polarization and piezo-polarization when used in a light-emitting element, and is therefore considered disadvantageous for use in this application. ing.

WO2010/023846A1WO2010 / 023846A1

S.K.Mathis et al. Journal of Crystal 231(2001)371-390S.K.Mathis et al. Journal of Crystal 231 (2001) 371-390

一方、サファイア基板の加工基板上に結晶成長した主面がc面以外である非極性面又は半極性面のGaNでは、少なくとも10μmのオーダーまでは、膜厚と欠陥密度との相関関係はなく、c面GaNのような膜厚が厚くなるのに伴う欠陥密度の低減効果は見られない。   On the other hand, in the case of GaN having a nonpolar or semipolar surface whose principal surface is crystal plane grown on the processed substrate of the sapphire substrate, there is no correlation between the film thickness and the defect density up to the order of 10 μm, There is no effect of reducing the defect density as the film thickness of c-plane GaN increases.

本発明の課題は、主面が非極性面又は半極性面であり且つ表面の欠陥密度が小さいIII-V族化合物半導体層を得ることである。   An object of the present invention is to obtain a III-V group compound semiconductor layer whose main surface is a nonpolar surface or a semipolar surface and whose surface defect density is small.

本発明は、基板表面が、基板主面部分と、該基板主面部分とは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分と、を有するベース基板を用い、該ベース基板の該基板表面における該結晶成長面部分を起点として該III-V族化合物半導体を層状に結晶成長させることにより主面が非極性面又は半極性面であるIII-V族化合物半導体層を形成する半導体層形成工程を有する半導体装置の製造方法であって、
上記半導体層形成工程において、III-V族化合物半導体層を厚さ00μm以上に形成し、そして、得られるIII-V族化合物半導体層の表面の欠陥密度が1×10 /cm 以下である
The present invention uses a base substrate having a substrate surface having a substrate main surface portion and a crystal growth surface portion capable of crystal growth of a III-V compound semiconductor having a different plane orientation from the substrate main surface portion. A III-V group compound semiconductor whose principal surface is a nonpolar plane or a semipolar plane by growing the group III-V compound semiconductor in layers from the crystal growth plane portion on the substrate surface of the base substrate A method of manufacturing a semiconductor device including a semiconductor layer forming step of forming a layer,
In the semiconductor layer forming step is performed to form the above thickness 3 00Myuemu group III-V compound semiconductor layer, and the defect density of the surface of the resulting group III-V compound semiconductor layer is in 1 × 10 7 / cm 2 or less There is .

本発明によれば、III-V族化合物半導体層を厚さ100μm以上に形成することにより、主面が非極性面又は半極性面であり且つ表面の欠陥密度が小さいIII-V族化合物半導体層を得ることができる。   According to the present invention, the III-V group compound semiconductor layer is formed to a thickness of 100 μm or more, whereby the main surface is a nonpolar plane or a semipolar plane and the surface defect density is small. Can be obtained.

実施形態に係る半導体装置の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor device which concerns on embodiment. (a)及び(b)は加工基板の断面図である。(A) And (b) is sectional drawing of a process board | substrate. GaN層の厚さと欠陥密度との関係を示すグラフである。It is a graph which shows the relationship between the thickness of a GaN layer, and defect density.

以下、実施形態について図面に基づいて詳細に説明する。   Hereinafter, embodiments will be described in detail based on the drawings.

本実施形態に係る半導体装置の製造方法は、図1に示すように、加工基板のベース基板10を用い、その上にIII-V族化合物半導体を層状に結晶成長させることにより主面が非極性面又は半極性面であるIII-V族化合物半導体層20(以下「半導体層」という。)を形成する半導体層形成工程を有する。   As shown in FIG. 1, the manufacturing method of the semiconductor device according to the present embodiment uses a base substrate 10 as a processed substrate, and a III-V group compound semiconductor is crystal-grown in a layer form on the base substrate 10 to make the main surface nonpolar. A semiconductor layer forming step of forming a group III-V compound semiconductor layer 20 (hereinafter referred to as “semiconductor layer”) which is a plane or semipolar plane.

ここで、ベース基板10としては、特に限定されるものではなく、例えば、サファイア基板(Al23のコランダム構造の単結晶の基板)、ZnO基板、SiC基板等が挙げられる。これらのうちサファイア基板が好ましい。 Here, the base substrate 10 is not particularly limited, and examples thereof include a sapphire substrate (a single crystal substrate having a corundum structure of Al 2 O 3 ), a ZnO substrate, and a SiC substrate. Of these, sapphire substrates are preferred.

ベース基板10は、加工基板であるが、例えば、図2(a)に示すような基板表面11にエッチング等により微細凹凸を形成した加工基板等が挙げられる。基板表面11は、基板主面部分11aと、その基板主面部分11aとは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分11bとを有する。ベース基板10は、図2(b)に示すように結晶成長面部分11b以外がSiO2等からなる結晶成長阻害層12で被覆されたものであってもよい。 The base substrate 10 is a processed substrate, and examples thereof include a processed substrate in which fine irregularities are formed on the substrate surface 11 as shown in FIG. 2A by etching or the like. The substrate surface 11 has a substrate main surface portion 11a and a crystal growth surface portion 11b that has a different plane orientation from that of the substrate main surface portion 11a and is capable of crystal growth of a group III-V compound semiconductor. As shown in FIG. 2B, the base substrate 10 may be one in which a portion other than the crystal growth surface portion 11b is covered with a crystal growth inhibition layer 12 made of SiO 2 or the like.

基板主面部分11aは、a面<{11−20}面>、c面<{0001}面>、m面<{1−100}面>、及びr面<{1−102}面>のいずれであってもよく、また、他の面方位の結晶面であってもよい。結晶成長面部分11bは、a面<{11−20}面>、c面<{0001}面>、m面<{1−100}面>、及びr面<{1−102}面>のいずれであってもよく、また、他の面方位の結晶面であってもよい。ベース基板10の基板表面11における結晶成長面部分11bを起点としてIII-V族化合物半導体を結晶成長させるが、そのIII-V族化合物半導体におけるIII族元素としてはアルミニウム(Al)、ガリウム(Ga)、インジウム(In)が挙げられ、V族元素としては窒素(N)、リン(P)、ヒ素(As)、アンチモン(Sb)が挙げられる。III-V族化合物半導体としては、典型的にはIII族窒化物半導体が挙げられ、具体的には、例えば、GaN、AlGaN、InGaN、InAlGaN、InAlN、InN等が挙げられる。これらのうちGaNが好ましい。   Substrate main surface portion 11a includes a-plane <{11-20} plane>, c-plane <{0001} plane>, m-plane <{1-100} plane>, and r-plane <{1-102} plane>. Any of them may be used, and the crystal plane may have another plane orientation. The crystal growth surface portion 11b includes an a plane <{11-20} plane>, a c plane <{0001} plane>, an m plane <{1-100} plane>, and an r plane <{1-102} plane>. Any of them may be used, and the crystal plane may have another plane orientation. A group III-V compound semiconductor is grown from the crystal growth surface portion 11b on the substrate surface 11 of the base substrate 10, and the group III elements in the group III-V compound semiconductor are aluminum (Al) and gallium (Ga). Indium (In), group V elements include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb). The group III-V compound semiconductor typically includes a group III nitride semiconductor, and specifically includes GaN, AlGaN, InGaN, InAlGaN, InAlN, InN, and the like. Of these, GaN is preferred.

半導体層20の主面は、非極性面又は半極性面であり、a面<{11−20}面>、m面<{1−100}面>、及びr面<{1−102}面>のいずれであってもよく、また、{10−11}面、{11−22}面、{20−21}面等の他の面方位の結晶面であってもよい。これらのうち半導体層20を厚さ100μm以上にした際の転位低減効果が著しいことから半極性面の{10−11}面が特に好ましい。ベース基板10上へのIII-V族化合物半導体の結晶成長はエピタキシャル成長であることが好ましい。   The main surface of the semiconductor layer 20 is a nonpolar plane or a semipolar plane, and is a plane <{11-20} plane>, m plane <{1-100} plane>, and r plane <{1-102} plane. >, Or a crystal plane of another plane orientation such as {10-11} plane, {11-22} plane, {20-21} plane. Of these, the {10-11} plane of the semipolar plane is particularly preferable because the effect of reducing dislocation when the semiconductor layer 20 is 100 μm or more in thickness is remarkable. The crystal growth of the III-V compound semiconductor on the base substrate 10 is preferably epitaxial growth.

結晶成長手段としては、例えば、ハイドライド気相成長法(HVPE法)、有機金属化学気相成長法(MOCVD法)、分子線エピタキシャル法(MBE法)等の気相成長手段が挙げられる。高速で厚膜の高品質な半導体層20が形成可能であるという観点からはハイドライド気相成長法が好ましい。結晶成長は、単一手段で行ってもよく、また、複数の手段を組み合わせて行ってもよい。例えば、まず、ベース基板10上に、有機金属化学気相成長法により、III-V族化合物半導体を結晶成長させて厚さの薄い半導体層を形成したテンプレートを作製し、そのテンプレートを用いて結晶成長速度が速いハイドライド気相成長法によりIII-V族化合物半導体を結晶成長させて半導体層20を形成することが考えられる。   Examples of the crystal growth means include vapor phase growth means such as hydride vapor phase epitaxy (HVPE), metal organic chemical vapor deposition (MOCVD), and molecular beam epitaxy (MBE). From the viewpoint that a high-quality semiconductor layer 20 having a high thickness can be formed at high speed, a hydride vapor phase growth method is preferable. Crystal growth may be performed by a single means or a combination of a plurality of means. For example, first, a template in which a thin semiconductor layer is formed by growing a group III-V compound semiconductor on the base substrate 10 by metal organic chemical vapor deposition is manufactured. It can be considered that the semiconductor layer 20 is formed by crystal growth of a group III-V compound semiconductor by a hydride vapor phase growth method having a high growth rate.

結晶成長条件としては、例えば、ハイドライド気相成長法によりベース基板10としてのサファイア基板上にIII-V族化合物半導体のGaNを結晶成長させる場合、反応容器内の圧力は10〜120kPa、及びサファイア基板の温度は900〜1150℃であり、また、キャリアガスには水素ガスや窒素ガス或いはそれらの混合ガスを用い、さらに、GaClを形成するための塩化水素ガス、及び窒素源のアンモニアガスの流量比(NH3/HCl)は2〜100である。なお、半導体層20を形成する前に、有機金属化学気相成長法等によりベース基板10の表面に厚さ20〜30nm程度のIII-V族化合物半導体からなる低温バッファ層及びまたは1〜10μmのIII-V族化合物半導体を設けてもよい。 As the crystal growth conditions, for example, when GaN of a III-V group compound semiconductor is grown on a sapphire substrate as the base substrate 10 by hydride vapor phase epitaxy, the pressure in the reaction vessel is 10 to 120 kPa, and the sapphire substrate The temperature of the gas is 900 to 1150 ° C., and hydrogen gas, nitrogen gas or a mixed gas thereof is used as the carrier gas, and the flow rate ratio of hydrogen chloride gas for forming GaCl and ammonia gas of the nitrogen source (NH 3 / HCl) is 2 to 100. Before forming the semiconductor layer 20, a low-temperature buffer layer made of a group III-V compound semiconductor having a thickness of about 20 to 30 nm and / or 1 to 10 μm is formed on the surface of the base substrate 10 by metal organic chemical vapor deposition or the like. A III-V compound semiconductor may be provided.

そして、本実施形態に係る半導体装置の製造方法では、その半導体層形成工程において、半導体層20を厚さ100μm以上に形成する。このように半導体層20を厚さ100μm以上に形成することにより、主面が非極性面又は半極性面であり且つ表面の欠陥密度が小さい半導体層20を得ることができる。なお、半導体層20を厚さとは、ベース基板10の表面の微細凹凸における凸部の上端面から半導体層20表面までの寸法である。   And in the manufacturing method of the semiconductor device concerning this embodiment, in the semiconductor layer formation process, semiconductor layer 20 is formed in thickness of 100 micrometers or more. Thus, by forming the semiconductor layer 20 with a thickness of 100 μm or more, it is possible to obtain the semiconductor layer 20 whose main surface is a nonpolar surface or semipolar surface and whose surface defect density is small. The thickness of the semiconductor layer 20 is a dimension from the upper end surface of the convex portion in the fine unevenness on the surface of the base substrate 10 to the surface of the semiconductor layer 20.

上記作用効果の観点からは、III-V族化合物半導体を結晶成長させて形成する半導体層20の厚さは好ましくは300μm以上であり、より好ましくは400μm以上である。なお、半導体層20の厚さの上限は特に限定されないが、例えば10cm以下である。   From the viewpoint of the above effects, the thickness of the semiconductor layer 20 formed by crystal growth of a group III-V compound semiconductor is preferably 300 μm or more, more preferably 400 μm or more. In addition, although the upper limit of the thickness of the semiconductor layer 20 is not specifically limited, For example, it is 10 cm or less.

得られる半導体層20の欠陥密度は、好ましくは1×107/cm2以下であり、より好ましくは1×106/cm2以下である。欠陥密度はカソードルミネッセンスによる暗点測定やKHOエッチングによるピット密度測定により算出できる。 The defect density of the obtained semiconductor layer 20 is preferably 1 × 10 7 / cm 2 or less, more preferably 1 × 10 6 / cm 2 or less. The defect density can be calculated by dark spot measurement by cathodoluminescence or pit density measurement by KHO etching.

本実施形態に係る半導体装置の製造方法では、ベース基板10上に形成した半導体層20の上に各種の機能層を設けて半導体装置を製造してもよい。この場合、半導体装置として、基板表面11が、基板主面部分11aと、基板主面部分11aとは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分11bとを有するベース基板10と、ベース基板10の基板表面11における結晶成長面部分11bを起点としてIII-V族化合物半導体が層状に結晶成長して形成された主面が非極性面又は半極性面である半導体層20とを備え、半導体層20の厚さが100μm以上である構成のものを得ることができる。   In the method for manufacturing a semiconductor device according to this embodiment, the semiconductor device may be manufactured by providing various functional layers on the semiconductor layer 20 formed on the base substrate 10. In this case, as a semiconductor device, the substrate surface 11 includes a substrate main surface portion 11a and a crystal growth surface portion 11b capable of crystal growth of a group III-V compound semiconductor while having a different plane orientation from the substrate main surface portion 11a. And a main surface formed by crystal growth of a group III-V compound semiconductor in layers from the crystal growth surface portion 11b on the substrate surface 11 of the base substrate 10 is a nonpolar surface or a semipolar surface. The semiconductor layer 20 is provided, and the semiconductor layer 20 having a thickness of 100 μm or more can be obtained.

また、本実施形態に係る半導体装置の製造方法では、半導体層20の全部又は一部をベース基板10から分離して自立基板を製造し(基板分離工程)、その自立基板上に各種の機能層を設けて半導体装置を製造してもよい。   In the method for manufacturing a semiconductor device according to the present embodiment, all or part of the semiconductor layer 20 is separated from the base substrate 10 to manufacture a self-supporting substrate (substrate separation process), and various functional layers are formed on the self-supporting substrate. May be provided to manufacture a semiconductor device.

本実施形態で製造される半導体装置としては、欠陥密度の小さい半導体層20が得られ、従って、その上に発光層を設ければ高い発光効率を得ることができることから、特に半導体レーザや発光ダイオード等の半導体発光素子が好適である。   As the semiconductor device manufactured in the present embodiment, the semiconductor layer 20 with a low defect density is obtained. Therefore, if a light emitting layer is provided on the semiconductor layer, high light emission efficiency can be obtained. A semiconductor light emitting device such as is suitable.

(半導体層の形成)
r面サファイア基板、n面サファイア基板({11−23}面サファイア基板)、{22−43}面サファイア基板の表面に、c軸に垂直で、且つ側面にc面近傍の結晶成長面部分が露出するようにストライプ状に溝加工を施すと共に、基板主面部分をSiO2からなる結晶成長阻害層で被覆した加工基板を作製した。溝間の凸部幅及び溝幅をいずれも2μmに形成し、また、溝深さを1μmに形成した。
(Formation of semiconductor layer)
On the surface of the r-plane sapphire substrate, n-plane sapphire substrate ({11-23} plane sapphire substrate), {22-43} plane sapphire substrate, there is a crystal growth surface portion perpendicular to the c-axis and near the c-plane on the side surface. A processed substrate was produced in which grooves were formed in stripes so as to be exposed, and the main surface portion of the substrate was coated with a crystal growth inhibiting layer made of SiO 2 . The protrusion width and groove width between the grooves were both 2 μm, and the groove depth was 1 μm.

上記加工基板に、有機金属化学気相成長法により、結晶成長面部分を基点としてGaNを結晶成長させ、主面が{11−22}面である厚さ5μmのGaN層を形成したGaNテンプレート、主面が{10−11}面である厚さ5μmのGaN層を形成したGaNテンプレート、及び主面が{20−21}面である厚さ8μmのGaN層を形成したGaNテンプレートをそれぞれ作製した。これらのGaNテンプレートのGaN層表面の欠陥密度は約2.0〜3.0×108/cm2であった。 A GaN template in which a GaN layer having a main surface of {11-22} plane and a GaN layer having a thickness of 5 μm is formed on the processed substrate by metalorganic chemical vapor deposition using a crystal growth surface portion as a base point; A GaN template in which a GaN layer having a thickness of 5 μm whose main surface is a {10-11} plane and a GaN template in which a GaN layer having a thickness of 8 μm whose main surface is a {20-21} plane were formed were prepared. . The defect density on the surface of the GaN layer of these GaN templates was about 2.0 to 3.0 × 10 8 / cm 2 .

そして、各GaNテンプレートについて、GaNを結晶成長させて厚さを変えてGaN層を形成し、それぞれについて表面の欠陥密度を測定した。   And about each GaN template, GaN was crystal-grown and thickness was changed, the GaN layer was formed, and the defect density of the surface was measured about each.

なお、GaN層の形成は以下のようにして行った。   The GaN layer was formed as follows.

まず、GaNテンプレートを、縦型ハイドライド気相成長(HVPE)装置(FH702−F型)の反応炉に、GaN層がガスの上流を向くように炭素製試料固定台にセットした。次いで、炉内圧力を101.3kPaに保持して基板領域を昇温した。その後、基板温度が500℃を超えた時点でアンモニアガスの供給を開始し、基板温度が結晶成長温度の1040〜1100℃に達した後、その状態を25分間保持して基板温度を安定させた。続いて、水素ガス及び窒素ガスをキャリアガスとして供給しながら、塩化水素ガスを0.8slm及びアンモニアガスを8〜24slmのそれぞれの流量(流量比=10〜30)で供給してGaNの結晶成長を行った。その後、塩化水素ガスの供給を止め、アンモニアガスを供給しながら自然冷却し、基板温度が200℃以下になった後にアンモニアガスの供給を止め、しかる後、反応炉からGaN層が形成された基板を取り出した。   First, the GaN template was set on a carbon sample fixing base in a reaction furnace of a vertical hydride vapor phase epitaxy (HVPE) apparatus (FH702-F type) so that the GaN layer faced upstream of the gas. Next, the substrate region was heated while maintaining the furnace pressure at 101.3 kPa. Thereafter, supply of ammonia gas was started when the substrate temperature exceeded 500 ° C., and after the substrate temperature reached 1040 to 1100 ° C. of the crystal growth temperature, the state was maintained for 25 minutes to stabilize the substrate temperature. . Subsequently, while supplying hydrogen gas and nitrogen gas as a carrier gas, hydrogen chloride gas is supplied at a flow rate of 0.8 slm and ammonia gas at a flow rate of 8 to 24 slm (flow rate ratio: 10 to 30) to grow GaN crystals. Went. Thereafter, the supply of hydrogen chloride gas is stopped, the substrate is naturally cooled while supplying ammonia gas, the supply of ammonia gas is stopped after the substrate temperature becomes 200 ° C. or less, and then the substrate on which the GaN layer is formed from the reactor. Was taken out.

また、同様に、サファイア基板上に厚さを変えてc面GaN層を形成し、それぞれについて表面の欠陥密度を測定した。   Similarly, c-plane GaN layers were formed on the sapphire substrate with different thicknesses, and the surface defect density was measured for each.

(欠陥密度評価)
得られたGaN層について、走査型電子顕微鏡/カソードルミネッセンス(SEM・CL)装置を用いて、GaN層表面の観察を行った。このときの加速電圧は5kV、観察範囲は20μm×20μmとし、観察範囲内に観察された暗点の総数から欠陥密度を算出した。
(Defect density evaluation)
About the obtained GaN layer, the GaN layer surface was observed using the scanning electron microscope / cathode luminescence (SEM * CL) apparatus. At this time, the acceleration voltage was 5 kV, the observation range was 20 μm × 20 μm, and the defect density was calculated from the total number of dark spots observed in the observation range.

(半導体層の厚さと欠陥密度との関係)
図3はGaN層の厚さと欠陥密度との関係を示す。
(Relationship between semiconductor layer thickness and defect density)
FIG. 3 shows the relationship between the thickness of the GaN layer and the defect density.

図3によれば、極性面のc面GaNでは、膜厚1μmのオーダーから100μmのオーダーに渡って、膜厚が厚くなるに従って欠陥密度が小さくなっていることが分かる。これに対し、半極性面の{11−22}面GaN、{10−11}面GaN、及び{20−21}面GaNでは、膜厚1μmのオーダーから10μmのオーダーにおいては、欠陥密度の膜厚依存性は認められないものの、膜厚100μmのオーダーになると、膜厚が厚くなるに従って欠陥密度が小さくなっていることが分かる。特に、{10−11}面GaNでは、膜厚100μmのオーダーにおける膜厚増加に伴う著しい欠陥密度の減少効果が認められる。   According to FIG. 3, it can be seen that in the c-plane GaN of the polar plane, the defect density decreases as the film thickness increases from the order of 1 μm to 100 μm. On the other hand, in the {11-22} plane GaN, {10-11} plane GaN, and {20-21} plane GaN, which are semipolar planes, a film having a defect density in the order of 1 μm to 10 μm. Although no thickness dependency is observed, it can be seen that when the film thickness is on the order of 100 μm, the defect density decreases as the film thickness increases. In particular, in {10-11} plane GaN, a remarkable effect of reducing the defect density with an increase in film thickness in the order of 100 μm is observed.

本発明は、半導体装置及びその製造方法、並びに自立基板の製造方法について有用である。   The present invention is useful for a semiconductor device, a method for manufacturing the same, and a method for manufacturing a free-standing substrate.

10 ベース基板
11 基板表面
11a 基板主面部分
11b 結晶成長面部分
20 III-V族化合物半導体層(半導体層)
10 Base substrate 11 Substrate surface 11a Substrate main surface portion 11b Crystal growth surface portion 20 III-V group compound semiconductor layer (semiconductor layer)

Claims (7)

基板表面が、基板主面部分と、該基板主面部分とは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分と、を有するベース基板を用い、該ベース基板の該基板表面における該結晶成長面部分を起点として該III-V族化合物半導体を層状に結晶成長させることにより主面が非極性面又は半極性面であるIII-V族化合物半導体層を形成する半導体層形成工程を有する半導体装置の製造方法であって、
上記半導体層形成工程において、III-V族化合物半導体層を厚さ00μm以上に形成し、そして、得られるIII-V族化合物半導体層の表面の欠陥密度が1×10 /cm 以下である半導体装置の製造方法。
A base substrate having a substrate surface having a substrate main surface portion and a crystal growth surface portion capable of crystal growth of a group III-V compound semiconductor while having a plane orientation different from that of the substrate main surface portion. The III-V group compound semiconductor layer having a main surface that is a nonpolar plane or a semipolar plane is formed by growing the group III-V compound semiconductor in layers from the crystal growth plane portion of the substrate surface of the substrate. A method of manufacturing a semiconductor device having a semiconductor layer forming step,
In the semiconductor layer forming step is performed to form the above thickness 3 00Myuemu group III-V compound semiconductor layer, and the defect density of the surface of the resulting group III-V compound semiconductor layer is in 1 × 10 7 / cm 2 or less A method of manufacturing a semiconductor device.
請求項1に記載された半導体装置の製造方法において、
上記III-V族化合物半導体がGaNである半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the III-V compound semiconductor is GaN.
請求項1又は2に記載された半導体装置の製造方法において、
上記III-V族化合物半導体層の主面が{10−11}面である半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method for manufacturing a semiconductor device, wherein the main surface of the III-V compound semiconductor layer is a {10-11} plane.
請求項1乃至3のいずれかに記載された半導体装置の製造方法において、
上記ベース基板がサファイア基板である半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
A method for manufacturing a semiconductor device, wherein the base substrate is a sapphire substrate.
請求項1乃至4のいずれかに記載された半導体装置の製造方法において、
上記半導体層形成工程において形成したIII-V族化合物半導体層の全部又は一部を自立基板としてベース基板から分離する基板分離工程をさらに有する半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to any one of claims 1 to 4,
A method of manufacturing a semiconductor device, further comprising a substrate separation step of separating all or part of the III-V compound semiconductor layer formed in the semiconductor layer formation step from a base substrate as a free-standing substrate.
基板表面が、基板主面部分と、該基板主面部分とは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分と、を有するベース基板と、
上記ベース基板の上記基板表面における上記結晶成長面部分を起点として上記III-V族化合物半導体が層状に結晶成長して形成された主面が非極性面又は半極性面であるIII-V族化合物半導体層と、
を備えた半導体装置であって、
上記III-V族化合物半導体層は、その厚さが00μm以上であり、且つその表面の欠陥密度が1×10 /cm 以下である半導体装置。
A base substrate having a substrate surface having a substrate main surface portion and a crystal growth surface portion capable of crystal growth of a group III-V compound semiconductor having a different plane orientation from the substrate main surface portion;
A III-V group compound in which the principal surface formed by crystal growth of the III-V compound semiconductor in a layered manner starting from the crystal growth surface portion on the substrate surface of the base substrate is a nonpolar plane or a semipolar plane A semiconductor layer;
A semiconductor device comprising:
The group III-V compound semiconductor layer has a thickness of 3 00Myuemu least der is, and the semiconductor device defect density of the surface is 1 × 10 7 / cm 2 or less.
基板表面が、基板主面部分と、該基板主面部分とは面方位が異なると共にIII-V族化合物半導体の結晶成長が可能な結晶成長面部分と、を有するベース基板を用い、該ベース基板の該基板表面における該結晶成長面部分を起点として該III-V族化合物半導体を層状に結晶成長させることにより主面が非極性面又は半極性面であるIII-V族化合物半導体層を形成する半導体層形成工程と、
上記半導体層形成工程において形成したIII-V族化合物半導体層の全部又は一部を自立基板としてベース基板から分離する基板分離工程と、
を有する自立基板の製造方法であって、
上記半導体層形成工程において、III-V族化合物半導体層を厚さ00μm以上に形成し、そして、得られるIII-V族化合物半導体層の表面の欠陥密度が1×10 /cm 以下である自立基板の製造方法。
A base substrate having a substrate surface having a substrate main surface portion and a crystal growth surface portion capable of crystal growth of a group III-V compound semiconductor while having a plane orientation different from that of the substrate main surface portion. The III-V group compound semiconductor layer having a main surface that is a nonpolar plane or a semipolar plane is formed by growing the group III-V compound semiconductor in layers from the crystal growth plane portion of the substrate surface of the substrate. A semiconductor layer forming step;
A substrate separating step for separating all or part of the III-V compound semiconductor layer formed in the semiconductor layer forming step from the base substrate as a free-standing substrate;
A self-supporting substrate manufacturing method comprising:
In the semiconductor layer forming step is performed to form the above thickness 3 00Myuemu group III-V compound semiconductor layer, and the defect density of the surface of the resulting group III-V compound semiconductor layer is in 1 × 10 7 / cm 2 or less A method of manufacturing a free-standing substrate.
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JP2003209062A (en) * 2002-01-17 2003-07-25 Sony Corp Crystal growth method of compound semiconductor layer and semiconductor element
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JP4186603B2 (en) * 2002-12-05 2008-11-26 住友電気工業株式会社 Single crystal gallium nitride substrate, method for manufacturing single crystal gallium nitride substrate, and base substrate for gallium nitride growth
JP4513446B2 (en) * 2004-07-23 2010-07-28 豊田合成株式会社 Crystal growth method of semiconductor crystal
JP4713426B2 (en) * 2006-08-30 2011-06-29 京セラ株式会社 Epitaxial substrate and vapor phase growth method
JP4913674B2 (en) * 2007-06-07 2012-04-11 国立大学法人名古屋大学 Nitride semiconductor structure and manufacturing method thereof
JP5392855B2 (en) * 2008-08-25 2014-01-22 国立大学法人山口大学 Semiconductor substrate and manufacturing method thereof
JP5347835B2 (en) * 2009-08-25 2013-11-20 豊田合成株式会社 Group III nitride semiconductor crystal manufacturing method

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