JP2003209062A - Crystal growth method of compound semiconductor layer and semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a crystal growth method of compound semiconductor layer which is suitable for forming a semiconductor light emitting element having an excellent crystal property by effectively controlling crystal defects. <P>SOLUTION: A plane (111), a plane inclining to the plane (111) within ±10° in angles, and a plane which is chemically equivalent to those planes, are formed as selective growth reference planes to a compound semiconductor substrate of a zincblende structure. Moreover, a compound semiconductor layer of a wurtzite structure is formed by the crystal growth method with the selective growth from the selective growth reference plane in order to form a plane (1-101), a plane with inclination to the plane (1-101) within ±10° or the plane equivalent in the crystal property to those planes. Accordingly, the flat plane (1-101) having an excellent crystal property can be formed on the substrate. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal growth method of a compound semiconductor layer in which a wurtzite structure compound semiconductor layer is crystal-grown on a zinc blende structure compound semiconductor substrate, and a semiconductor device formed by the crystal growth method. In particular, the present invention relates to a crystal growth method of a compound semiconductor layer suitable for forming a semiconductor light emitting device having excellent crystallinity.

[0002]

2. Description of the Related Art Since gallium nitride (GaN) has a relatively large bandgap, it is expected to be applied to a semiconductor light emitting device such as a light emitting diode or a laser diode from blue light to ultraviolet light. Conventionally, a gallium nitride layer is generally formed by crystal growth on a required sapphire substrate. For example, when a light emitting diode is formed, a nitriding layer having a thickness of 30 nm formed at 510 ° C. is formed on the sapphire substrate. Gallium low temperature buffer layer, formed at 1020 ° C. and having silicon added, thickness of 4 μm
N-type gallium nitride layer at 1020 ° C. and silicon-added with a thickness of 0.15 μm of n-type Al _0.15 Ga
_0.85 N layer, 100 nm thick In _0.06 Ga _0.94 N layer formed at 800 ° C. and added with zinc and silicon,
0.15 μm thick p-type Al _0.15 Ga _{0.8 5} N layer formed at 1020 ° C. and containing magnesium, and 0.5 μm thick p-type nitridation formed at 1020 ° C. and containing magnesium A structure in which gallium layers are sequentially stacked is known (for example, S. Nakamura:
J. Val. Sci. Technol. A, Vol. 13, No. 3, P705 May /
See Jun 1995). The light emitting diode having this structure has a structure in which a p-electrode and an n-electrode are attached respectively, and nickel and gold are added to the p-type gallium nitride layer.
A p-electrode made of two layers is provided, and an n-electrode made of two layers of titanium and aluminum is provided for the n-type gallium nitride layer.

The gallium nitride layer crystal-grown using such a sapphire substrate has an advantage that the surface flatness is excellent and the crystallinity is excellent as compared with those formed on other substrates. However, there are problems that the sapphire substrate has no conductivity and cannot be cleaved, and that the process technology cultivated in III-V group compound semiconductors such as GaAs cannot be used. is there.

Therefore, in order to utilize the process technology cultivated in III-V group compound semiconductors, it has been attempted to carry out crystal growth of a gallium nitride layer on a zinc blende structure compound semiconductor substrate such as a GaAs substrate. ing. For example, in the crystal growth method of gallium nitride disclosed in Japanese Patent Application Laid-Open No. 9-194299, a surface inclined in advance with respect to the (100) plane is used, and a gallium nitride film is formed on the inclined surface to form various light emitting devices. A gallium nitride layer for forming is formed. The use of such an inclined surface has an advantage that the crystallinity of the gallium nitride film can be improved as compared with the case where the gallium nitride film is formed on the (100) plane or the (111) B plane. Further, similarly, as a technique of forming a gallium nitride-based compound semiconductor layer on a zinc blende structure compound semiconductor substrate using a surface inclined with respect to a (100) substrate, it is described in JP-A-9-191128. The technology is known.

Further, G is electrically conductive and can be cleaved.
In order to form a high-quality gallium nitride film on an aAs substrate, a technique of forming a Ga-excessive surface on the substrate surface is also known, as disclosed in, for example, Japanese Patent Application Laid-Open No. 9-255496. When forming this Ga-excessive surface, heat treatment is performed at a low temperature of 600 to 700 ° C. without supplying a raw material containing a Group V element. By this heat treatment, when the group V source material is supplied later, the surface of GaAs can be sufficiently initial-nitrided, and the gallium nitride layer having excellent flatness can be grown.

In the semiconductor process technology, there is also known a technology in which a gallium nitride layer is crystal-grown on a silicon substrate using the most general silicon substrate.
Anisotropic etching is performed on a silicon substrate forming an angle of several degrees with the (01) plane, and the [0, 0, 0, 1] direction of the gallium nitride compound semiconductor layer is oriented in the [1, 1, 1] direction. Of the flat gallium nitride-based compound semiconductor layer configured as
-101) surface forming technology is also known (Proceedi
ngs 2001 Korea-Japan Joint Workshop on Advanced Se
miconductor Process and Equipments, pp.84-88).

[0007]

Usually, when crystal-growing a gallium nitride-based compound semiconductor, (0001)
Although the plane is used, the number of dangling bonds for capturing a nitrogen atom in the (0001) plane is larger than that in another plane, for example, the S plane ((1-101) plane). It is known that the number of semiconductor light emitting elements is reduced, and thus the manufactured semiconductor light emitting element has an aspect that the light emitting characteristics are not always sufficient. However, in the current process technology, it is difficult to make the S-plane ((1-101) plane a flat main surface on the substrate, and the S-plane ((1-101) plane is a final element structure. Will have an inclined surface.

Similarly, when a zinc blende structure compound semiconductor substrate such as a GaAs substrate is used, the substrate has conductivity and cleaving can be realized.
When a pre-tilted surface is simply used as a reference for crystal growth as in the techniques disclosed in Japanese Patent No. 94299 and Japanese Patent Laid-Open No. 9-191128, the crystal plane is determined by the tilted angle. On the contrary, if the tilt is not made with high precision, a new problem occurs that the device characteristics vary.

Further, in the technique of forming a Ga-excessive surface as disclosed in Japanese Patent Application Laid-Open No. 9-255496, it should be noted as a measure for improving the surface flatness, but the Ga-excessive region is a semiconductor light emitting element. In some cases, the problem may occur that the light emitting characteristics of the manufactured semiconductor light emitting element deteriorate.

In the technique of forming a flat (1-101) plane of a gallium nitride-based compound semiconductor layer using a silicon substrate as described above, the gallium nitride layer is deposited on the surface of the silicon substrate in the initial stage of growth. There is a problem that it is not specified whether the atom is a gallium atom or a nitrogen atom. That is, in the [0, 0, 0, 1] direction of the gallium nitride-based compound semiconductor deposited on the silicon substrate, the gallium nitride-based compound semiconductor has polarity, whereas the silicon substrate itself is diamond. Is a structural substrate,
The [1,1,1] direction is non-polar. Therefore, it is not specified whether the deposition starts from gallium atoms or nitrogen atoms on a non-polar silicon substrate, and if the crystal layers that started deposition with different atoms collide with each other, strain or the like may occur. Defects are likely to occur.

In view of the above technical problems, the present invention provides a crystal growth method for a compound semiconductor layer suitable for forming a semiconductor light emitting device having excellent crystallinity by effectively suppressing crystal defects, and An object of the present invention is to provide a semiconductor device formed by the crystal growth method of the compound semiconductor layer.

[0012]

In order to solve the above-mentioned technical problems, a crystal growth method for a compound semiconductor layer according to the present invention comprises a (111) plane on a zinc blende structure compound semiconductor substrate,
A plane having an inclination within ± 10 ° with respect to the (111) plane or a plane crystallographically equivalent to these planes is formed as a selective growth reference plane, and a compound semiconductor layer having a wurtzite structure is formed from the selective growth reference plane by the selective growth. Crystal growth (1-10
1) plane, a plane having an inclination with respect to the (1-101) plane within ± 10 °, or a plane crystallographically equivalent to these planes.

According to the crystal growth method of a compound semiconductor layer of the present invention, a compound semiconductor layer having a wurtzite structure is crystal-grown on a zinc blende structure compound semiconductor substrate. The growth method is selective growth. , The selective growth starts from the selective growth reference plane. The selective growth reference plane is selected to be the (111) plane of the zinc blende structure compound semiconductor substrate, the plane having an inclination within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes. By applying (1
-101) plane, inclination with respect to (1-101) plane is ± 10
It is possible to obtain a compound semiconductor layer having a wurtzite structure having a plane within ° or a plane crystallographically equivalent to these planes. Since the zinc blende structure compound semiconductor substrate itself is made of a material having polarity as described above, the defect density can be reduced and the (1-101) plane formed by selective growth has a high surface dangling bond density. Deposit good quality crystals.

Regarding the fact that a crystal layer having excellent crystallinity can be obtained by selecting such crystal planes, for example, a GaAs substrate is selected as a zinc blende structure compound semiconductor substrate and a GaN layer is formed as a wurtzite structure compound semiconductor layer. For example, the case of [1], [1] of a GaAs substrate is explained.
The direction is oriented parallel to the [0, 0, 0, 1] direction of the GaN layer, and when the required selective growth is performed with the (111) plane of the GaAs substrate as the reference plane for selective growth, Ga
The original main surface [0, 0, 1] direction of the As substrate and the GaN layer
The [1, -1, 0, 1] directions are aligned with an inclination angle of about 7 degrees or less. Therefore, the original main surface of the GaAs substrate
Crystal planes can be formed in the same direction as the [0, 0, 1] direction, and a good quality crystal with few defects can be obtained.

In the semiconductor element of the present invention, the zincblende structure compound semiconductor substrate is provided with a (111) plane, a plane within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes. It is formed as a selective growth reference plane, and crystals are grown from the selective growth reference plane by selective growth (1-1
The compound semiconductor layer having a wurtzite structure is formed with a 01) plane, a plane with an inclination of ± 10 ° or less with respect to the (1-101) plane, or a plane crystallographically equivalent to these. It is characterized in that a compound semiconductor layer is formed with a first conductivity type layer, a second conductivity type layer, and an active layer.

According to the crystal growth method for a compound semiconductor layer of the present invention described above, a high-quality compound semiconductor layer having a wurtzite structure with few crystal defects is formed. By forming the first conductivity type layer, the second conductivity type layer, and the active layer, it is possible to form an element having excellent light emitting characteristics.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. The crystal growth method of a compound semiconductor layer according to the present invention is a (111) plane on a zincblende structure compound semiconductor substrate, a plane within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes. Is formed as the selective growth reference plane, and the compound semiconductor layer having a wurtzite structure is crystal-grown from the selective growth reference plane by the selective growth, and the inclination with respect to the (1-101) plane and the (1-101) plane is within ± 10 °. Or a surface crystallographically equivalent to these surfaces is formed.

The substrate used in the present invention is a zinc blende structure compound semiconductor substrate such as gallium arsenide (GaA).
s), and a zinc-blende structure compound semiconductor substrate may be composed of a group III-V compound semiconductor such as beta-SiC, BN, BP, AlP, AlAS, GaP,
GaAs, GaSb, beta-ZnS, ZnSe, ZnTe, beta-HgS, HgSe,
The structure may be one or a combination of materials selected from HgTe, InP, InAs, and InSb. Further, in a device manufacturing method that does not include a cleavage step as described below, a substrate is formed by laminating these zinc blende structure compound layers on various substrates such as a glass substrate, a silicon substrate, and a sapphire substrate. May be.

In such a zinc blende structure compound semiconductor substrate, the inclination with respect to the (111) plane and the (111) plane is ± 1.
A surface within 0 ° or a surface crystallographically equivalent to these surfaces is processed so as to serve as a reference surface for selective growth. The major surface of the substrate typically has a (001) plane, and such a major surface is (0
In the case of using a zinc blende structure compound semiconductor substrate for the (01) plane, in order to expose the (111) plane, unevenness is formed on the main surface of the substrate by a method such as anisotropic etching to form the (001) plane. It is possible to form a (111) plane that appears as a stepped portion inclined with respect to. Such a (111) plane can be formed into an arbitrary pattern by performing selective anisotropic etching using an etching mask. By controlling the shape of the mask, uneven or concave Can also be striped or polygonal.

For example, when a concave portion is formed on the main surface of the substrate by a method such as anisotropic etching and the side surface thereof is an inclined (111) surface, the opposite side surface is (-). 1-11) plane, and these (11
When crystal growth is attempted from both the 1) plane and the (-1-11) plane, the crystals grown from the (111) plane and the crystals grown from the (-1-11) plane collide with each other. Prior to the selective growth, a growth-inhibiting film is formed such that only one (111) plane faces the opening. The growth-inhibiting film is a film for inhibiting crystal growth on the film, and the growth-inhibiting film does not exist in the selectively formed opening, so that the required selective growth is performed. A mask material made of an insulating film such as a silicon oxide film or a silicon nitride film is used for the growth inhibiting film. The shape of the opening of this mask is a stripe shape as an example, but it may be a shape that does not cause a problem in cleavage even in the case of an element that does not cleave or when cleaving,
For example, the shape may be a curved shape, a circular shape, an elliptical shape, a triangular shape, a polygonal shape such as a pentagonal shape or a hexagonal shape, or a composite thereof. Moreover, it is possible to form a plurality of openings as in a normal semiconductor process.

As described above, the plane serving as the selective growth reference plane is (1
Centering on the (11) plane, the inclination with respect to the (111) plane is ± 10
Surfaces within ° and surfaces crystallographically equivalent to these are also included. According to the experimental results and the like, even if the (111) plane is not accurate, it is possible to achieve similar crystal growth to some extent even on a plane within ± 10 ° with respect to the (111) plane. You may use. Further, a plane crystallographically equivalent to these (for example, a (-1-1-1) plane) can be considered in the same manner.

When a growth-inhibiting film or the like serving as a mask for such selective growth is formed, the (111) plane and (111) plane are formed.
A compound semiconductor layer having a wurtzite structure is crystal-grown by selective crystal growth while facing a plane with an inclination of ± 10 ° or less or a plane crystallographically equivalent to the plane from the opening of the growth-inhibiting film. As the compound semiconductor layer to be selectively grown, a nitride semiconductor having a wurtzite type crystal structure, a BeMgZnCdS compound semiconductor, and BeM
A gZnCdO-based compound semiconductor or the like is preferable. As the crystal layer made of a nitride semiconductor, for example, a group III compound semiconductor can be used, and gallium nitride (Ga
N) -based compound semiconductors, aluminum nitride (AlN) -based compound semiconductors, indium nitride (InN) -based compound semiconductors, indium gallium nitride (InGaN) -based compound semiconductors, aluminum gallium nitride (AlGaN) -based compound semiconductors are preferably formed. In particular, gallium nitride-based compound semiconductors are preferable.

In the present invention, InGaN, Al
GaN, GaN, etc. do not necessarily mean a nitride semiconductor of only a ternary mixed crystal and only a binary mixed crystal.
Needless to say, aN is within the scope of the present invention even if it contains a trace amount of Al and other impurities within a range that does not change the action of InGaN. Further, the surface substantially equivalent to the S-plane includes a plane orientation tilted in the range of 5 to 6 degrees with respect to the S-plane. Here, in the present specification, the term “nitride” refers to B, Al, Ga, In, and Ta as group III, and the group V as N.
Refers to compounds containing, within 1% of the whole or 1x10
^In some cases, impurities of ²⁰ cm ³ or less are included.

As a method of growing this compound semiconductor layer,
Various vapor phase epitaxy methods can be mentioned, for example, vapor phase epitaxy methods such as organometallic compound vapor phase epitaxy method (MOCVD (MOVPE) method) and molecular beam epitaxy method (MBE method),
A hydride vapor phase epitaxy method (HVPE method) can be used. Among them, according to the MOVPE method, a material having good crystallinity can be obtained quickly. In the MOVPE method, TMG (trimethylgallium) and TEG (triethylgallium) as Ga sources, TMA (trimethylaluminum) and TEA (triethylaluminum) as Al sources, and TMI (trimethylindium) and TEI (triethylindium) as In sources. ) And other alkyl metal compounds are often used, and as the nitrogen source, gases such as ammonia and hydrazine are used. As the impurity source, silane gas is used for Si, germane gas is used for Ge, Cp2Mg (cyclopentadienyl magnesium) is used for Mg, and DEZ (diethyl zinc) is used for Zn. In the MOVPE method, these gases are supplied to the surface of the substrate heated to, for example, 600 ° C. or higher to decompose the gas, thereby
The nAlGaN-based compound semiconductor can be epitaxially grown.

As described above, centering around the (111) plane,
In the case where selective growth is performed using a plane with an inclination with respect to the (111) plane within ± 10 ° or a plane crystallographically equivalent to these planes as the selective growth reference plane which is the growth start surface of the selective growth, the S plane (( The compound semiconductor layer having a wurtzite structure having a (1-101) plane), a plane having an inclination within ± 10 ° with respect to the (1-101) plane, or a plane crystallographically equivalent to these appears as a flat plane. The S-plane is a stable surface that is observed when such selective growth is performed, and is a surface that is relatively easy to obtain.

Regarding the S-plane, when a crystal layer is formed by using a gallium nitride-based compound semiconductor, the number of bonds from Ga to N becomes 2 or 3 on the S-plane, which is next to the C-plane. Here, since the C-plane cannot be practically obtained on the C + plane, the number of bonds on the S-plane becomes the largest.
For example, when a nitride is grown on a sapphire substrate having a C + plane as the main surface, the surface of the wurtzite type nitride is generally C
Although it becomes a + plane, a flat S plane can be stably formed by utilizing the selective growth as described above, and an N bond which tends to be detached on a plane parallel to the C + plane is less than Ga. While they are bonded by a book bond, they are bonded by at least one pound on the S side. Therefore,
This effectively increases the V / III ratio, which is advantageous for improving the crystallinity of the laminated structure. Further, since the S-plane itself has an orientation different from that of the selective growth reference plane, dislocations may bend with respect to the S-plane, which is also advantageous in reducing defects. The selective growth mask also contributes to the reduction of substrate dislocation.

Further, since a zincblende structure compound semiconductor substrate having polarity is used as the starting surface for selectively growing the compound semiconductor layer, when the compound semiconductor layer is laminated thereon, it is caused by the polarity. Atomic alignment occurs, which can increase the crystal regularity and suppress the defect density. In other words, when compared with a non-polar silicon substrate, it is not specified whether the deposition starts from gallium atoms or nitrogen atoms. However, the problem that the defects tend to occur easily occurs in the silicon substrate, but such a problem does not occur in the zinc blende structure compound semiconductor substrate in which different atoms are stacked in layers and have polarities on the surface. become.

In the compound semiconductor layer having a wurtzite type crystal structure to be selectively grown, a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer are laminated in order to make the device function as a light emitting device, for example. To be done. The first conductivity type semiconductor layer may be formed continuously with the lower compound semiconductor layer.
In the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer, the first conductivity type is p-type or n-type, and the second conductivity type is the opposite conductivity type. For example, when the crystal layer is composed of a silicon-doped gallium nitride compound semiconductor layer, the n-type semiconductor layer is composed of a silicon-doped gallium nitride compound semiconductor layer, and In
A double hetero structure can be formed by forming a GaN layer as an active layer and further forming a magnesium-doped gallium nitride-based compound semiconductor layer as a p-type semiconductor layer thereon. It is also possible to adopt a structure in which the InGaN layer which is the active layer is sandwiched between AlGaN layers or a structure in which the AlGaN layer is formed on only one side. The active layer may be composed of a single bulk active layer, but a single quantum well (SQ
A quantum well structure such as a W) structure, a double quantum well (DQW) structure, and a multiple quantum well (MQW) structure may be formed. A barrier layer is additionally used in the quantum well structure for the purpose of separating the quantum well. InGaN active layer
When the layer is formed, the structure is particularly easy to manufacture in the manufacturing process, and the light emitting characteristics of the device can be improved. Furthermore, this InGaN layer is particularly easy to crystallize and has good crystallinity when grown on the S-plane, which has a structure in which nitrogen atoms are hard to be desorbed, and the luminous efficiency can be improved.

It should be noted that the nitride semiconductor has a property of becoming n-type due to nitrogen vacancies formed in the crystal even if it is non-doped.
Usually, by doping a donor impurity such as Si, Ge, or Se during crystal growth, an n-type having a preferable carrier concentration can be obtained. Further, the p-type nitride semiconductor can be obtained by doping the crystal with an acceptor impurity such as Mg, Zn, C, Be, Ca, or Ba, but in order to obtain a p-layer having a high carrier concentration, Is preferably annealed at 400 ° C. or higher in an inert gas atmosphere such as nitrogen or argon after doping with an acceptor impurity. There is also a method of activation by electron beam irradiation or the like, which is activated by microwave irradiation, light irradiation, or the like. There is also a way to make it.

An n-side electrode (or n-electrode) and a p-side electrode (p-electrode) are formed on the first conductive type semiconductor layer and the second conductive type semiconductor layer. Ti / Al / Pt as n-side electrode
A metal material such as / Au may be vapor-deposited, or a transparent electrode such as ITO may be formed. The p-side electrode is, for example, Ni /
The electrode layer may be formed of a laminated structure of Pt / Au or Ni (Pt) / Pt / Au, or may be formed of a thin film of Ag or aluminum while using a thin Ni film as a contact metal for reducing the contact resistance. One of the p-electrode and the n-electrode can be shared by a plurality of laser elements, and these electrode layers are generally formed by depositing a multilayer metal film by vapor deposition or the like on each electrode. In order to divide each element, it is possible to perform fine processing by lift-off or the like using photolithography.

When a semiconductor device is formed by using the crystal growth method of the compound semiconductor layer of the present invention, particularly when a semiconductor laser device is formed, a resonator is formed on the end face of the stripe-shaped crystal growth portion or the like. . As is well known, a resonator can be formed by cleaving a crystal, and for example, a resonator plane can be formed by cleaving a plane substantially perpendicular to the longitudinal direction of a striped opening. it can. In this case, (1) of the compound semiconductor layer selectively grown using the (111) plane as a reference plane for selective growth.
The (-120) plane is (1) of the zinc blende structure compound semiconductor substrate.
It is parallel to the −10) plane and is extremely effective when both are divided by the crystal plane. Even if the resonance surface is not formed by cleavage, the resonance surface may be formed by an etching method or the like.

Further, by forming a plurality of semiconductor laser elements formed by the crystal growth method of the compound semiconductor layer of the present invention so as to be arranged, a display device and a lighting device can be constructed. In a display device in which a plurality of such semiconductor laser elements are arranged, the light emitting elements can be arranged at a high density, and the easiness of manufacturing can be improved by sharing the electrodes. Further, it is not limited to a display device that emits light of a single color, and a display device that emits light of multiple colors can be configured.

The present invention will be described in more detail below with reference to each embodiment. The crystal growth method of the compound semiconductor layer of the present invention can be modified and changed without departing from the scope of the invention, and the present invention is not limited to the following embodiments.

[First Embodiment] In the crystal growth method of a compound semiconductor layer of the present embodiment, a GaAs substrate having a (001) plane as a main surface is used as an example of a zinc blende structure compound semiconductor substrate, and In this example, the compound semiconductor layer to be laminated on is a GaN layer.

As shown in FIG. 1A, a GaAs substrate 11 having a (001) plane as a main surface 11a is prepared. This GaAs substrate 11 is an example of a zinc blende structure compound semiconductor substrate, and the cross section 11c shown in FIG. 1 has a (1-10) plane, and when a crystal is cleaved in a cleaving step as described later, The (1-10) plane can be used as a cleavage plane and can be easily cleaved. It should be noted that FIG. 1B shows the plane orientation of the main surface and the plane orientation of the cross section of the substrate, and the minus symbol in the text of the specification is indicated by a bar symbol. In the present embodiment, the GaAs substrate 11 having the (001) plane as the main surface 11a is used as the zinc blende structure compound semiconductor substrate, but the present invention is not limited to this.
It is also possible to use a zinc blende structure compound semiconductor substrate, for example, a tilted substrate, whose main surface is a surface whose inclination is within ± 15 ° with respect to the (0) plane, or a crystallographically equivalent surface.

Next, a photoresist film is formed on the entire main surface 11a of the GaAs substrate 11, and the photoresist film is selectively exposed and developed so as to form a stripe-shaped opening pattern. Next, anisotropic etching is performed to remove the main surface 11a of the GaAs substrate 11 facing the bottom of the opening of the photoresist film, and the recess 12 shown in FIG. 2 is formed in the main surface 11a of the GaAs substrate 11. The shape of the recess 12 is about 4
It is a structure with a pair of inclined side surfaces and a bottom surface inclined at 5 degrees,
The pair of inclined side surfaces are respectively in the [-1, -1, 1] direction and
It has a plane orientation of [1,1,1] direction, and [1,1,1]
(111) plane having a plane orientation of direction and [-1, -1,
The (-1-11) plane having the plane orientation of the 1] direction is extended in a strip shape when viewed from above, and the strip-shaped (111) plane is formed in parallel at a predetermined pitch. In the present embodiment, the anisotropic etching is finished so that the bottom surface remains. However, the bottom surface is removed by deeper etching to form a V-shaped cross section, the type of etching is changed, or the inclination is changed. By using the substrate, it is possible to control so that the pair of inclined side surfaces do not appear symmetrically.

Next, a thin silicon oxide film is formed as a growth inhibition film 13 by a vapor phase growth method or the like on the entire main surface 11a of the GaAs substrate 11 in which the recess 12 is formed. The growth inhibiting film 13 is formed along the pair of inclined side surfaces and the bottom surface in the recess 12 and once covers the inside of the recess 12. Then, a photoresist film is formed on the growth inhibiting film 13, and the photoresist film is selectively exposed and developed so as to have a stripe-shaped opening pattern. The opening pattern is such that each (111) surface is opened and the (111) surface is exposed at the bottom of the photoresist film. That is, since the strip-shaped (111) planes are repetitive patterns arranged in parallel at a predetermined pitch, the openings of the photoresist film also have repetitive patterns in which strip-shaped openings are arranged in parallel at a predetermined pitch. Becomes Due to the selective exposure and development of the photoresist film, the surface of the growth inhibiting film 13 is exposed at the bottom of the opening of the photoresist film, and the growth inhibiting film 13 is selectively removed by etching to form the (111) plane. Selective growth reference plane consisting of 14
To form. The selective growth reference plane 14 formed here is the (111) plane in the present embodiment, but the present invention is not limited to this, and a plane having an inclination within ± 10 ° with respect to the (111) plane or crystallographically equivalent to these planes. It may be an aspect.

Next, as shown in FIG. 4, a silicon-doped n-type GaN contact layer 15 is formed as a compound semiconductor layer having a wurtzite crystal structure by selective growth. The silicon-doped n-type GaN contact layer 15 selectively grows from the (111) plane that is the selective growth reference plane 14, and even if the source gas is deposited on the growth inhibition film 13, the growth inhibition is easily caused. It evaporates on the film 13. This silicon-doped n-type GaN contact layer 15 grows so as to maintain a substantially equilateral triangular shape in cross section, and when viewed from the direction normal to the main surface of the substrate, has a strip shape having a direction perpendicular to the illustrated cross section as a longitudinal direction. Grow into a pattern.

FIG. 5 further shows silicon-doped n-type GaN.
It shows a state in which the growth of the contact layer 15 has progressed, and the height (position in the direction normal to the main surface of the substrate) of a portion of the silicon-doped n-type GaN contact layer 15 having a substantially triangular cross section is growth impeded. It extends over the growth-inhibiting film 13 beyond the film 13. As a result, a flat and relatively large (1-101) plane (that is, S plane) 15 is formed above the main surface of the substrate of the silicon-doped n-type GaN contact layer 15.
s appears. The bottom side of the silicon-doped n-type GaN contact layer 15 is the (0001) plane, and the n-type Ga is
(0001) plane of N contact layer 15 and (1-101)
A ridgeline is formed with the surface.

By continuing selective growth, (1-10
1) The surface 15s is further grown, the adjacent silicon-doped n-type GaN contact layers 15 are integrated, and large crystal growth is performed to form one flat surface as shown in FIG. To do. In this example, a cavity is formed on the (-1-11) plane of the inclined side surface facing the (111) plane, but the cavity does not necessarily have to be formed.

As shown in FIG. 6B, the (1-101) plane of the silicon-doped n-type GaN contact layer 15 has an angle difference of about 7 degrees with the (001) plane of the GaAs substrate 11. Therefore, silicon-doped n-type Ga having a surface substantially aligned with the main surface of the GaAs substrate 11 is present.
The N contact layer 15 is formed. In addition, (b) of FIG.
6A is a diagram showing a plane orientation in a cross section 11c of FIG. 6A. In FIG. 6B, a plane orientation [1, -1, 0] direction of a GaAs substrate perpendicular to the cross section 11c and a GaN [ 1-120]
The directions are the same.

Next, based on the (1-101) plane of the silicon-doped n-type GaN contact layer 15, as shown in FIG. 7, each semiconductor layer for sequentially functioning as a light emitting element such as a semiconductor laser is sequentially laminated. To do. First, n-type Al is formed on the silicon-doped n-type GaN contact layer 15.
The GaN clad layer 16 is formed and its n-type AlGaN is formed.
An n-type GaN guide layer 17 is formed on the clad layer 16. InGaN / Ga is formed on the n-type GaN guide layer 17.
A multiple quantum well (MQW) layer 18 of N is formed,
On the multiple quantum well (MQW) layer 18, p-type AlGa is formed.
An N layer 19 is formed, and p is formed on the p-type AlGaN layer 19.
The type GaN guide layer 20 is formed. A p-type AlGaN cladding layer 21 and a p-type GaN contact layer 22 are formed on the p-type GaN guide layer 20.

After forming each of the compound semiconductor layers as described above, cleavage is performed for the purpose of forming a resonance plane for laser oscillation, for example. Cleavage is to break the crystal structure along a predetermined crystal plane, and in the present embodiment, the cleavage line 30 shown by the dotted line in FIG. 7 is the plane orientation [1, -1, 0] direction of the GaAs substrate and the GaN [ The [1-120] plane is the (1-10) plane of the GaAs substrate and the (1-120) plane of the GaN-based semiconductor layer, which are oriented in parallel with each other, and as shown in FIG. Easily done.

Next, as shown in FIG. 9, the GaAs substrate 1
1 and the growth inhibition film 13 functioning as a mask material are removed. Various methods such as an etching method, a polishing method, and laser ablation can be used to remove the GaAs substrate 11 and the growth inhibition film 13.

The growth-inhibiting film 13 has an uneven surface formed in the recess 12, and the back surface of the n-type GaN contact layer 15 after the growth-inhibiting film 13 is removed also has the shape of the growth-inhibiting film 13. Reflecting the above, the shape becomes uneven. Therefore, in the present embodiment, the back surface of the n-type GaN contact layer 15 is polished, and as shown in FIG.
The back surface of the aN contact layer 15 is made flat. After the flattening of the back surface, element isolation and formation of a p-electrode and an n-electrode are performed to form a semiconductor light emitting element.

As described above, according to the crystal growth method of the compound semiconductor layer of the present embodiment, the GaAs substrate 11 itself is made of the material having the polarity as described above, so that the defect density can be reduced. In addition, it is formed by selective growth (1-1
Since the (01) plane has a high dangling bond density on the surface, good quality crystals can be deposited, and (1-)
Since the (101) plane constitutes a flat plane, it is advantageous when a device is formed by laminating various compound semiconductor layers.

From the selection of the above-mentioned crystal planes, the (111) plane of the GaAs substrate 11 facing between the selective growth masks is an inclined plane when viewed in the direction normal to the principal plane of the substrate, By using this inclined (111) plane as the selective growth reference plane 14 which is the crystal growth start plane, it is possible to reduce substrate dislocations. Furthermore, the plane orientation of the GaAs substrate
The [1, -1, 0] direction and the [1-120] direction of GaN are oriented parallel to each other and the (1-10) plane of the GaAs substrate and the G direction, respectively.
By making the (1-120) plane of the aN-based semiconductor layer a cleavage plane, since these planes are parallel to each other, the cleavage work can be easily carried out and a good resonance plane can be formed. is there.

[Second Embodiment] FIG. 11 is a view showing an example of a semiconductor light emitting device formed by using the above-described compound semiconductor layer crystal growth method. This semiconductor light emitting element is a laser element and has the above-mentioned cleavage plane 51 as a resonance plane.

The silicon-doped n-type GaN contact layer 42 is a compound semiconductor film grown from the selective growth reference plane, and the upper surface of the n-type GaN contact layer 42 is (1-1
01) surface. The n-type AlGaN cladding layer 43 is formed so as to be continuous through the (1-101) plane,
An n-type GaN guide layer 44 is formed on the n-type AlGaN cladding layer 43. Multiple quantum wells (MQW) made of InGaN / GaN on the n-type GaN guide layer 44
The layer 45 is formed, and the multiple quantum well (MQW) layer 45 is formed.
A p-type AlGaN layer 46 is formed on the p-type AlG layer 46.
A p-type GaN guide layer 47 is formed on the aN layer 46. On the p-type GaN guide layer 47, p-type AlGa is formed.
An N clad layer 48 and a p-type GaN contact layer 49 which is, for example, magnesium-doped are formed.

An n electrode 41 is formed on the back surface of the n-type GaN contact layer 42, and a p electrode 50 is formed on the p-type GaN contact layer 49. Where n electrode 4
For example, a metal material such as Ti / Al / Pt / Au may be vapor-deposited, or a transparent electrode such as ITO may be formed. The p-electrode 50 is, for example, Ni / Pt / Au or Ni
A laminated structure of (Pt) / Pt / Au may be used, or an electrode layer may be formed of a thin film of Ag or aluminum while using a thin Ni film as a contact metal for reducing contact resistance.

In such a semiconductor light emitting device according to the present embodiment, since the GaN layer formed as the wurtzite type compound semiconductor layer has extremely good crystallinity, its light emitting characteristics are improved, The life can be extended. In addition, as described above, (1
Since the cleavage plane 51 obtained by simultaneously cleaving the (-10) plane and the (1-120) plane of the GaN-based semiconductor layer serves as a resonance plane,
Its manufacture is also easy, and the highly accurate resonance surface using cleavage contributes to the laser oscillation of the semiconductor light emitting device.

In this embodiment, the semiconductor element is a semiconductor light emitting element such as a semiconductor laser. However, the semiconductor element is not limited to this, and the semiconductor element may be a transistor, a light receiving element or other functional element. The semiconductor light emitting element may also be a light emitting diode or the like.

[0053]

According to the above-described crystal growth method of the compound semiconductor layer of the present invention, since the zinc blende structure compound semiconductor substrate itself is made of the polar material as described above, the defect density can be reduced. Further, since the (1-101) plane formed by selective growth has a high dangling bond density on the surface, good quality crystals can be deposited, and the (1-101) plane constitutes a flat surface. Therefore, it is advantageous when a device is formed by laminating various compound semiconductor layers.

From the selection of the above-mentioned crystal planes, the (111) plane of the zinc blende structure compound semiconductor substrate facing between the selective growth masks is inclined when viewed in the direction normal to the main surface of the substrate. It is also possible to reduce substrate dislocations by using this inclined (111) plane as a selective growth reference plane which is a crystal growth start plane. Furthermore, the plane orientation [1, -1, 0] direction of the zinc blende structure compound semiconductor substrate and GaN
The [1-120] planes of the zinc-blende structure compound semiconductor substrate and the (1-120) plane of the GaN-based semiconductor layer, which are oriented in parallel with the [1-120] directions, are cleaved planes. Are parallel to each other, it is possible to easily proceed the cleavage work, and it is possible to form a good resonance surface when forming a laser element.

[Brief description of drawings]

FIG. 1 is a process perspective sectional view according to a crystal growth method of a compound semiconductor layer of a first embodiment of the present invention, FIG.
[FIG. 3] is a perspective view showing a GaAs substrate in a perspective view, and (b) is a view showing a plane orientation in the cross section.

FIG. 2 is a perspective cross-sectional view of a process according to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, wherein
It is a process perspective sectional view showing a process of forming a recess on an s substrate.

FIG. 3 is a process perspective cross-sectional view according to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, which is a process perspective cross-sectional view showing a state where the growth inhibition film is formed.

FIG. 4 is a perspective cross-sectional view of a step related to the crystal growth method for the compound semiconductor layer of the first embodiment of the present invention, showing a selective perspective growth using the growth inhibition film as a mask. is there.

FIG. 5 is a process perspective sectional view according to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, which is a process perspective sectional view at a stage where the selective growth is advanced.

FIG. 6 is a process perspective sectional view according to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, and is a process perspective sectional view showing a flat surface formed by selective growth.

FIG. 7 is a process perspective cross-sectional view relating to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, and is a process perspective cross-sectional view showing a state in which gallium nitride based semiconductor layers are laminated.

FIG. 8 is a process perspective sectional view according to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, which is a process perspective sectional view showing a cleavage process.

FIG. 9 is a perspective perspective sectional view of a step of a crystal growth method for a compound semiconductor layer according to a first embodiment of the present invention, which is a perspective perspective sectional view of a step of removing a substrate and a growth inhibition film.

FIG. 10 is a perspective cross-sectional view of a step relating to the crystal growth method of the compound semiconductor layer of the first embodiment of the present invention, which is a perspective cross-sectional view of the step of polishing the back surface side of the gallium nitride based semiconductor layer.

FIG. 11 is a perspective sectional view of a semiconductor light emitting device according to a second embodiment of the present invention.

[Explanation of symbols]

11 GaAs substrate 12 recess 13 Growth inhibition film 14 Selective growth reference plane 15, 42 n-type GaN contact layer 16,43 n-type AlGaN cladding layer 17,44 n-type GaN guide layer 18, 45 Multiple quantum well (MQW) layer 19, 46 p-type AlGaN layer 20, 47 p-type GaN guide layer 21, 48 p-type AlGaN cladding layer 22, 49 p-type GaN contact layer 41 n electrode 50 p electrode 51 Cleaved surface

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4G077 AA03 BE15 DB01 DB08 ED05                       ED06 HA02                 5F045 AA04 AA05 AB14 AB17 AC07                       AC12 AF02 AF04 AF06 AF13                       BB12 CA12 DA53 DB02 HA02                 5F073 AA45 AA51 AA55 AA74 AA89                       BA09 CA02 CA07 CA17 CB02                       CB04 CB05 DA05 DA16 DA21                       DA32 DA35 EA28 EA29

Claims (18)

[Claims] 1. A zincblende structure compound semiconductor substrate (11
1) plane, a plane having an inclination within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes is formed as a selective growth reference plane, and by selective growth, a wurtzite structure is formed from the selective growth reference plane. When the compound semiconductor layer is crystal-grown, the inclination with respect to the (1-101) plane and the (1-101) plane is ±.
A method for growing a crystal of a compound semiconductor layer, which comprises forming a plane within 10 ° or a plane crystallographically equivalent thereto. 2. The crystal growth method for a compound semiconductor layer according to claim 1, wherein the (1-101) plane or a plane crystallographically equivalent thereto is a flat plane. 3. The [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
[1] direction of the zinc blende structure compound semiconductor substrate [1,
The crystal growth method for a compound semiconductor layer according to claim 1, wherein the compound semiconductor layer is oriented in the [1, 1] direction. 4. The selective growth reference plane is a (111) plane of the zincblende structure compound semiconductor substrate or a plane within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes. The method for growing a crystal of a compound semiconductor layer according to claim 1, wherein: 5. The main surface during selective growth of the zinc blende structure compound semiconductor substrate is a (100) surface, a surface having an inclination with respect to the (100) surface within ± 15 °, or crystallographically equivalent to these. The method for growing a crystal of a compound semiconductor layer according to claim 1, wherein 6. The crystal growth method for a compound semiconductor layer according to claim 1, wherein the surface on which the zinc-blende structure compound semiconductor substrate is selectively grown is a surface on which irregularities are formed. 7. The compound semiconductor layer according to claim 6, wherein the unevenness is formed by subjecting the main surface of the zinc blende structure compound semiconductor substrate to selective anisotropic etching. Crystal growth method. 8. The crystal growth method for a compound semiconductor layer according to claim 6, wherein the concave or convex portions of the irregularities are formed in a stripe shape or a polygonal shape. 9. The method for crystal growth of a compound semiconductor layer according to claim 1, wherein the selective growth is performed by using a growth inhibition film covering a surface other than the selective growth reference plane. 10. The compound semiconductor layer of the wurtzite structure formed by the selective growth is formed so as to cover all or part of a main surface of the zinc blende structure compound semiconductor substrate. The method for growing a crystal of a compound semiconductor layer according to claim 1. 11. The crystal growth method for a compound semiconductor layer according to claim 1, wherein the zinc blende structure compound semiconductor substrate is made of a III-V group compound semiconductor. 12. The zinc blende structure compound semiconductor substrate
beta-SiC, BN, BP, AlP, AlAS, GaP, GaAs, GaSb, beta
-ZnS, ZnSe, ZnTe, beta-HgS, HgSe, HgTe, InP, InA
2. The method for growing a crystal of a compound semiconductor layer according to claim 1, comprising one or a combination of materials selected from s and InSb. 13. The selective growth reference plane is constituted by a plane composed of a group III atom.
A method for growing a crystal of a compound semiconductor layer according to claim 1. 14. The compound semiconductor layer having a wurtzite structure is a nitride compound semiconductor layer.
A method for growing a crystal of a compound semiconductor layer according to claim 1. 15. The nitride compound semiconductor layer is a gallium nitride-based compound semiconductor layer.
4. The crystal growth method of the compound semiconductor layer according to 4. 16. A zinc blende structure compound semiconductor substrate (1
11) plane, a plane having an inclination within ± 10 ° with respect to the (111) plane, or a plane crystallographically equivalent to these planes is formed as a selective growth reference plane, and crystals are grown from the selective growth reference plane by selective growth. (1-101) plane, (1-101)
A wurtzite structure compound semiconductor layer having a surface with an inclination of ± 10 ° or less, or a surface crystallographically equivalent thereto, and the wurtzite structure compound semiconductor layer has a first conductivity type. A semiconductor element comprising a layer, a second conductivity type layer, and an active layer. 17. The semiconductor device according to claim 16, wherein light is extracted from the active layer. 18. The semiconductor device according to claim 16, wherein the compound semiconductor layer having the wurtzite structure is cleaved, and the cleaved surface is used as a cavity end surface.