JP2001284266A - Method of manufacturing group iii nitride compound semiconductor and group iii nitride compound semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride compound semiconductor which suppresses through-transition. SOLUTION: A GaN layer 31 is etched into an island shape of dot, stripe, lattice or the like to provide step differences, and a mask 4 is formed on the bottoms of the step differences to have such a thickness that the upper surface of the step differences are lower than the upper surface of the GaN layer 31. The GaN layer 32 is laterally epitaxially grown with upper and side surfaces 31a and 31b of upper parts of the step differences as nuclei to bury the step differences, and thereafter it can also be grown upwards. At this time, the upper part of the mask 4 where the GaN layer 32 is laterally epitaxilally grown can be used as a region where propagation of through-transition of the GaN layer 31 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for producing a group III nitride compound semiconductor. In particular, the present invention relates to a method for manufacturing a group III nitride compound semiconductor using lateral epitaxial growth (ELO) growth. The group III nitride-based compound semiconductor is, for example, a binary system such as AlN, GaN, and InN, Al _x Ga _1-x N, Al _x In _1-x N, and Ga _x In _1-x N Also 0 <x
A ternary system such as <1), Al _x Ga _y In _1-xy N (0 <x <1, 0 <y
General formula Al _x Ga _y In including the quaternary system of <1, 0 <x + y <1)
_1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). In the present specification, unless otherwise specified, a group III nitride-based compound semiconductor simply referred to as a group III nitride-based compound semiconductor is a group III nitride-based compound semiconductor doped with an impurity for changing the conductivity type to p-type or n-type. Is also included.

[Prior art]

[0002] In the case of a light emitting device, for example, a group III nitride-based compound semiconductor is a direct transition type semiconductor having an emission spectrum ranging from ultraviolet to red over a wide range.
(LED) and laser diodes (LD). In addition, since its band gap is wide, stable operation can be expected at a higher temperature than elements using other semiconductors. Therefore, application to transistors such as FETs has been actively developed. In addition, because arsenic (As) is not the main component, development of various semiconductor devices in general is expected from an environmental point of view. In this group III nitride compound semiconductor, sapphire is usually used as a substrate and is formed thereon.

[0003]

However, when a group III nitride compound semiconductor is formed on a sapphire substrate, dislocation occurs due to a misfit in the lattice constant between sapphire and the group III nitride compound semiconductor. There is a problem that the element characteristics are not good. The dislocation due to the misfit is a threading dislocation penetrating the semiconductor layer in the vertical direction (perpendicular to the substrate surface), and a problem that a dislocation of about 10 ⁹ cm ⁻² propagates in the group III nitride compound semiconductor. There is. This propagates each group III nitride compound semiconductor layer having a different composition to the uppermost layer. As a result, for example, in the case of a light emitting element, there is a problem that the element characteristics such as the threshold current of the LD and the element life of the LD and the LED are not improved. Also,
Other semiconductor devices have only been low in mobility (mobility) because electrons are scattered by defects. These were the same when other substrates were used.

[0004] This will be described with reference to the schematic diagram of FIG. FIG. 12 shows a substrate 91, a buffer layer 92 formed thereon, and a group III nitride compound semiconductor layer 93 further formed thereon. Conventionally, sapphire or the like is used for the substrate 91, and aluminum nitride (AlN) or the like is used for the buffer layer 92. A buffer layer 92 of aluminum nitride (AlN) is
Although it is provided for the purpose of alleviating a misfit with the group II nitride-based compound semiconductor layer 93, the occurrence of dislocations cannot be reduced to zero. From this dislocation generation point 900, threading dislocations 9 in the vertical direction (perpendicular to the substrate surface)
01 propagates through the buffer layer 92 and the group III nitride compound semiconductor layer 93. Thus, various desired IIs are formed on the group III nitride-based compound semiconductor layer 93.
When an attempt is made to form a semiconductor device by laminating a group I nitride-based compound semiconductor, threading dislocations further propagate through the semiconductor device from the dislocation 902 reaching the surface of the group III nitride-based compound semiconductor layer 93 in the vertical direction. It will go. As described above, according to the conventional technique, there is a problem that propagation of dislocations cannot be prevented when forming a group III nitride compound semiconductor layer.

In recent years, a technique using lateral growth has been developed to prevent threading dislocations. This is achieved by forming a mask made of silicon oxide, tungsten, or the like having a partially striped window on a sapphire substrate or a group III nitride compound semiconductor layer, and using the semiconductor in the window as a nucleus to form a mask. It grows laterally on top. Further, a growth method in which a lateral growth portion is formed to be floating with respect to a substrate, such as a so-called pendio ELO, has been developed. However, in the case of ELO growth using a mask, since the mask is higher than the portion of the window serving as a nucleus for crystal growth, the crystal grows once in the vertical direction using the semiconductor in the window portion as a nucleus and then goes around the mask. As shown in FIG. For this reason, there is a problem that dislocations and distortions are often generated at the corners of the mask, and threading dislocations generated at these portions suppress a decrease in threading dislocations. or,
Also in the Pendio ELO, since a mask is formed on the upper surface of a layer serving as a nucleus for crystal growth, there is a problem that a threading dislocation is similarly generated at a corner when the semiconductor is grown on the mask.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to produce a group III nitride compound semiconductor in which the generation of threading dislocations is suppressed.
In particular, it is to improve the drawbacks of ELO growth using a mask.

[0007]

According to a first aspect of the present invention, there is provided a method of manufacturing a group III nitride-based compound semiconductor by epitaxially growing a group III nitride-based compound semiconductor on a substrate. At least one
The base layer, which is made of a group III nitride-based compound semiconductor, and whose uppermost layer is the first group III nitride-based compound semiconductor, is made into an island state such as a dot-like, stripe-like, or lattice-like structure by etching. A step of providing a step to expose the surface of the intermediate portion or the surface of the substrate to the bottom, a step of forming a mask on the bottom of the step with a thickness such that the upper surface is lower than the upper surface of the uppermost layer, and forming by etching. The upper surface and the side surface of the upper step of the first group III nitride-based compound semiconductor in an island state such as a spot, stripe, or lattice are formed as a second core.
Growing the group III nitride-based compound semiconductor vertically and horizontally.
In this specification, the base layer is used to collectively represent a single layer of a group III nitride-based compound semiconductor layer and a multilayer including at least one group III nitride-based compound semiconductor layer. . In addition, the island state here is a concept that conceptually refers to a state of an upper step formed by etching.
The upper portions of the steps may be continuous over an extremely wide range, such as forming the entire surface of the wafer in a stripe shape or a lattice shape. Further, the side surface of the step does not necessarily mean that the side surface is perpendicular to the substrate surface and the surface of the group III nitride compound semiconductor, but may be an oblique surface. On this occasion,
The cross section may have a V-shape without a bottom surface at the bottom of the step. The same applies to the following claims unless otherwise specified.

[0008] The invention described in claim 2 is the first invention.
In the method of manufacturing a group III nitride compound semiconductor described in the above, the mask is made of a substance on which epitaxial growth of the group III nitride compound semiconductor is inhibited.

The invention according to claim 3 is characterized in that substantially all of the side surfaces of the step are {11-20} surfaces.

[0010] The invention according to claim 4 is the first II.
It is characterized in that the group I nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition. Here, the same composition means that a difference in the degree of doping (a difference of less than 1% in molar ratio) is neglected.

The invention according to claim 5 is characterized in that the mask is a silicon oxide film, a silicon nitride film, a tungsten, a titanium nitride film or another conductive mask.

The invention according to claim 6 is the first invention.
A group III nitride compound semiconductor formed on a portion of a group III nitride compound semiconductor layer produced by the method according to any one of claims 5 to 5 which has been epitaxially grown laterally. Element.

The invention according to claim 7 is the first invention.
A group III nitride-based compound semiconductor layer manufactured by the method according to any one of claims 5 to 5, wherein a different group III nitride-based compound semiconductor layer is stacked on a layer formed on a laterally epitaxially grown portion. A group III nitride compound semiconductor light-emitting device characterized by being obtained.

The invention described in claim 8 is the first invention.
In addition to the method of manufacturing a group III nitride compound semiconductor according to any one of claims 5 to 5, by removing substantially all but the upper layer of the portion epitaxially grown laterally,
I characterized by obtaining a group III nitride compound semiconductor layer
This is a method for producing a group II nitride compound semiconductor.

[0015] The invention according to claim 9 provides the invention according to claim 8.
It is a group III nitride compound semiconductor substrate obtained by the method of (1).

[0016]

Functions and effects of the present invention The outline of the method for producing a group III nitride compound semiconductor of the present invention will be described with reference to FIG. Although FIG. 1 shows a diagram having a substrate 1 and a buffer layer 2 to assist the explanation and understanding of the dependent claims, the present invention relates to a group III nitride compound semiconductor having threading dislocations in the vertical direction. The purpose of the present invention is to obtain a group III nitride compound semiconductor layer having a region in which threading dislocations in the vertical direction are reduced, and the buffer layer 2 is not an essential element of the present invention. Hereinafter, on the surface of the substrate 1 formed via the buffer layer 2,
First having a threading dislocation in the vertical direction (perpendicular to the substrate surface)
An example in which the present invention is applied using the group III nitride-based compound semiconductor layer 31 will be used to explain the main effects of the present invention.

As shown in FIG. 1A, the first group III nitride-based compound semiconductor layer 31 is etched into an island state such as a dot, stripe or lattice, and a step is formed to provide a substrate 1 at the bottom. Is formed so as to expose the surface. Next, a mask 4 is formed on the exposed surface of the substrate 1. The upper surface 4a of the mask 4 is formed on the upper surface 31a of the first group III nitride compound semiconductor layer 31.
Lower than In this manner, the second group III nitride-based compound semiconductor 32 is epitaxially grown in the vertical and horizontal directions with the upper surface 31a and the side surface 31b of the upper portion of the step as nuclei, thereby filling the step portion, or forming a contact with the upper surface 4a of the mask 4. It can be grown upward while forming a gap between them. At this time, the second group III nitride compound semiconductor 32
In the upper part of the laterally epitaxially grown portion, the propagation of threading dislocations of the group III nitride-based compound semiconductor layer 31 is suppressed, and a region in which threading dislocations are reduced is formed in a buried or bridged step portion. (Claim 1).
Thereby, the lateral growth is immediately realized with the side surface of the step as a nucleus. That is, in the ELO using the conventional mask, the mask is thicker by the thickness of the mask than the portion serving as a nucleus for crystal growth. As a result, the crystal growth first grows in the vertical direction only to compensate for the thickness of the mask, and then goes around the upper surface of the mask and grows in the horizontal direction. As a result, the crystal is distorted due to the wraparound at the corner of the mask, which causes dislocation. In the present invention, first, instead of such wraparound growth on the mask, the second III
Since the group III nitride compound semiconductor 32 grows, no strain is applied to the crystal, and thus no dislocation occurs. Since the growth on the mask 4 is not caused by wraparound, the mask 4 and the second
Is not bonded to the group III nitride-based compound semiconductor 32?
It is considered to be weak and does not suffer from distortion from the mask 4. Furthermore, it is also possible to form a gap between the mask and the second group III nitride-based compound semiconductor 32 for growth. When growing with a gap,
It is possible to completely block the distortion from the mask,
This makes it possible to obtain high-quality crystals. Also, in the conventional ELO growth in which the wraparound growth is performed on the mask, the layers grown from the nuclei on both sides are united at the central portion.
It is known that the crystal axes on both sides are slightly tilted. This tilt is generated by forming a gap between the mask 4 and the second group III nitride compound semiconductor 32,
This can be prevented. As a result,
A higher quality lateral growth layer can be obtained.

In the portion growing in the horizontal direction, threading dislocations do not propagate in the vertical direction. III-nitride compound semiconductor layer 31 and buffer layer 2 and second III-nitride compound semiconductor 32
When there is almost no discontinuous surface due to epitaxial growth, when a conductor such as tungsten is used as a mask, it is longer in the vertical direction (normal direction to one surface of the substrate) than when a conductor is used as a mask. When current flows, no resistance is caused by discontinuous portions. Moreover, it can be made structurally stable.

At this time, if the second group III nitride-based compound semiconductor 32 that fills the step portion or bridges the step does not epitaxially grow in the vertical direction from the substrate 1 which is the bottom of the lower step, or if it is extremely slow, For example, it is much quicker to epitaxially grow laterally from the side surface of the step and to combine with the lateral epitaxial growth surface from the side surface of the opposing step. At this time, the part II that fills or bridges the step
Threading dislocations from the lower layer do not propagate at all above the group I nitride compound semiconductor 32. The side surface of the step is not necessarily required to be vertical, but when it is vertical, the threading dislocation density on this side surface is extremely low. Therefore, since the lateral growth is performed from the side surface where the threading dislocation density is extremely low, the threading dislocation density in the lateral growth region is significantly reduced. As a result, a very high quality crystal region can be obtained. As shown in FIG. 1 (c), the laterally grown portion combines the epitaxial growth from both sides, and when the growth is further continued, the second group III nitride compound grown uniformly thick on the substrate surface is obtained. A semiconductor 32 is obtained.
The bottom surface of the step does not need to be a substrate. The etching may be stopped at a certain depth of the first group III nitride compound semiconductor 31 or the intermediate surface of the semiconductor layer 31 may be exposed. further,
The intermediate surface of any of a plurality of layers constituting the base layer having at least the first group III nitride compound semiconductor 31 may be exposed as a bottom.

The mask is made of a polycrystalline semiconductor such as polycrystalline silicon or polycrystalline nitride semiconductor, silicon oxide (SiO _x ), silicon nitride, or the like.
(SiN _x ), oxides such as titanium oxide (TiO _x ) and zirconium oxide (ZrO _x ), nitrides, refractory metals such as titanium (Ti) and tungsten (W), and multilayer films of these Can be. A second group III nitride compound semiconductor 32 on the mask;
It is only necessary to use a substance that does not easily grow vertically (claims 2 and 5).

The above-described rapid lateral epitaxial growth can be easily realized when the side surface of the step of the group III nitride compound semiconductor layer 31 is a {11-20} plane (claim 3). At this time, for example, at least the upper part of the growth surface during the lateral epitaxial growth can be kept as the {11-20} plane. If the first group III nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition, rapid lateral epitaxial growth can be easily realized (claim 4).

According to the above method, threading dislocations propagating from the first group III nitride-based compound semiconductor layer 31 are suppressed, and the second group III nitride-based compound semiconductor 3 is structurally stable.
2 can be formed. Although FIG. 1 shows an example in which a step having a side surface perpendicular to the substrate surface is formed, the present invention is not limited to this, and the side surface of the step may be an oblique surface. At this time, there is no bottom at the bottom of the step, the cross section is V-shaped,
A mask may be formed thereon. These are the same in the following description.

By forming an element above the portion of the group III nitride-based compound semiconductor layer obtained in the above step which has been laterally epitaxially grown, a semiconductor element having a layer with few defects and high mobility is obtained. (Claim 6).

By forming a light-emitting device on a portion of the group III nitride-based compound semiconductor layer obtained in the above step which is laterally epitaxially grown, the life of the device or the LD is improved.
(Embodiment 7).

Further, by separating only the upper layer of the portion of the group III nitride-based compound semiconductor layer obtained in the above step which has been laterally epitaxially grown from other layers, the crystal in which crystal defects such as dislocations are significantly suppressed can be obtained. A group III nitride-based compound semiconductor having good properties can be obtained (claims 8 and 9).
In addition, a group III nitride compound semiconductor substrate having good crystallinity can be obtained. In addition, "substantially all removal" indicates that the present invention is included in the present invention even if it includes a part in which threading dislocation remains partly from the viewpoint of simplicity in production. In addition, by leaving only the laterally grown region of the second group III nitride compound semiconductor layer formed as described above, the region serving as the nucleus for crystal growth is etched to expose the substrate. Alternatively, the lateral growth may be repeatedly performed by exposing the intermediate surface of the base layer as described above. That is, the second lateral growth may be performed on the exposed surface of the mask with the mask being lower than the layer serving as a nucleus for crystal growth. In this case, since a crystal serving as a nucleus for crystal growth in the second lateral growth is formed by the lateral growth, the threading dislocation density is extremely low. Also has a lower threading dislocation density. In this way, it becomes possible to obtain a group III nitride compound semiconductor that has grown uniformly in the lateral direction on the substrate surface. The number of repetitions of these lateral growths is arbitrary.

[0026]

FIG. 1 shows an outline of an embodiment of a method for producing a group III nitride compound semiconductor according to the present invention. FIG. 1 shows an example in which the substrate 1 is exposed. A buffer layer 2 and a first group III nitride compound semiconductor layer 31 are formed on a substrate 1 and etched in a trench shape (FIG. 1A). At this time, a step occurs due to the etching, and the side surface and the bottom (lower step surface) of the step are formed with the surface that has not been etched as the upper step. The side surface is, for example, a {11-20} surface. Next, the mask 4 is formed only at the lower part of the step so as not to be higher than the upper part 31a of the step. For this formation, there is a formation method in which after a mask is uniformly formed by sputtering or the like, other portions are removed by photorefrography. Alternatively, a lift-off method may be used in which a resist is applied to the upper step 31a of the step, a mask is uniformly formed, and the resist is peeled off.

Next, under the condition of lateral epitaxial growth, the second group III nitride-based compound semiconductor 32 is epitaxially grown using the side and upper surfaces of the step as nuclei. If the organic metal growth method is used, lateral epitaxial growth can be easily performed while maintaining the growth surface at the {11-20} plane. Thus, if lateral growth of the side surface of the step occurs, the threading dislocation from the mask 4 does not propagate to that part of the second group III nitride compound semiconductor 32 (FIG. 1B). Thus, by setting the etching shape and the lateral epitaxial growth conditions so that the lateral growth on both side surfaces of the step unite above the etched portion, the etched second group III nitride-based compound is formed. A region in which threading dislocations are suppressed can be formed in the semiconductor 32 (FIG. 1C). In the lateral growth step of FIG. 1B, the growth temperature and pressure and the supply
By optimizing the III / V ratio, lateral growth can be much faster than vertical growth.

As shown in FIG. 2, a buffer layer formed on a substrate as a base layer, and a group III nitride-based compound semiconductor layer epitaxially grown on the buffer layer are separated by one.
As the period, a layer formed in a plurality of periods may be used as a nucleus of a crystal grown in the lateral direction. In FIG. 2, a buffer layer 21, a group III nitride compound semiconductor layer 22, a buffer layer 23, and a group III nitride compound semiconductor layer 31 are formed in this order, and the group III nitride compound semiconductor layer 31 is etched. An example is shown in which the buffer layer 23 is exposed at the bottom of the step. In this example, the first group III nitride-based compound semiconductor layer 3 with the mask 4 left on the buffer layer 23
1 is formed so as not to protrude from the upper surface 31a. Further, at the stage of the process as shown in FIG. 2A, etching is performed deeper than the thickness of the group III nitride compound semiconductor layer 31 so that the bottom of the step becomes the buffer layer 21.
(FIG. 3) in which the mask 4 is formed with a thickness that does not protrude from the upper surface of the group III nitride compound semiconductor layer 31. In any case, the group III nitride compound semiconductor layer 32 formed above the lower part of the step is mainly composed of the uppermost layer II of the upper part of the step.
A region formed by lateral epitaxial growth with the group I nitride-based compound semiconductor layer 31 as a nucleus and in which threading dislocations propagating in the vertical direction can be suppressed. Other effects are the same as those in the case of FIG.

The embodiment of the invention described above can be selected from each of the following.

When a group III nitride compound semiconductor is sequentially formed on a substrate, sapphire, silicon (Si), silicon carbide (SiC), spinel (MgAl ₂ O ₄ ), Zn
O, MgO or other inorganic crystal substrates, III-V group compound semiconductors such as gallium phosphide or gallium arsenide, or group III nitride compound semiconductors such as gallium nitride (GaN) can be used.

As a method for forming the group III nitride-based compound semiconductor layer, metal organic chemical vapor deposition (MOCVD or MOVPE) is preferable, but molecular beam vapor deposition (MBE), halide vapor deposition (Halide VPE). ), Liquid phase epitaxy (LPE) or the like may be used, and each layer may be formed by a different growth method.

For example, when laminating a group III nitride compound semiconductor on a sapphire substrate, in order to form it with good crystallinity,
It is preferable to form a buffer layer to correct lattice mismatch with the sapphire substrate. When using another substrate, it is desirable to provide a buffer layer. As the buffer layer, a group III nitride compound semiconductor Al _x Ga formed at a low temperature is used.
_y In _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), more preferably Al _x Ga _1-x N (0 ≦ x ≦ 1). This buffer layer may be a single layer or a multilayer having different compositions and the like. The buffer layer may be formed at a low temperature of 380 to 420 ° C.
It may be formed by a VD method. Alternatively, a buffer layer made of AlN can be formed by a reactive sputtering method using a high-purity metal aluminum and a nitrogen gas as raw materials using a DC magnetron sputtering apparatus. Similarly general formula _{Al x Ga y In 1-xy} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1, the composition ratio is optional) can form a buffer layer. Further, a vapor deposition method, an ion plating method, a laser ablation method, and an ECR method can be used. The buffer layer formed by physical vapor deposition is desirably formed at 200 to 600 ° C.
More preferably, the temperature is 300 to 500 ° C, and more preferably,
350-450 ° C. When a physical vapor deposition method such as these sputtering methods is used, the thickness of the buffer layer is 100 to 3
000Å is desirable. More preferably, it is 100 to 400 °, most preferably 100 to 300 °. As the multilayer, for example, a layer composed of Al _x Ga _1-x N (0 ≦ x ≦ 1) and GaN
There is a method in which layers are alternately formed, and layers having the same composition are alternately formed at a formation temperature of, for example, 600 ° C. or lower and 1000 ° C. or higher. Of course, these may be combined, and the multilayer is composed of three or more group III nitride-based compound semiconductors Al _x Ga _y In
_1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) may be stacked. Generally, the buffer layer is amorphous and the intermediate layer is single crystal. A plurality of cycles may be formed with the buffer layer and the intermediate layer as one cycle, and the repetition may be an arbitrary cycle. The more repetitions, the better the crystallinity.

In the group III nitride compound semiconductor of the buffer layer and the upper layer, part of the group III element composition may be replaced with boron (B) or thallium (Tl), or the composition of nitrogen (N) may be reduced. Parts are phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi)
The present invention can be substantially applied even if it is replaced by. Further, these elements may be doped to such an extent that they cannot be displayed in composition. For example, a group III nitride-based compound semiconductor having no indium (In) or arsenic (As) in the composition of Al _x Ga _1-x N (0
≦ x ≦ 1), by doping aluminum (Al), indium (In) having a larger atomic radius than gallium (Ga), or arsenic (As) having a larger atomic radius than nitrogen (N), a nitrogen atom The crystal distortion may be improved by compensating for the expansion strain of the crystal due to the loss of the crystal with the compression strain. In this case, the acceptor impurity is III
A p-type crystal can also be obtained by as-grown since it easily enters the position of the group atom. By improving the crystallinity in this way, threading dislocations can be further reduced to about 100 to 1000 times in accordance with the present invention. In the case of a base layer in which the buffer layer and the group III nitride compound semiconductor layer are formed in two or more periods, when each group III nitride compound semiconductor layer is doped with an element having a larger atomic radius than the main constituent element, good. In the case where the light emitting device is configured as a light emitting device, a binary system of a group III nitride-based compound semiconductor,
Alternatively, it is desirable to use a ternary system.

When an n-type group III nitride compound semiconductor layer is formed, Si, Ge, Se, Te,
A group IV element or a group VI element such as C can be added. Examples of p-type impurities include Zn, Mg, Be, Ca, Sr, and Ba.
A Group IV element or a Group IV element can be added. These may be doped with plural or n-type impurities and p-type impurities in the same layer.

As the lateral epitaxial growth, it is preferable that the growth surface is perpendicular to the substrate, but it is also possible to grow the crystal while keeping the facet surface oblique to the substrate. At this time, the cross section may have a V-shaped section without a bottom surface at the bottom of the step. In the case of a vertical plane, the threading dislocation density is extremely low, so that the crystallinity of the lateral growth region is improved. If the facet is inclined, threading dislocations are bent and threading dislocations are also formed in the lateral growth region. A thicker layer has a lower threading dislocation density.

As for the lateral epitaxial growth, it is more preferable that at least the upper part of the lateral epitaxial growth surface and the substrate surface are perpendicular to each other, and it is more preferable that all of them are {11-20} planes of a group III nitride compound semiconductor. Is more desirable.

At the time of etching, due to the relationship between depth and width, steps are provided so as to be closed or cross-linked by lateral epitaxial growth.

The base layer is composed of multiple layers, for example, AlN, Al _x Ga
_1-x N or the _{Al x Ga y In 1-xy} N (x ≠ 0) consists of a layer, the first
If GaN is used as the Group III nitride compound semiconductor of
The layer made of N, Al _x Ga _1-x N or Al _x Ga _y In _1-xy N (x ≠ 0) acts as a stopper layer during plasma etching containing chlorine such as Cl ₂ or BCl ₃ , so that a step is formed. It is convenient to adjust the depth of the light. The same applies to the case where the buffer layer and the group III nitride compound semiconductor layer are repeated at an arbitrary period as the uppermost buffer layer of the base layer and the layer is etched so as to expose this layer. This makes it possible to easily set conditions for suppressing the vertical growth from the mask and promoting the lateral growth from the side surface of the first group III nitride compound semiconductor layer. This facilitates the design of the step and makes it possible to reduce the depth of the step. When the depth is shallow, it is considered that the growth process of growing from the upper surface of the first group III nitride-based compound semiconductor layer and growing laterally becomes dominant. In any case, lateral growth is possible on the mask.

When the crystal axis direction of the group III nitride-based compound semiconductor layer laminated on the substrate can be predicted, the a-plane ({11-20} plane) or m-plane (｛ It is useful to perform masking or etching in a stripe shape so as to be perpendicular to the (1-100 ° plane). The stripes and the mask may be arbitrarily designed in an island shape, a lattice shape, or the like. The lateral epitaxial growth surface may be a growth surface that is perpendicular to the substrate surface or a growth surface that is oblique to the substrate surface. To make the (11-20) plane the lateral epitaxial growth plane as the a-plane of the group III nitride compound semiconductor layer, for example, the longitudinal direction of the stripe is the m plane of the group III nitride compound semiconductor layer (1-100). ) Perpendicular to the plane. For example, when the substrate is the a-plane or the c-plane of sapphire, in both cases, the m-plane of sapphire is formed thereon.
Since it usually coincides with the a-plane of the group I nitride-based compound semiconductor layer, etching is performed accordingly. Also in the case of a point-like, lattice-like, or other island-like shape, it is preferable that each surface forming the contour (side wall) is a {11-20} plane.

The mask is made of a polycrystalline semiconductor such as polycrystalline silicon or a polycrystalline nitride semiconductor, silicon oxide (SiO _x ), silicon nitride (S
iN _x ), oxides such as titanium oxide (TiO _x ) and zirconium oxide (ZrO _x ), nitrides, refractory metals such as titanium (Ti) and tungsten (W), and multilayer films of these it can. These film forming methods are optional in addition to vapor deposition methods such as vapor deposition, sputtering, and CVD. This material can also be used for a mask used to leave the first group III nitride compound semiconductor layer. Note that the mask used for etching is removed during the lateral growth to expose the upper surface of the first group III nitride-based compound semiconductor layer.

When etching is performed, reactive ion etching (RIE) is desirable, but any etching method can be used. Instead of forming a step having a side surface perpendicular to the substrate surface, an anisotropic etching may be used to form, for example, a V-shaped section having no bottom surface at the bottom of the step.

Having a region in which the threading dislocation is suppressed.
Semiconductor elements such as FETs and light-emitting elements can be formed over the entire group III nitride-based compound semiconductor or over a region where threading dislocations are suppressed. In the case of a light-emitting element, the light-emitting layer may have a homo-structure, a hetero-structure, or a double-hetero structure in addition to a multiple quantum well structure (MQW) and a single quantum well structure (SQW). May be formed.

The above-described group III nitride compound semiconductor having a region in which threading dislocation is suppressed is removed by removing, for example, the substrate 1, the buffer layer 2, and a portion where a step is formed by etching to prevent threading dislocation. And a group III nitride-based compound semiconductor substrate. A group III nitride compound semiconductor element can be formed thereon, or can be used as a substrate for forming a larger group III nitride compound semiconductor crystal. The removal method is optional in addition to the mechanochemical polishing.

Hereinafter, description will be made based on specific embodiments of the present invention. Although a light-emitting device will be described as an example, the present invention is not limited to the following example, and discloses a method of manufacturing a group III nitride compound semiconductor applicable to any device.

The group III nitride compound semiconductor of the present invention is:
It was manufactured by vapor phase growth by metal organic compound vapor phase epitaxy (hereinafter referred to as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ or N ₂ ), trimethylgallium (Ga (CH ₃ ) ₃ , hereinafter referred to as “TMG”) and trimethylaluminum (Al (CH ₃ ) ₃ , Hereinafter, referred to as “TMA”, trimethylindium (In (CH ₃ ) ₃ , hereinafter referred to as “TMI”), cyclopentadienyl magnesium (Mg (C
₅ H _{5) 2,} which is hereinafter referred to as "Cp ₂ Mg").

[First Embodiment] FIG. 1 shows the steps of this embodiment. The temperature was lowered to 400 ° C., H ₂ was 10 L / min, NH ₃ was 5 L / min, and TMA was 20 μmol on the single crystal sapphire substrate 1 with the a-plane cleaned by organic cleaning and heat treatment as the main surface.
The buffer layer 2 of AlN was formed at a thickness of about 40 nm by supplying at about / min for about 3 minutes. Next, the temperature of the sapphire substrate 1 is set to 1000 ° C.
Held in, 300 [mu] mol of H ₂ 20L / min, the NH ₃ 10L / min, and TMG
/ min to form a GaN layer 31 having a thickness of about 0.5 μm.

Using a hard bake resist mask,
By selective dry etching using reactive ion etching (RIE), etching was performed in a stripe shape having a width of 10 μm, an interval of 10 μm, and a depth of 0.5 μm. Thereby, the GaN layer 3
The upper part of the substrate 1 having a width of 10 μm and a step of 0.5 μm and the exposed substrate 1 having a width of 10 μm were alternately formed (FIG. 1A). At this time, the side surface on which a step having a depth of 0.5 μm was formed was the {11-20} surface of the GaN layer 31.

Next, a silicon dioxide film (SiO ₂ ) was uniformly formed by sputtering. After that, a resist was applied, and a photorefgraph process was performed. The resist was left in a portion where the silicon dioxide film was left, and a portion not covered with the resist was wet-etched. As a result, a wafer having the structure shown in FIG. 1A was obtained.

Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H ₂ was 20 L / min, NH ₃ was 10 L / min, and TMG was 2 μmol / min.
And a GaN layer 32 was formed by lateral epitaxial growth with the {11-20} plane, which is the side surface on which a step having a depth of 0.5 μm is formed, of the GaN layer 31 as a nucleus. At this time, there was almost no vertical growth on the upper surface of the step, and no vertical growth from the mask 4 at the bottom (FIG. 1B). In this manner, steps are filled by lateral epitaxial growth mainly with the {11-20} plane as the growth plane, or a crosslinked structure having a small gap between the mask 4 and the mask 4 is obtained, and the surface becomes flat (FIG. 1). (C)). Thereafter, the H ₂ 20L / min, the NH ₃ 10L /
The GaN layer 32 was grown by introducing min and TMG at 300 μmol / min, and the GaN layer 31 and the GaN layer 32 were made to have a total thickness of 3 μm.
In the portion of the GaN layer 32 formed above the bottom of the step having a depth of 0.5 μm of the GaN layer 31, threading dislocation was significantly suppressed as compared with the portion formed above the top of the step.

[Second Embodiment] In this embodiment, a base layer composed of multiple layers as shown in FIG. 2 is used. With the a-plane cleaned by organic cleaning and heat treatment as the main surface, the temperature was lowered to 400 ° C. on the single-crystal sapphire substrate 1 to reduce H ₂ to 10 L / min.
Supply NH ₃ at 5 L / min and TMA at 20 μmol / min for about 3 minutes to
AlN layer (first buffer layer) 21 was formed to a thickness of about 40 nm. Next, the temperature of the sapphire substrate 1 is maintained at 1000 ° C.
Of H ₂ was introduced 20L / min, the NH ₃ 10L / min, and TMG at 300 [mu] mol / min, to form the GaN layer having a thickness of about 0.3μm (intermediate layer) 22.
Next, the temperature was lowered to 400 ° C., H ₂ was 10 L / min, NH ₃ was 5
L / min and TMA at 20 μmol / min for about 3 minutes to feed the second AlN
The layer (second buffer layer) 23 was formed to a thickness of about 40 nm. Then, maintaining the temperature of the sapphire substrate 1 to 1000 ° C., the H ₂ 20
L / min, NH ₃ were introduced at 10 L / min, and TMG was introduced at 300 μmol / min to form a GaN layer 31 having a thickness of about 0.5 μm. Thus, a film thickness of about 4
0 nm first AlN layer (first buffer layer) 21, thickness about 0.3 μm
A GaN layer (intermediate layer) 22, a second AlN layer (second buffer layer) 23 having a thickness of about 40 nm, and a GaN layer 31 having a thickness of about 0.5 μm. Generally, the buffer layer is amorphous and the intermediate layer is single crystal. A plurality of cycles may be formed with the buffer layer and the intermediate layer as one cycle, and the repetition may be an arbitrary cycle. The more repetitions, the better the crystallinity.

Next, using a hard bake resist mask, selective dry etching using reactive ion etching (RIE) was performed to obtain a width of 10 μm, an interval of 10 μm, and a depth of 0.5 μm.
Etching was performed in a stripe shape of μm. With this, GaN
The upper part of the layer 31 having a width of 10 μm and the step difference of 0.5 μm and the exposed second AlN layer 23 having a width of 10 μm (bottom part of the lower part) were formed alternately (FIG. 2). At this time, the side surface on which a step having a depth of 0.5 μm was formed was the {11-20} surface of the GaN layer 31.

Next, a mask 4 was formed on the second AlN layer 23 in the same manner as in the first embodiment. The thickness of the mask 4 is a thickness at which the mask does not come out on the GaN layer 31.

Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H ₂ was 20 L / min, NH ₃ was 10 L / min, and TMG was 2 μmol / min.
And a GaN layer 32 was formed by lateral epitaxial growth with the {11-20} plane, which is the side surface on which a step having a depth of 0.5 μm is formed, of the GaN layer 31 as a nucleus. At this time, there was almost no vertical growth from the upper surface of the step. Also, there was no vertical growth on the bottom mask 4. In this way, the steps were filled by the lateral epitaxial growth mainly with the {11-20} plane as the growth plane, or a lateral growth region of a crosslinked structure was obtained, and the surface became flat. After this, H ₂
20 L / min, NH ₃ was introduced at 10 L / min, TMG was introduced at 300 μmol / min,
The GaN layer 32 is grown, and the GaN layer 31 and the GaN layer 32 are
The thickness was set to μm. 0.5 μm in depth of the GaN layer 31 of the GaN layer 32
In the portion formed above the bottom of the step m, threading dislocations were significantly suppressed as compared with the portion formed above the top of the step.

[Third Embodiment] In this embodiment, as in the second embodiment, a first AlN film having a thickness of about 40 nm is formed on a sapphire substrate 1.
Layer (first buffer layer) 21, GaN layer (intermediate layer) 22 with a thickness of about 0.3 μm, second AlN layer (second buffer layer) with a thickness of about 40 nm
23, after forming the base layer 20 composed of the GaN layer 31 having a thickness of about 0.5 μm, etching about 0.8 μm to form the GaN layer 3
1 is the uppermost layer, width 10μm, upper step 0.8μm, width 1
The exposed first AlN layers 21 (lower bottom portion) of 0 μm were alternately formed (FIG. 3). At this time, the side surface on which the step having a depth of 0.8 μm was formed was the {11-20} plane of the GaN layer 31, the second AlN layer (second buffer layer) 23, and the GaN layer (intermediate layer) 22. The mask 4 is formed on the first AlN layer 21 so as not to protrude above the GaN layer 31. In this manner, lateral epitaxial growth mainly with the {11-20} plane as the growth surface is performed in the same manner as in the second embodiment, and after the surface is flattened, the GaN layer 32 is grown. To a total thickness of 3 μm. GaN layer 32, GaN layer 31, second
AlN layer (second buffer layer) 23 and GaN layer (intermediate layer) 22
In the portion formed above the mask 4 at the bottom of the step having a depth of about 0.8 μm, threading dislocations were significantly suppressed as compared with the portion formed above the upper surface of the step.

[Fourth Embodiment] In the present embodiment, in forming the GaN layer 31 in the first embodiment, Ga is doped by TMI.
N: In layer 31 The doping amount of indium (In) is about 1 × 1
It was set to 0 ¹⁶ / cm ³ . Thereafter, etching and lateral epitaxial growth of GaN were performed in substantially the same manner as in the first embodiment (FIG. 4). GaN: GaN grown laterally with In layer 31 as the core
In the layer 32, threading dislocations were slightly smaller than those of the first embodiment. Also, GaN grown vertically on the GaN: In layer 31
The layer 32 has a threading dislocation of about 1/1 compared to that of the first embodiment.
Reduced to 00.

Fifth Embodiment A laser diode (LD) 100 shown in FIG. 5 was formed on a wafer formed in the same manner as in the first embodiment above the lateral growth region as follows. However, when forming the GaN layer 32, silane (SiH ₄ ) was introduced to make the GaN layer 32 a layer made of silicon (Si) doped n-type GaN. It should be noted that the GaN layer 31 and the G
The aN layer 32 is simply referred to as the GaN layer 103.

A sapphire substrate 101, a buffer layer 102 made of AlN, and a two-stage GaN layer 103 consisting of a GaN layer and an n-type GaN layer
Silicon (Si) doped Al _0.08 Ga
_0.92 N clad layer 104, silicon (Si) doped GaN n guide layer 105, MQW structure light emitting layer 106, magnesium (Mg) doped GaN p guide layer 107, magnesium (Mg) doped Al _0.08 Ga _0.92
A p-cladding layer 108 made of N and a p-contact layer 109 made of GaN doped with magnesium (Mg) were formed. Next, an electrode 110 made of gold (Au) is formed on the p-contact layer 109.
A was partially etched until the two-stage GaN layer 103 of the GaN layer and the n-type GaN layer was exposed, thereby forming an electrode 110B made of aluminum (Al). Laser diode (LD) 10
The essential part of the element portion of No. 0 was formed in the region where the threading dislocation was suppressed, which was above the lateral epitaxial growth region of the GaN layer 103. The laser diode (LD) 100 thus formed has remarkably improved device life and luminous efficiency.

Sixth Embodiment A light emitting diode (LED) 200 shown in FIG. 6 was formed on the wafer in the same manner as the first embodiment above the lateral growth region on the wafer as follows. However, when forming the GaN layer 32, silane (SiH ₄ ) was introduced to make the GaN layer 32 a layer made of silicon (Si) doped n-type GaN. It should be noted that the GaN layer 31 and the G
The aN layer 32 is simply referred to as the GaN layer 203.

A sapphire substrate 201, a buffer made of AlN
A GaN layer 203 including a GaN layer and an n-type GaN layer.
Silicon (Si) -doped Al_0.08Ga
_0.92N cladding layer 204, light emitting layer 205,
Gnesium (Mg) doped Al_0.08Ga _0.92P class consisting of N
Pad layer 206, made of magnesium (Mg) doped GaN
A p-contact layer 207 was formed. Next, p contact layer
An electrode 208A made of gold (Au) is formed on the GaN layer
Etching until the two-stage GaN layer 203 of the p-type GaN layer is exposed
To form an electrode 208B made of aluminum (Al)
did. The light emitting diode (LE) formed in this manner
D) 200 markedly improved device life and luminous efficiency.

[Seventh Embodiment] In this embodiment, n is used as the substrate.
A mold silicon (Si) substrate was used. n-type silicon (Si) substrate 3
01 at a temperature 1150 ° C. on the H ₂ 10L / min, the NH ₃ 10L / min, T
MG to 100 [mu] mol / min, TMA and 10 .mu.mol / min, the H ₂ gas 0.
Silane (SiH ₄ ) diluted to 86 ppm was supplied at 0.2 μmol / min, and silicon (Si) -doped Al _0.15 Ga _0.85 N having a thickness of 0.5 μm was supplied.
Was formed. Next, using a hard bake resist mask, reactive ion etching (R
10 μm width by selective dry etching using IE)
m, an interval of 10 μm, and a depth of 0.5 μm. Thus, the width 10 of n-Al _0.15 Ga _{0.8 5} N layer 3021
The upper stage of 0.5 μm and the step difference of 0.5 μm and the lower stage (bottom) of the exposed n-type silicon substrate 301 having a width of 10 μm were alternately formed (FIG. 7A). At this time, the side surface on which the step having a depth of 0.5 μm is formed is the {11-2} of the n-Al _0.15 Ga _0.85 N layer 3021.
0 ° plane.

Next, a mask 5 made of tungsten was formed on the bottom of the step so as not to be exposed on the upper surface of the layer 3021 made of Al _0.15 Ga _0.85 N. n-type silicon substrate 3
01 at 1150 ° C., H ₂ at 20 L / min, NH ₃ at 10 L / min.
min, TMG and 2 [mu] mol / min, TMA and 0.2 .mu.mol / min, silane diluted with H ₂ gas (SiH ₄₎ was supplied with 4 nmol / min, nA
l _0.15 Ga _0.85 n-Al _0.15 Ga _0.85 with the {11-20} plane serving as a nucleus as a side surface forming a step having a depth of 0.5 μm of the N layer 3021
The N layer 3022 was formed by lateral epitaxial growth. At this time, vertical epitaxial growth from the mask 5 on the top and bottom of the step hardly occurred (FIG. 7B). Thus, the step was filled or the structure became a crosslinked structure by the lateral epitaxial growth mainly with the {11-20} plane as the growth plane, and the surface became flat. After this,
The H ₂ 10L / min, the NH ₃ 10L / min, a TMG 100μmol / min, TMA
10 μmol / min, silane (SiH ₄ ) diluted with H ₂ gas
Is supplied at 0.2 μmol / min, and the n-Al _0.15 Ga _0.85 N layer 3022 is supplied.
Is grown, and the n-Al _0.15 Ga _0.85 N layer 3021 and the n-Al _0.15 Ga
_The total thickness of the _0.85 N layer 3022 was 2 μm (FIG. 7C). Hereinafter, an n-Al _0.15 Ga _0.85 N layer 3 having a thickness of 2 μm
021 and the n-Al _0.15 Ga _0.85 N layer 3022 together with the n-Al
Described as _0.15 Ga _0.85 N layer 302.

As described above, on the n-Al _0.15 Ga _0.85 N layer 302 formed on the n-type silicon substrate 301, an n guide layer 303 made of GaN doped with silicon (Si), a light emitting layer 304 having an MQW structure, Mg) doped GaN p
Guide layer 305, magnesium (Mg) doped Al _0.08 Ga
_0.92 N p cladding layer 306, magnesium (Mg)
A p-contact layer 307 made of doped GaN was formed. Next, an electrode 308A made of gold (Au) is formed on the p-contact layer 307, and aluminum (Au) is formed on the back surface of the silicon substrate 301.
An electrode 308B comprising l) was formed (FIG. 8). The main part of the element part of the laser diode (LD) 300 is n-Al _0.15 Ga
It was formed in a region where threading dislocations were suppressed, which was above the lateral epitaxial growth region of the _0.85 N layer 302. The laser diode (LD) 300 formed in this way has significantly improved element life and luminous efficiency.

[Eighth Embodiment] In this embodiment, n is used as the substrate.
A mold silicon (Si) substrate was used. Similar to the n-Al _0.15 Ga _0.85 N layer 302 formed on the n-type silicon substrate 301 of the seventh embodiment, the n-Al _0.15
A wafer having a Ga _0.85 N layer 402 was prepared, and a light-emitting layer 403 and a p-cladding layer 404 made of magnesium (Mg) -doped Al _0.15 Ga _0.85 N were formed. Next, an electrode 405A made of gold (Au) was formed on the p-cladding layer 404, and an electrode 405B made of aluminum (Al) was formed on the back surface of the silicon substrate 401 (FIG. 9). The light emitting diode (L
ED) 400 has significantly improved device life and luminous efficiency.

[Application] As an application example of the present invention, the second Ga
It is also useful to further etch the region of the N layer 32 where threading dislocations are not reduced, and to further laterally epitaxially grow the GaN layer. FIG. 10 shows the first GaN layer 31,
FIG. 4 is a schematic view of a position where a second GaN layer 32 is etched. As shown in FIG. 10A, etching is performed in a stripe shape to form a portion of the GaN layer 31 (hatched in the figure) above the step and the bottom of the step indicated by B. The formation of the mask 4 is the same as in the first embodiment. As shown in FIG. 10B, the GaN layer 32 filling the step on the mask indicated by B in FIG. To form A mask is formed only in this lower part. This mask also has a thickness that does not protrude from the uppermost surface of the layer formed on the substrate.
Thus, the second GaN layer 3 in which the GaN layer 33 is located above the step
FIG. 10 shows that lateral epitaxial growth with
As shown in (c), the region indicated by 31 which is a portion where threading dislocations are propagated from the GaN layer 31, the threading dislocations are suppressed in the upper part of the GaN layer 32 grown laterally epitaxially 3
A region indicated by 2 and a region indicated by 33 in which threading dislocations are suppressed are formed above the GaN layer 33 grown laterally epitaxially. As a result, it is possible to form a region in which threading dislocations are reduced over almost the entire surface of the wafer. The etching depth of the GaN layer 32 may be arbitrary. As a result, threading dislocations are suppressed over the entire surface II
A group I nitride compound semiconductor substrate can also be obtained.

[Modification of Etching] FIG.
This is an example in which the upper step of the step is formed in an island shape by the {11-20} planes of the set. FIG. 11A shows three sets of $ 11-2.
Although the outer periphery formed by the 0 ° plane is also shown, this is a simplified schematic diagram for the sake of understanding, and in practice, tens of millions of island-shaped upper steps may be formed per wafer. In FIG. 11A, the bottom B of the step has three times the area of the top of the island-shaped step. In FIG. 11B, the bottom B of the step has an area eight times that of the top of the island-shaped step.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a group III nitride compound semiconductor according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing the structure of a group III nitride compound semiconductor light emitting device according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a part of a manufacturing process of a group III nitride compound semiconductor light emitting device according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to a seventh embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a group III nitride compound semiconductor light emitting device according to an eighth embodiment of the present invention.

FIG. 10 is a schematic view showing another example of etching of the first group III nitride compound semiconductor.

FIG. 11 is a schematic view showing still another example of etching the first group III nitride compound semiconductor.

FIG. 12 is a cross-sectional view showing threading dislocations propagating in a group III nitride compound semiconductor.

[Explanation of symbols]

 1, 101, 201, 301, 401 Substrate 2, 102, 202 Buffer layer 20 Base layer 21 First buffer layer forming base layer 22 Intermediate layer forming base layer 23 Second buffer layer forming base layer 31 1 group III nitride compound semiconductor (layer) 32 second group III nitride compound semiconductor (layer) 103, 203 n-GaN layer 104, 204, 302, 402 n-AlGaN cladding layer 105, 303 n- GaN guide layers 106, 205, 304, 403 Emitting layers 107, 305 p-GaN guide layers 108, 206, 306, 404 p-AlGaN cladding layers 109, 207, 307 p-GaN layers 110A, 208A, 308A, 405A p-electrodes 110B, 208B, 308B, 405B n-electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshio Hiramatsu 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. 4G077 AA03 AB02 BE11 BE15 DA05 DB08 EF03 EH03 HA06 5F041 AA40 CA04 CA05 CA23 CA34 CA40 CA46 CA77 5F045 AA04 AB09 AB14 AB17 AC01 AC08 AC12 AD08 AD14 AD15 AF03 AF04 AF09 AF20 BB12 BB3 AA45 AA74 CA07 CB05 CB07 DA05 DA06 DA07 DA25 DA35 EA29

Claims (9)

[Claims] 1. A method for producing a group III nitride compound semiconductor by epitaxially growing a group III nitride compound semiconductor on a substrate, comprising: at least one layer of a group III nitride compound semiconductor; The base layer to be a group III nitride-based compound semiconductor is formed into an island state such as a dot, a stripe, or a lattice by etching, and a step is formed so as to expose the surface of the intermediate portion of the base layer or the surface of the substrate to the bottom. Providing, a step of forming a mask on the bottom of the step with a thickness such that an upper surface is at a position lower than the upper surface of the uppermost layer, and a dot, stripe, grid, or the like formed by the etching. The upper surface and the side surface of the upper step of the first group III nitride compound semiconductor in an island state are used as nuclei, and the second
Growing the group III nitride-based compound semiconductor vertically and horizontally. 2. The method according to claim 1, wherein the mask is made of a material on which the epitaxial growth of the group III nitride compound semiconductor is inhibited. 3. The side surface of the step is substantially entirely # 11-2.
The method for producing a group III nitride-based compound semiconductor according to claim 1, wherein the plane is a 0 ° plane. 4. The semiconductor device according to claim 1, wherein the first group III nitride compound semiconductor and the second group III nitride compound semiconductor have the same composition.
A method for producing a group I nitride compound semiconductor. 5. The semiconductor device according to claim 1, wherein the mask is a silicon oxide film, a silicon nitride film, a tungsten, a titanium nitride film, or another conductive mask. The method for producing a group III nitride compound semiconductor according to the above. 6. An upper layer of a part of the group III nitride-based compound semiconductor layer produced by the method for producing a group III nitride-based compound semiconductor according to claim 1, which is laterally epitaxially grown. A group III nitride-based compound semiconductor device, characterized in that the device is formed as follows. 7. A portion of the III-nitride compound semiconductor layer produced by the method for producing a III-nitride compound semiconductor according to claim 1, wherein the portion of the III-nitride compound semiconductor layer is laterally epitaxially grown. A group III nitride compound semiconductor light-emitting device obtained by laminating different group III nitride compound semiconductor layers on an upper layer. 8. In addition to the method of manufacturing a group III nitride-based compound semiconductor according to any one of claims 1 to 5, by removing substantially all but the upper layer of the laterally epitaxially grown portion. A method for producing a group III nitride compound semiconductor substrate, comprising obtaining the group III nitride compound semiconductor substrate. 9. A group III nitride compound semiconductor substrate obtained by the method of claim 8.