JP6011254B2 - Electronic component having joint with solder alloy containing Bi as main component - Google Patents

Description

  The present invention relates to an electronic component having a joint portion that is joined using a Pb-free solder alloy, and particularly has a joint portion that is joined using a Pb-free solder alloy mainly composed of Bi that is suitable as a high-temperature solder alloy. It relates to electronic components.

  In recent years, regulations on chemical substances harmful to the environment have become stricter, and this regulation is no exception for solder materials used for the purpose of joining electronic components and the like to a substrate. Pb (lead) has been used as a main component for solder materials for a long time, but it has already been regulated by the RoHS directive. For this reason, Pb-free solder has been actively developed.

  Solders used when bonding electronic components to a substrate are roughly classified into high temperature (about 260 ° C. to 400 ° C.) and medium / low temperature (about 140 ° C. to 230 ° C.) depending on the limit temperature of use. As for a solder alloy for medium and low temperatures (about 140 to 230 ° C.), a Pb-free solder alloy containing Sn as a main component has already been put into practical use. For example, in Patent Document 1, Sn is the main component, Ag is 1.0 to 4.0 mass%, Cu is 2.0 mass% or less, Ni is 0.5 mass% or less, and P is 0.2 mass%. % Pb-free solder alloy is described. Patent Document 2 describes a Pb-free solder alloy containing 0.5 to 3.5% by mass of Ag, 0.5 to 2.0% by mass of Cu, and the balance being Sn.

  On the other hand, development of various high-temperature solder alloys has been carried out in various organizations in order to realize Pb-free. For example, Patent Document 3 discloses a Bi / Ag brazing material containing 30 to 80% by mass of Bi and having a melting temperature of 350 to 500 ° C. However, since the Bi / Ag brazing material described in Patent Document 3 has a high liquidus temperature of 400 to 700 ° C., the working temperature at the time of bonding is estimated to be 400 to 700 ° C. or higher, and the electronic device to be bonded It is thought that the temperature exceeds the temperature that the substrate can withstand.

Japanese Patent Laid-Open No. 11-077366 JP-A-8-215880 JP 2002-160089 A

  Although high-temperature Pb-free solder materials have been developed by various organizations as described above, generally high-temperature solder has high solidus temperature, moderate liquidus temperature, low-temperature and high-temperature heat. Many characteristics such as high durability against cycles, good thermal stress relaxation characteristics, and good wetting and spreading properties are required. For this reason, the actual situation is that a solder material having characteristics that are sufficiently satisfactory in terms of practical use has not yet been found.

  The present invention has been made in view of the above-described conventional circumstances, and is used for solder bonding in an electronic component such as a Si chip having a bonding portion bonded using Bi-based Pb-free solder containing Bi as a main component. It aims at obtaining high joint reliability by making the wettability and joining property excellent at the time.

  In order to achieve the above object, the present inventor examined means for improving wettability and bondability due to factors other than the solder composition, and as a result of focusing on the state of the solder joint surface in the electronic component, the surface roughness of the joint surface was In addition, the present inventors have found that the thickness of the oxide layer existing on the bonding surface and the wettability and bonding properties have a great influence on the wettability and bonding properties.

That is, the electronic component of the first embodiment of the present invention contains 5.0% by mass or less of one or more of Zn, Al, Sn, Sb, and P, with the balance being Bi, and a solder alloy. It has a joint part joined by a solder alloy containing Bi in an amount of 85% by mass or more, and the uppermost layer of the joint part is mainly composed of any one of Au, Ag, Ni and Cu, The center line average roughness of the upper layer solder joint surface is 1.0 μm or more and 5.0 μm or less.

The electronic component according to the second embodiment of the present invention contains 5.0% by mass or less of one or more of Zn, Al, Sn, Sb, and P, the balance being Bi, and a solder alloy. It has a joint part joined by a solder alloy containing Bi in an amount of 85% by mass or more, and the uppermost layer of the joint part is mainly composed of any one of Au, Ag, Ni, and Cu, and from the surface Oxygen depth at the depth of 1000 nm is reduced to 0%, the maximum oxygen concentration between the surface and 1000 nm depth is set to 100%, and the depth of penetration from the surface where the oxygen concentration is reduced to 10% is oxidized. When defined as the thickness of the physical layer, the solder joint surface of the uppermost layer is covered with an oxide layer having a thickness of 0.2 nm to 30 nm.

Furthermore, the electronic component according to the third embodiment of the present invention contains 5.0% by mass or less of one or more of Zn, Al, Sn, Sb, and P, with Bi being Bi as the balance , and solder. The entire alloy has a joint part joined by a solder alloy containing Bi of 85% by mass or more, and the uppermost layer of the joint part is mainly composed of any one of Au, Ag, Ni and Cu, The center line average roughness of the solder joint surface of the uppermost layer is 1.0 μm or more and 5.0 μm or less, and the oxygen content of the portion entering 1000 nm in the depth direction from the surface is reduced to 0% and the depth from the surface is 1000 nm. When the maximum oxygen concentration during the period is defined as 100% and the penetration depth from the surface where the oxygen concentration is reduced to 10% is defined as the thickness of the oxide layer, the solder joint surface of the uppermost layer has a thickness of 0.2 nm or more. Cover with oxide layer of 30nm or less It is characterized in that it is.

In addition, the electronic device manufacturing method according to the present invention is applicable to an electronic component having a solder joint whose uppermost layer is mainly composed of any one of Au, Ag, Ni, and Cu. , Sb, and P are each contained in an amount of 5.0% by mass or less, the remainder is Bi, and solder is soldered using a solder alloy containing 85% by mass or more of Bi in the entire solder alloy. A method of manufacturing an apparatus, wherein the center line average roughness of the solder joint surface of the uppermost layer is 1.0 μm or more and 5.0 μm or less, or the amount of oxygen in a portion entering 1000 nm in the depth direction from the surface is measured. When the depth of penetration from the surface where the maximum oxygen concentration between the surface and the depth of 1000 nm from the surface is set to 100% and the oxygen concentration is reduced to 10% is defined as the thickness of the oxide layer, The solder joint surface of It is covered with an oxide layer having a thickness of 0.2 nm or more and 30 nm or less, or the center line average roughness of the solder joint surface is 1.0 μm or more and 5.0 μm or less, and the solder joint surface is defined above It is characterized by being covered with an oxide layer having a thickness of 0.2 nm to 30 nm.

  According to the present invention, even when Bi-based Pb-free solder is used for solder bonding of electronic components, solder bonding excellent in wettability and bondability can be realized, and thus has high bonding reliability. An electronic device can be obtained.

It is a graph explaining the definition of the thickness of an oxide layer.

  In electronic devices and substrates such as Si chips, SiC chips, and GaN chips, if the surface roughness of the joint with the solder is large or the oxide layer formed on the surface is thick, the wettability of the solder is significantly reduced. Resulting in. That is, if the surface is rough, the substantial surface area of the solder joint surface increases, so that the oxides and the like present at the interface between the solder joint portion of the electronic component and the solder increase, thereby reducing the wettability. Further, when the surface is rough, it becomes easy to entrap impurities. Also, if the oxide layer formed on the solder joint surface of the joint is thick or if there are many impurities adhering to the joint surface, it becomes difficult for the metal constituting the joint and the solder alloy to directly contact each other. , Reducing wettability and bonding strength.

  Therefore, in order to prevent deterioration of the wettability and bondability of the solder, in the electronic component of the present invention, the average roughness of the bonding surface where the solder is bonded and the thickness of the oxide layer formed thereon are below a predetermined value. It is limited to. Thereby, even if it uses the solder which has Bi as a main component which cannot generally be said to be good in wettability, the highly reliable solder joint in which wettability was improved is attained. Further, by reducing the surface roughness, it is possible to make it difficult for impurities to adhere and to easily remove the adhered impurities.

  More specifically, the electronic component according to one specific example of the present invention has a center line average roughness of the solder joint surface of the joint portion where the joint with the Pb-free solder alloy containing Bi as a main component is 5.0 μm. It is as follows. By limiting the surface roughness of the solder joint surface to the above value or less, solder wettability and jointability are improved. As described above, an oxide layer formed on the joint surface is one of the major causes of lowering the wettability and jointability of the solder in the solder joint surface of the joint where the joint is made with the solder. In particular, the amount of oxide present in the vicinity of the solder surface greatly affects wettability and bondability. That is, no matter how thin the oxide layer is, if the surface is rough and there are many irregularities, the amount of oxide present on the solder surface (near) increases and the same phenomenon occurs as when the oxide layer is substantially thick. , The wettability and bondability are greatly reduced.

  To make matters worse, when the surface roughness of the solder joint surface is large, not only the amount of oxide increases, but also the contact area between the solder and the solder joint surface in the electronic component becomes small. For example, when trying to join a semiconductor element and a substrate with solder, the substantial contact area greatly affects wettability and the like. When the surface roughness of the bonding surface is very small, the area spread on the bonding surface is a substantial bonding area. On the other hand, when the surface roughness is large, extremely speaking, the joint surface between the solder and the semiconductor element or the like comes into contact only at a plurality of points, and the substantial joint area becomes extremely small. In such a case, even if the oxide layer is thin, the contact area is small and it is difficult to obtain a desired bonding strength.

  Therefore, in the electronic component of one specific example of the present invention, the center line average roughness of the solder joint surface is 5.0 μm or less, more preferably 3.0 μm or less. This value is an experimental result, and the qualitative reason for reducing the surface roughness is as already described. That is, experimentally, when the center line average roughness exceeds 5.0 μm, the wettability of the solder containing Bi as a main component is remarkably lowered, and it was impossible to join depending on the conditions. More preferably, when the thickness is 3.0 μm or less, excellent reliability having high bonding strength can be obtained.

  Next, an electronic component according to another specific example of the present invention will be described. In the electronic component of another specific example, the thickness of the oxide layer formed on the solder joint surface of the joint with the solder is 30 nm or less. In this case, the center line average roughness of the solder joint surface is preferably 5.0 μm or less. In order to cope with defects related to the wettability and bonding properties of solder used in various applications, it is effective to make the oxide layer on the bonding surface thinner. That is, the main cause of reducing wettability and bondability is an oxide present between the solder joint surface of the joint portion of the semiconductor element or the like and the solder matrix.

  Usually, metals are alloyed if an appropriate material is selected. However, general metal element oxides remain solid at the bonding temperature (for example, 200 ° C. to 450 ° C.), and thus hardly react at the bonding surface. For this reason, the solder metal and the uppermost layer of the substrate cannot be satisfactorily contacted, and as a result, a desired joint strength cannot be obtained. That is, it is one of the important conditions for solder joining using Bi-based solder that the oxide layer is not present as much as possible on the solder joint surface.

  For this reason, the thickness of the oxide layer formed on the solder connection surface of the joint portion of the electronic device such as a semiconductor element or the electronic component such as the substrate is set to 30 nm or less. As described above, the oxide layer greatly reduces wettability and the like, but it is difficult not to exist at all, and if it is a certain thickness, the oxide layer can be appropriately adjusted by appropriately adjusting the soldering conditions and the like. Adverse effects can be suppressed.

  When Bi-based solder is used as a bonding material, although it depends on the contained elements, if the oxide layer is 30 nm or less, the oxide layer may be broken at the time of bonding, and the solder molten metal may be in direct contact with a metal surface such as a substrate. It becomes possible, and good joining is possible. In this way, if the solder and the metal surface can be directly soldered without using an oxide layer, the bonding strength can be increased. Therefore, in an electronic device obtained by soldering an electronic component, it can be used in a harsh environment. In addition, it is possible to obtain excellent bonding reliability that can sufficiently withstand.

<Method for manufacturing electronic parts>
There are no particular limitations on the method of manufacturing the electronic component of the present invention. A substrate will be described as an example of an electronic component. The substrate is generally produced by rolling a Cu plate, and cold rolling, warm rolling, hot rolling or the like can be used for the rolling. When rolling, it may be performed only by cold rolling from the beginning to the final step, but by combining two or more types of rolling, cracks and burrs are difficult to enter during rolling, and quality is improved. Increasing the speed can increase production efficiency.

  However, when warm rolling or hot rolling is performed, an oxide film (oxide layer) is easily formed on the substrate surface, so when combining two or more types of rolling, first perform warm rolling or hot rolling, After removing the oxide layer thus formed as much as possible, it is preferable to perform cold rolling as a finish. Thus, it becomes possible to make an oxide layer thin by making the last process cold. For finishing cold rolling, it is preferable to use a mirror-finished roll having a surface finish, and it is more preferable to use a roll having a center line average roughness of 5.0 μm or less. By using such a roll, a substrate having a small surface roughness can be manufactured.

  Removal of the oxide layer after warm rolling or hot rolling can be performed, for example, by acid cleaning, polishing, grinding, or the like. In addition to reducing the thickness of the oxide layer on the substrate surface by acid cleaning or polishing, the surface roughness can be reduced. Furthermore, an effect of removing foreign matters on the substrate surface can be expected. There is no limitation on the type of acid used in the acid cleaning, but it is preferable to use a solution in which a strong acid is diluted or a solution in a weak acid. If washing is performed using a stock solution of strong acid, the dissolution rate of the substrate in the acid solution becomes too fast, and there is a high possibility that the dissolution proceeds partially or the surface roughness increases. Accordingly, it is preferable to use an aqueous solution containing several percent of a strong acid or an aqueous solution of a weak acid, and adjust the cleaning time to be longer depending on the situation.

  There is no particular limitation on the method for polishing the substrate. For example, buffing may be performed using an automatic polishing apparatus. At this time, the particle size of the ejected particles used is preferably 0.1 μm or less. By using such fine particles, the surface roughness can be kept small. In polishing the substrate, it is preferable to polish the substrate by rotating the polishing means or by reciprocating in the direction perpendicular to the method of moving the substrate, thereby enabling uniform polishing without unevenness.

  As described above, in the production of a substrate as an electronic component, in order to produce a substrate having a thin oxide layer, a substrate having a small surface roughness, or a substrate having a thin oxide layer and a small surface roughness, The surface of the substrate is preferably polished or acid-washed, and then the substrate is roll-rolled, particularly roll-rolled with a roll having a surface roughness of 5.0 μm or less. In particular, it is more preferable to combine the oxide layer removing process by polishing or the like with a roll rolling process.

  Next, the metallized layer formed as the uppermost layer in the solder joint portion of the electronic component will be described. The method for forming the metallized layer is not particularly limited, and may be performed by, for example, a plating method, a vacuum evaporation method, a sputtering method, or the like. Among these, the vacuum deposition method is more preferable because it is relatively inexpensive and the thickness of the metallized layer to be formed can be easily controlled.

  However, sufficient care is required to keep the surface roughness small. For example, if the vapor deposition rate is too slow, it takes time for vapor deposition, and the variation in layer thickness varies depending on the vapor deposition location. On the other hand, if the deposition rate is too high, the layer thickness varies, and the surface roughness increases, which is not preferable. The optimum deposition rate is generally 15 to 50 liters / second, although it is highly device dependent.

  Moreover, there is a degree of vacuum as an important parameter as well as the deposition rate. If the vacuuming is insufficient and the degree of vacuum is low, oxygen or the like exists in the apparatus, so that an oxide film is formed, a uniform film (layer) cannot be formed due to the residual gas, or a porous film is formed. . And as a result of generating them in combination, the thickness and surface roughness of the layer may vary greatly.

A preferable degree of vacuum for avoiding this is approximately 6 × 10 ⁻³ Pa or less. If vapor deposition can be performed at such a degree of vacuum, it is easy to form a uniform layer with a small surface roughness. If a higher degree of vacuum can be achieved, a more preferable layer can be formed, but it is too costly, so the equipment and manufacturing conditions take into account the balance between the required layer quality and cost. Etc. may be appropriately selected. In addition, although conditions, such as an above-described vapor deposition rate and a vacuum degree, are found based on the test result in a small vacuum vapor deposition apparatus, these are conditions which can fully be applied also to mass production equipment.

<Solder composition>
The solder alloy used for the solder joint of the electronic component of the present invention is a Bi-based alloy, and the composition contains Bi of 85% by mass or more. Furthermore, it may contain a second element group, and preferably contains one or more of Zn, Al, Cu, Sn, Sb, and P. However, the content of each element in the second element group is 5.0 mass% or less. This is because if the Bi content is less than 85% by mass or each element of the second element group exceeds 5.0% by mass, the liquidus temperature is out of the range of 250 to 270 ° C. In many cases, the melting point is not suitable as a high-temperature solder.

  Bi, Zn, Al, Cu, Sn, Sb, and P each having a purity of 99.9% by weight or more were prepared as raw materials. Large flakes and bulk-shaped raw materials were reduced to a size of 3 mm or less by cutting and crushing while paying attention to ensure that the alloy after melting did not vary in composition depending on the sampling location. Next, a predetermined amount of these raw materials was weighed and put into a graphite crucible for a high-frequency melting furnace.

  The crucible containing the raw materials was placed in a high-frequency melting furnace, and nitrogen was flowed at a flow rate of 0.7 liter / min or more per kg of the raw materials in order to suppress oxidation. In this state, the melting furnace was turned on to heat and melt the raw material. When the metal began to melt, it was stirred well with a mixing rod and mixed uniformly so as not to cause local compositional variations. After confirming sufficient melting, the high frequency power supply was turned off, the crucible was quickly taken out, and the molten metal in the crucible was poured into the mold of the solder mother alloy. A mold having the same shape as that generally used in the production of a solder mother alloy was used.

  In this way, solder mother alloys of Samples 1A to 23A having various mixing ratios were produced. The compositions of the solder mother alloys of Samples 1A to 23A were analyzed using an ICP emission spectroscopic analyzer (SHIMAZU S-8100). The analysis results are shown in Table 1 below.

<Processing into sheet shape>
The solder mother alloys of Samples 1A to 23A were processed into a sheet using a rolling mill. Specifically, each solder mother alloy (a plate ingot having a thickness of 5 mm) was roughly rolled to a thickness of about 300 μm using a hot rolling mill. At that time, the ingot feed speed was adjusted and rolled while taking care not to cause cracks. The coarsely rolled sample was washed with alcohol and then rolled to a thickness of 0.70 mm using a cold rolling mill. Then, it cut | judged to the width of 25 mm by slitter process, and also wash | cleaned through the automatic washing machine, and dried at room temperature vacuum in the vacuum furnace. In order to perform wettability evaluation and shear strength test on the solder thus obtained, a substrate and a SiC chip were prepared by the following method.

<Production of substrate>
As a substrate material, a plurality of Cu plates having a thickness of 10 mm and a purity of 99.99% by mass were prepared. These Cu plates were warm-rolled at 50 to 90 ° C. to a thickness of 2 mm. Next, it was washed for 1 to 10 minutes using a 5% aqueous acetic acid solution, and further washed with water to sufficiently wash out the acid. And it dried by the normal temperature vacuum drying by a vacuum oven, the drying in normal temperature nitrogen atmosphere, or the heat drying in 150 degreeC air | atmosphere. The obtained plurality of Cu plates were cold-rolled using a roll having a center line average roughness of 0.1 to 3 μm and thinned to a thickness of 0.60 mm.

  Next, the plurality of Cu plates subjected to cold rolling were subjected to metallization under various conditions to form an uppermost layer made of Ni, Ag, Au, or Cu. In this way, the center line average roughness of the uppermost solder joint surface is about 1.0 to 8.0 μm, and the joint surface is covered with an oxide layer having a thickness of about 0.2 to 50 nm. A substrate was prepared. Usually, the substrate which is a component of the electronic component is often rolled at room temperature, and even when performing acid cleaning, a 5% aqueous acetic acid solution is not always used, but in this embodiment, an oxide layer and surface roughness are used. In order to adjust etc., it manufactured on such conditions intentionally.

<Adjustment of surface roughness of SiC chip>
As an electronic device to be soldered to the substrate, a plurality of SiC chips each having a size of 2 × 2 mm and a solder joint portion made of Ni were prepared. These SiC chips are polished with polishing paper (roughness: # 240, # 1000, # 8000), and the surface roughness of the Ni surface is adjusted by buffing (abrasive grain size: 0.1 μm). Ni, Ag, Au, or Cu was deposited to form the uppermost layer. The degree of vacuum was 3 × 10 ^{−4 to} 5 × 10 ⁻² Pa, and the deposition rate was 15 to 100 kg / second. Thus, the center line average roughness of the solder joint surface of the uppermost layer is about 1.0 to 8.0 μm, and the joint surface is covered with the oxide layer having a thickness of about 0.2 to 50 nm. A plurality of SiC chips were prepared.

  The thickness and surface roughness of the oxide layer were measured for each of the plurality of substrates and the plurality of SiC chips produced as described above. The thickness of the oxide layer is measured using a field emission Auger electron spectrometer (manufactured by ULVAC-PHI, model: SAM-4300), and the surface roughness is a surface roughness measuring apparatus (manufactured by Tokyo Seimitsu Co., Ltd., model: Measured using Surfcom 470A). These plural substrates and plural SiC substrates were combined as shown in Table 2 to obtain samples 24B to 59B.

  The thickness of the oxide layer was defined as follows. That is, the oxygen content in the portion 1000 nm in the depth direction (perpendicular to the solder surface) from the solder surface is set to 0%, and the maximum oxygen concentration between the solder surface and the depth of 1000 nm is set to 100%. The penetration depth from the solder surface where the concentration was reduced to 10% was defined as the thickness of the oxide layer (see FIG. 1).

  A solder joint is produced using the solder alloys of Samples 1A to 23A processed as described above, the substrates of Samples 24B to 59B and the SiC chip, and wettability (joinability), shear strength, and heat cycle. Reliability by testing was evaluated. First, as a first evaluation, among the samples shown in Table 2, 23 sets of combinations including the substrate of the sample 28B and the SiC chip were prepared, and each of the solder alloys of Samples 1A to 23A processed into a sheet shape shown in Table 1 Soldered using In this way, 24 solder joint samples were produced. At this time, the solder joined body joined using the solder alloy of sample 1A was designated as sample 1, and the solder joined bodies joined using the solder alloy of samples 2A-23A in the following order were designated as samples 2-23, respectively. And evaluation of the wettability etc. which were shown below was performed with respect to each of these solder joined bodies of samples 1-23.

  Next, as a second evaluation, using the sample 2A shown in Table 1, the substrates of Samples 24B to 59B shown in Table 2 and the SiC chip were joined to prepare 36 solder joined samples. At this time, the sample 24B was made of a solder joint made of a substrate and a SiC chip as a sample 24, and the samples 25B to 59B were made of a solder joint made of a SiC chip and samples 25 to 59, respectively. Then, the following evaluations of wettability and the like were performed on each of the solder joints of Samples 24 to 59 in the same manner as the first evaluation.

<Evaluation of wettability (bondability)>
First, the heater part of the wettability tester was covered with a double cover, and heated at a heater set temperature of 410 ° C. while flowing nitrogen at a flow rate of 12 liters / minute from four locations around the heater part. After the set heater temperature was stabilized, the substrate of each sample was set in the heater section and heated for 25 seconds. Next, the solder alloy of each sample was placed on the substrate and heated for 25 seconds, and then the SiC chip of each sample was placed on the solder and heated for 10 seconds.

  After the heating was completed, the joined body composed of the solder-bonded substrate and the SiC chip was taken up from the heater portion, and once installed in a place where the nitrogen atmosphere was maintained, it was cooled. After sufficiently cooling, it was taken out into the atmosphere. The solder alloy, the substrate and the SiC chip of each joined body obtained in this way were visually inspected, and “x” indicates that the joint could not be joined. The case where the chip was not protruded from the four sides of the chip was evaluated as “Δ”, and the case where the bonding was possible and the wet spread was good (the solder was thinly wet and spread out from the four ends of the SiC chip) was evaluated as “◯”.

<Share strength evaluation>
In order to evaluate the joint strength of the solder joint, the shear strength was measured using a shear strength measuring device (Xyztec, Condor EZ bond tester). In addition, this test was performed using three samples each of which the substrate and the SiC chip could be joined with a solder alloy (samples with a wettability evaluation of ◯ and samples with a Δ) in the above-described evaluation of wettability. The value was defined as the shear strength of the sample.

  The specific method for measuring the share strength is as follows. That is, the bonded body of each sample was fixed to the work holder (part for fixing the sample) of the shear strength measuring device with the SiC chip surface facing upward, and the shear tool was applied to the side surface of the SiC chip to apply a shear stress to the solder. . Then, a load was applied to the shear tool from the side surface of the bonded SiC chip by automatic measurement, and the shear strength was measured by applying a load until the solder or the SiC chip was broken.

<Heat cycle test>
A heat cycle test was conducted to evaluate the reliability of solder joints. In addition, this test was performed using two samples each of which the Cu substrate and the SiC chip could be joined with the solder alloy (samples with a wettability evaluation of ◯ and samples with a Δ) in the above-described evaluation of wettability. . That is, a heat cycle test in which a cycle of cooling at −40 ° C. and heating at + 150 ° C. was performed on two bonded bodies of each sample composed of a substrate bonded with a solder alloy and a SiC chip. In the heat cycle test of each sample, one of the two joined bodies was repeated up to 300 cycles for confirmation on the way, and the remaining one was repeated up to 500 cycles.

  In this way, after each bonded body subjected to the heat cycle test was embedded in the resin, cross-section polishing was performed, and the bonded surface was observed by SEM (device name: HITACHI S-4800). When the solder / substrate / SiC chip joint surface was peeled off or the solder mother phase joint surface was cracked, “x”, there was no such defect, and the same joint surface as in the initial state was maintained. The case was evaluated as “◯”. These evaluation results are shown in the following Table 3-1 (first evaluation) and Table 3-2 (second evaluation).

  As can be seen from the results in Tables 3-1 and 3-2 above, the joined bodies of Samples 1 to 17 and Samples 24 to 43 that satisfy the requirements of the present invention exhibit good characteristics in all the evaluation items. That is, good evaluation results were obtained in any of wettability, shear strength, and reliability. The reason why the wettability was good is thought to be that not only the oxide film layer and surface roughness of the substrate and SiC chip, but also the solder composition satisfied the requirements of the present invention. Thus, since it exhibits good wettability without being obstructed by the oxide, the bonding strength, that is, the shear strength is also high. As a result, it is considered that high reliability was obtained.

  On the other hand, in the joined bodies of Samples 18 to 23 and Samples 44 to 59 that do not satisfy the requirements of the present invention, the solder composition is not preferable, and the thickness and surface roughness of the oxide layer of the substrate and the SiC chip are not appropriate. This resulted in an unfavorable result. Specifically, in these samples, good wettability is not obtained in all samples in the wettability evaluation. Even in the samples that have reached the shear strength test, the shear strength is lower than the bonded bodies of Samples 1 to 17 and Samples 24 to 43, and in the heat cycle test, all samples (samples 18, 20 to 22 that could not be bonded) , 48-51, and 56-59).

Claims (4)

One or more of Zn, Al, Sn, Sb, and P are each contained by 5.0% by mass or less, the remainder is Bi, and the entire solder alloy is joined by a solder alloy containing Bi by 85% by mass or more. The uppermost layer of the joint is mainly composed of any one of Au, Ag, Ni and Cu, and the center line average roughness of the solder joint surface of the uppermost layer is 1.0 μm. An electronic component having a thickness of 5.0 μm or less. One or more of Zn, Al, Sn, Sb, and P are each contained by 5.0% by mass or less, the remainder is Bi, and the entire solder alloy is joined by a solder alloy containing Bi by 85% by mass or more. The uppermost layer of the joint is composed mainly of any one of Au, Ag, Ni and Cu, and the oxygen content in the part 1000 nm deep from the surface is reduced to 0% When the maximum oxygen concentration between the surface and the depth of 1000 nm is 100% and the penetration depth from the surface where the oxygen concentration is reduced to 10% is defined as the thickness of the oxide layer, the solder joint of the uppermost layer An electronic component, wherein the surface is covered with an oxide layer having a thickness of 0.2 nm to 30 nm. One or more of Zn, Al, Sn, Sb, and P are each contained by 5.0% by mass or less, the remainder is Bi, and the entire solder alloy is joined by a solder alloy containing Bi by 85% by mass or more. The uppermost layer of the joint is mainly composed of any one of Au, Ag, Ni and Cu, and the center line average roughness of the solder joint surface of the uppermost layer is 1.0 μm. More than 5.0 μm and the oxygen content of the portion 1000 nm deep from the surface is reduced to 0%, the maximum oxygen concentration between the surface and the depth of 1000 nm is set to 100%, and the oxygen concentration is 10%. When the depth of penetration from the surface reduced to the thickness is defined as the thickness of the oxide layer, the solder joint surface of the uppermost layer is covered with an oxide layer having a thickness of 0.2 nm to 30 nm. Electronic components. For an electronic component having a solder joint whose uppermost layer is mainly composed of any one of Au, Ag, Ni and Cu, one or more of Zn, Al, Sn, Sb and P A method of manufacturing an electronic device by soldering using a solder alloy containing 5.0% by mass or less, the balance being Bi, and containing 85% by mass or more of Bi in the entire solder alloy, The center line average roughness of the solder joint surface is 1.0 μm or more and 5.0 μm or less, or the oxygen content of the portion entering 1000 nm in the depth direction from the surface is reduced to 0% and the depth from the surface is 1000 nm. When the depth of penetration from the surface where the maximum oxygen concentration is 100% and the oxygen concentration is reduced to 10% is defined as the thickness of the oxide layer, the solder joint surface of the uppermost layer has a thickness of 0.2 nm to 30 nm. In the oxide layer Or the center line average roughness of the solder joint surface is 1.0 μm or more and 5.0 μm or less, and the solder joint surface is covered with an oxide layer having a thickness of 0.2 nm or more and 30 nm or less as defined above. A method of manufacturing an electronic device.

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