JP5994661B2 - 検証プログラム、検証方法及び検証装置 - Google Patents

検証プログラム、検証方法及び検証装置 Download PDF

Info

Publication number
JP5994661B2
JP5994661B2 JP2013016352A JP2013016352A JP5994661B2 JP 5994661 B2 JP5994661 B2 JP 5994661B2 JP 2013016352 A JP2013016352 A JP 2013016352A JP 2013016352 A JP2013016352 A JP 2013016352A JP 5994661 B2 JP5994661 B2 JP 5994661B2
Authority
JP
Japan
Prior art keywords
transfer period
unit
verification
channel
combination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013016352A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014149565A5 (enExample
JP2014149565A (ja
Inventor
拓 河村
拓 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2013016352A priority Critical patent/JP5994661B2/ja
Priority to US14/134,435 priority patent/US9547568B2/en
Publication of JP2014149565A publication Critical patent/JP2014149565A/ja
Publication of JP2014149565A5 publication Critical patent/JP2014149565A5/ja
Application granted granted Critical
Publication of JP5994661B2 publication Critical patent/JP5994661B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microelectronics & Electronic Packaging (AREA)
JP2013016352A 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置 Expired - Fee Related JP5994661B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013016352A JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置
US14/134,435 US9547568B2 (en) 2013-01-31 2013-12-19 Method and apparatus for verifying circuit design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013016352A JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置

Publications (3)

Publication Number Publication Date
JP2014149565A JP2014149565A (ja) 2014-08-21
JP2014149565A5 JP2014149565A5 (enExample) 2015-11-19
JP5994661B2 true JP5994661B2 (ja) 2016-09-21

Family

ID=51223847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013016352A Expired - Fee Related JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置

Country Status (2)

Country Link
US (1) US9547568B2 (enExample)
JP (1) JP5994661B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160173398A1 (en) * 2014-12-12 2016-06-16 Intel Corporation Method, Apparatus And System For Encoding Command Information In a Packet-Based Network
US9891986B2 (en) * 2016-01-26 2018-02-13 Nxp Usa, Inc. System and method for performing bus transactions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063642A (ja) 1983-09-16 1985-04-12 Fujitsu Ltd 競合動作試験方式
JPS63276660A (ja) 1987-04-14 1988-11-14 Fujitsu Ltd バスモニタ方式
JPH04148461A (ja) 1990-10-12 1992-05-21 Hitachi Ltd マルチプロセッサシステムテスト方式
JP2721430B2 (ja) 1990-11-20 1998-03-04 株式会社日立製作所 リクエスト競合生成方式
JPH05108401A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd テストパターン生成方法
JPH06149762A (ja) 1992-11-10 1994-05-31 Hitachi Ltd 計算機システムの競合動作試験方式
JP2008262457A (ja) * 2007-04-13 2008-10-30 Hitachi Kokusai Electric Inc マルチコアプロセッサのバス監視方法
JP5347482B2 (ja) * 2008-12-18 2013-11-20 富士通セミコンダクター株式会社 性能評価装置、性能評価方法及びシミュレーションプログラム
JP2010244300A (ja) 2009-04-06 2010-10-28 Mitsubishi Electric Corp テストパターン作成手法、シミュレーション方法、情報処理装置およびシミュレーション装置
US8255345B2 (en) * 2009-05-15 2012-08-28 The Aerospace Corporation Systems and methods for parallel processing with infeasibility checking mechanism
JP5153904B2 (ja) * 2010-09-22 2013-02-27 インターナショナル・ビジネス・マシーンズ・コーポレーション プログラムの動作推測方法及びプログラム

Also Published As

Publication number Publication date
JP2014149565A (ja) 2014-08-21
US20140214355A1 (en) 2014-07-31
US9547568B2 (en) 2017-01-17

Similar Documents

Publication Publication Date Title
CN113868987B (zh) 一种系统级芯片的验证平台及其验证方法
CN113076227A (zh) Mcu验证方法、系统和终端设备
CN118036525B (zh) 基于uvm和c模型的验证系统与方法、存储介质、验证平台
US8036874B2 (en) Software executing device and co-operation method
CN100476837C (zh) 一种支持随机指令测试的微处理器fpga验证装置
JP5994661B2 (ja) 検証プログラム、検証方法及び検証装置
US8250545B2 (en) Associated apparatus and method for supporting development of semiconductor device
US20080288902A1 (en) Circuit design verification method and apparatus and computer readable medium
US11295052B1 (en) Time correlation in hybrid emulation system
US7228513B2 (en) Circuit operation verification device and method
CN115732025A (zh) Ram访问冲突的验证方法及验证装置
US7231568B2 (en) System debugging device and system debugging method
US20080281576A1 (en) Interface board, simulator, synchronization method, and synchronization program
US20100161305A1 (en) Performance evaluation device, performance evaluation method and simulation program
US20060212768A1 (en) Verification circuitry for master-slave system
JP5664430B2 (ja) 試験装置、検証モデル開発方法及びプログラム
CN115292760A (zh) 芯片验证系统、方法及计算机可读存储介质
JP2004021907A (ja) 性能評価用シミュレーションシステム
JP5673197B2 (ja) 試験プログラムおよび試験方法
JPH10221410A (ja) Lsiの自動論理検証方式
KR20140113175A (ko) 버스 프로토콜 검사기, 이를 포함하는 시스템 온 칩 및 버스 프로토콜 검사 방법
US20190012418A1 (en) Simulation program, method, and device
JP2012238089A (ja) 集積回路装置、検証装置及び検証方法
CN119885991A (zh) 调试方法、设备及存储介质
Viktorin et al. Framework for fast prototyping of applications running on reconfigurable system on chip

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20150611

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151001

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151001

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160627

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160726

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160808

R150 Certificate of patent or registration of utility model

Ref document number: 5994661

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees