JP2014149565A5 - - Google Patents

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Publication number
JP2014149565A5
JP2014149565A5 JP2013016352A JP2013016352A JP2014149565A5 JP 2014149565 A5 JP2014149565 A5 JP 2014149565A5 JP 2013016352 A JP2013016352 A JP 2013016352A JP 2013016352 A JP2013016352 A JP 2013016352A JP 2014149565 A5 JP2014149565 A5 JP 2014149565A5
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JP
Japan
Prior art keywords
competition
explanatory drawing
shows
monitor
verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2013016352A
Other languages
English (en)
Japanese (ja)
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JP5994661B2 (ja
JP2014149565A (ja
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Priority to JP2013016352A priority Critical patent/JP5994661B2/ja
Priority claimed from JP2013016352A external-priority patent/JP5994661B2/ja
Priority to US14/134,435 priority patent/US9547568B2/en
Publication of JP2014149565A publication Critical patent/JP2014149565A/ja
Publication of JP2014149565A5 publication Critical patent/JP2014149565A5/ja
Application granted granted Critical
Publication of JP5994661B2 publication Critical patent/JP5994661B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2013016352A 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置 Expired - Fee Related JP5994661B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013016352A JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置
US14/134,435 US9547568B2 (en) 2013-01-31 2013-12-19 Method and apparatus for verifying circuit design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013016352A JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置

Publications (3)

Publication Number Publication Date
JP2014149565A JP2014149565A (ja) 2014-08-21
JP2014149565A5 true JP2014149565A5 (enExample) 2015-11-19
JP5994661B2 JP5994661B2 (ja) 2016-09-21

Family

ID=51223847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013016352A Expired - Fee Related JP5994661B2 (ja) 2013-01-31 2013-01-31 検証プログラム、検証方法及び検証装置

Country Status (2)

Country Link
US (1) US9547568B2 (enExample)
JP (1) JP5994661B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160173398A1 (en) * 2014-12-12 2016-06-16 Intel Corporation Method, Apparatus And System For Encoding Command Information In a Packet-Based Network
US9891986B2 (en) * 2016-01-26 2018-02-13 Nxp Usa, Inc. System and method for performing bus transactions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063642A (ja) 1983-09-16 1985-04-12 Fujitsu Ltd 競合動作試験方式
JPS63276660A (ja) 1987-04-14 1988-11-14 Fujitsu Ltd バスモニタ方式
JPH04148461A (ja) 1990-10-12 1992-05-21 Hitachi Ltd マルチプロセッサシステムテスト方式
JP2721430B2 (ja) 1990-11-20 1998-03-04 株式会社日立製作所 リクエスト競合生成方式
JPH05108401A (ja) * 1991-10-17 1993-04-30 Hitachi Ltd テストパターン生成方法
JPH06149762A (ja) 1992-11-10 1994-05-31 Hitachi Ltd 計算機システムの競合動作試験方式
JP2008262457A (ja) * 2007-04-13 2008-10-30 Hitachi Kokusai Electric Inc マルチコアプロセッサのバス監視方法
JP5347482B2 (ja) * 2008-12-18 2013-11-20 富士通セミコンダクター株式会社 性能評価装置、性能評価方法及びシミュレーションプログラム
JP2010244300A (ja) 2009-04-06 2010-10-28 Mitsubishi Electric Corp テストパターン作成手法、シミュレーション方法、情報処理装置およびシミュレーション装置
US8255345B2 (en) * 2009-05-15 2012-08-28 The Aerospace Corporation Systems and methods for parallel processing with infeasibility checking mechanism
JP5153904B2 (ja) * 2010-09-22 2013-02-27 インターナショナル・ビジネス・マシーンズ・コーポレーション プログラムの動作推測方法及びプログラム

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