JP5979086B2 - Supervisory circuit - Google Patents

Description

  The present invention relates to a monitoring circuit that monitors the operation of a half-bridge circuit including two switching elements that are complementarily driven with a dead time in which both are turned off.

  For example, a half bridge circuit composed of two switching elements connected in series is used for an inverter, a synchronous rectification type DC / DC converter, and the like. In this case, the two switching elements are complementarily driven after a period during which both are turned off (referred to as dead time) is provided. Conventionally, various techniques for monitoring the operation of such a half-bridge circuit have been devised.

  For example, among the PWM signals for driving two switching elements, a logical sum of one PWM signal and a signal obtained by delaying the other PWM signal by an integration circuit is obtained, and based on a signal representing the logical sum. There is a technique of detecting an abnormality in which dead time cannot be secured (upper and lower arm short circuit abnormality) (see, for example, Patent Document 1). In addition, whether or not the switching state of all the switching elements is normal can be monitored by inputting a PWM signal for driving all the switching elements to a microcomputer (hereinafter abbreviated as “microcomputer”). There are also techniques for monitoring.

Japanese Patent No. 3596301

  Among the above-described conventional techniques, the former technique cannot monitor whether the PWM signal is normal, that is, whether the switching operation by the switching element is normally performed. On the other hand, in the latter technique, it is necessary to monitor twice as many signals as the number of half-bridge circuits to be monitored. Therefore, as the number of monitoring targets increases, signal wiring becomes very complicated. . Furthermore, for example, when the signal to be monitored is a high-voltage signal that operates at a relatively high voltage, an insulating element corresponding to the number of the signals is required, which causes a problem of high cost.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a monitoring circuit capable of detecting an abnormality relating to a half-bridge circuit without increasing the number of signals to be monitored unnecessarily. is there.

  The monitoring circuit according to claim 1 monitors the operation of the half bridge circuit including two switching elements that are complementarily driven with a dead time in which both are turned off. The monitoring circuit includes a signal synthesis circuit and an abnormality detection circuit. The signal synthesis circuit generates a monitoring signal based on two driving state signals representing driving states of the two switching elements. The monitoring signal is at the first level during a period in which both of the two driving state signals represent the off driving state. Further, the monitoring signal becomes a second level different from the first level during a period in which at least one of the two driving state signals represents the on-driving state.

  The monitoring signal generated in this way changes as follows according to the presence / absence and type of abnormality related to the half-bridge circuit. That is, when there is no abnormality related to the half bridge circuit, the period during which the monitoring signal is at the first level is equivalent to the desired dead time. On the other hand, when an abnormality relating to the dead time occurs, the period during which the monitoring signal is at the first level is a period different from the desired dead time.

  When an abnormality relating to the switching operation has occurred, the monitoring signal is as follows. Examples of the abnormality related to the switching operation include a short-circuit fault in which one or both switching elements are fixed in an on state, and an open fault in which one or both switching elements are fixed in an off state. When such an abnormality occurs, the period during which the monitoring signal is at the first level is not equal to the desired dead time. In addition, when such an abnormality occurs, the number of times the monitoring signal changes within a predetermined period is smaller than when no abnormality occurs.

  Focusing on this point, the abnormality detection circuit detects an abnormality related to the half-bridge circuit as follows based on the monitoring signal. That is, the abnormality detection circuit detects an abnormality related to the switching operation of the two switching elements based on the number of edges within the predetermined period of the monitoring signal. As described above, when an abnormality relating to switching occurs, the number of times the monitoring signal changes within a predetermined period tends to decrease. Therefore, the abnormality detection circuit can reliably detect an abnormality related to the switching operation by the above method.

  The abnormality detection circuit detects an abnormality related to dead time based on the pulse width of the monitoring signal. As described above, when an abnormality relating to the dead time occurs, the period during which the monitoring signal is at the first level is not equal to the desired dead time. Therefore, the abnormality detection circuit can reliably detect an abnormality related to the dead time by the above method. Thus, according to this means, it is possible to accurately detect both the abnormality relating to the dead time and the abnormality relating to the switching operation in the half bridge circuit without increasing the signals to be monitored unnecessarily.

The 1st Embodiment is a figure showing roughly the composition of a monitoring circuit. The figure which shows the PWM signal and the monitoring signal at the time of normal FIG. 2 equivalent diagram when an abnormality relating to the switching operation occurs Figure equivalent to Fig. 2 when an abnormality relating to dead time occurs Flowchart showing contents of switching abnormality determination processing Flow chart showing contents of dead time abnormality determination processing The figure which shows the 1st structural example which applied the monitoring circuit to the motor drive system. The figure which shows the 2nd structural example which applied the monitoring circuit to the motor drive system. The figure which shows the 3rd structural example which applied the monitoring circuit to the motor drive system. The figure which shows the 1st structural example which applied the monitoring circuit to the DC / DC converter system. The figure which shows the 2nd structural example which applied the monitoring circuit to the DC / DC converter system. The figure which shows the 3rd structural example which applied the monitoring circuit to the DC / DC converter system. The figure which shows the aspect by which a control system and a drive system are mounted in a mutually different printed wiring board FIG. 13 equivalent diagram showing the prior art FIG. 1 equivalent diagram showing the second embodiment 2 equivalent diagram 3 equivalent diagram 4 equivalent diagram 1 equivalent diagram 1 equivalent diagram The flowchart which shows 3rd Embodiment and shows the content of edge processing The flowchart which shows 4th Embodiment and shows the content of the dead time acquisition process Flow chart showing contents of dead time determination processing

Hereinafter, a plurality of embodiments of the monitoring circuit will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
The monitoring circuit 1 shown in FIG. 1 monitors the operation of the half bridge circuit 2. The half bridge circuit 2 has a well-known configuration including two switching elements that constitute upper and lower arms. The half bridge circuit 2 is used, for example, for an inverter that drives a motor, a synchronous rectification type DC / DC converter, or the like.

  The two switching elements are complementarily driven after a period (dead time) in which both are turned off is provided. The control circuit 3 outputs two PWM signals (corresponding to drive signals) that change complementarily to the half-bridge circuit 2, and controls the drive of the half-bridge circuit 2 by PWM (Pulse Width Modulation). The switching element is turned on when a high level PWM signal is applied, and is turned off when a low level PWM signal is applied (High-Active). The control circuit 3 is configured mainly with a microcomputer, for example.

  The monitoring circuit 1 includes a signal generation circuit 4 and an abnormality detection circuit 5. The signal generation circuit 4 is configured by a NOR circuit. The signal generation circuit 4 is input with two high-active PWM signals or a signal (corresponding to a drive state signal) that changes in accordance with them. The signal generation circuit 4 generates a monitor signal that is a logical sum of two input signals and is inverted. The monitoring signal is given to the abnormality detection circuit 5. The abnormality detection circuit 5 is composed mainly of a microcomputer, for example. Although described in detail later, the abnormality detection circuit 5 detects an abnormality related to the half bridge circuit 2 based on the monitoring signal. The control circuit 3 and the abnormality detection circuit 5 may be configured by the same microcomputer or may be configured by separate microcomputers.

Next, the waveform of the monitoring signal at normal time and abnormal time will be described.
(1) Normal time The PWM signal at the normal time has a waveform as shown in FIGS. That is, when one of the two PWM signals is at a high level, the other is at a low level. Further, there is a period (dead time) in which both of the PWM signals are at the low level from the time when the one of the PWM signals is switched to the low level until the time when the other PWM signal is switched to the high level.

  Therefore, the normal monitoring signal has a waveform as shown in FIG. That is, the monitoring signal is at a high level (corresponding to the first level) during a period in which both of the two PWM signals are at a low level. In addition, the monitoring signal is at a low level (corresponding to the second level) during a period in which at least one of the two PWM signals is at a high level. In this case, the period during which the monitoring signal is at a high level is as long as the desired dead time. In the following description, a period in which the monitoring signal is at a high level (first level) is also referred to as a both signal inactive period. In addition, the length of both signal inactive sections corresponds to the pulse width of the monitoring signal.

  In addition, the monitoring signal has four edges in one period Tb of the PWM carrier wave (which is a carrier period, which is also a switching period in this case). That is, in one cycle Tb, there are two timings (rising edge) when the monitoring signal changes from the low level to the high level, and there are two timings (falling edge) when the monitoring signal changes from the high level to the low level. Exists.

(2) When an abnormality relating to the switching operation occurs As an abnormality relating to the switching operation of the switching element, one or both of the switching elements are fixed to the ON state, and one or both of the switching elements are fixed to the OFF state. For example, open failure. Here, a case where the switching element on the lower arm side has an open failure will be described as an example. When such a failure occurs, the PWM signal has a waveform as shown in FIGS. That is, the PWM signal on the upper arm side has the same waveform as that in the normal state, but the PWM signal on the lower arm side is fixed at the low level.

  Therefore, the monitoring signal in the case where the failure has occurred has a waveform as shown in FIG. That is, after the failure occurs, both signal inactive sections of the monitoring signal have a length different from the desired dead time. Further, the monitoring signal has three edges in the period in which the failure occurs. Further, the monitoring signal has two edges in the period after the occurrence of the failure. That is, when the failure occurs, the number of times that the monitoring signal changes in a predetermined period is smaller than that in the normal state. Note that when another abnormality related to the switching operation occurs, the number of times the monitoring signal changes is smaller than that in the normal state as in the case where the open failure on the lower arm side occurs.

(3) When an abnormality relating to the dead time occurs For example, when an abnormality occurs in which the dead time is shorter than a desired length, the PWM signal has a waveform as shown in FIGS. In other words, the period from the fall of one PWM signal to the rise of the other PWM signal is shorter than in the normal state. Therefore, the monitoring signal when the abnormality occurs has a waveform as shown in FIG. That is, when the abnormality occurs, both signal inactive sections of the monitoring signal are short periods different from the desired dead time.

Subsequently, the control contents of the abnormality detection circuit 5 having the above-described configuration will be described with reference to the flowcharts of FIGS.
(1) Switching abnormality determination process The switching abnormality determination process is a process for determining the presence or absence of an abnormality related to the switching operation. In this case, the abnormality detection circuit 5 controls the contents as shown in FIG. First, in step S1, the number of edges in a predetermined measurement period of the monitoring signal is acquired. Measurement of the number of edges in the measurement period can be realized by a timer function of a general microcomputer. When the number of edges is acquired, the number of edges in the timer register is cleared. The measurement period may be an arbitrary period (predetermined period), and for example, a period such as a carrier cycle, a carrier half cycle, or every constant rotation of the motor can be employed.

  In step S2, it is determined whether or not an edge is not generated in the monitoring signal. The state where no edge occurs in the monitoring signal is, for example, the following state. That is, when the half bridge circuit 2 is used for an inverter, when the rotational speed of the motor driven by the inverter is extremely low (when almost stopped), switching is not performed due to a motor lock state or the like. For example, when the period lasts long. Further, when the half bridge circuit 2 is used for a boost converter, the input voltage is equal to or higher than a target value (command value) of the output voltage. Further, when the half-bridge circuit 2 is used in a step-down converter, the input voltage is equal to or lower than the target value of the output voltage.

  In such a state, it is difficult to determine whether there is an abnormality related to the switching operation based on the number of edges. For this reason, in this embodiment, when it is determined in step S2 that no edge occurs in the monitoring signal (YES), the abnormality determination regarding the switching operation is not performed. Specifically, if “YES” in the step S2, the process proceeds to a step S3. In step S <b> 3, the abnormality detection circuit 5 instructs the control circuit 3 to perform a normal switching operation. In response to this, the control circuit 3 controls the driving of the two switching elements as usual. After execution of step S3, the process ends.

On the other hand, if it is determined in step S2 that the edge is generated in the monitoring signal (NO), the process proceeds to step S4. In step S4, it is determined whether or not the number of edges acquired in step S1 matches the specified number. As in this embodiment, when the drive of the switching element is PWM controlled (in the PWM control mode), the specified number of times can be determined based on the following equation (1). However, the specified number of times is N, the measurement period is Ta, and the carrier period is Tb.
N = 4 × (Ta / Tb) (1)

When the switching element is driven by rectangular wave control (in the rectangular wave control mode), the specified number of times can be determined based on the following equation (2). However, M is the number of times of switching within the measurement period.
N = 2 × M (2)

  If the edge count matches the specified count, “YES” is determined in the step S4, and the process proceeds to the step S3. That is, it is determined that no abnormality relating to the switching operation has occurred, and the normal switching operation is executed. On the other hand, if the number of edges does not match the specified number, “NO” is determined in the step S4, and the process proceeds to the step S5. In step S5, the abnormality detection circuit 5 instructs the control circuit 3 to execute a predetermined fail-safe process. In response to this, the control circuit 3 executes fail-safe processing.

  Examples of the fail-safe process when an abnormality relating to the switching operation occurs include the following process. That is, when the half-bridge circuit 2 is used for an inverter, the driving of each switching element is controlled to apply a short-circuit brake. When the half bridge circuit 2 is used in a DC / DC converter, the upper arm side switching element is turned on and the lower arm side switching element is turned off. After step S5 is executed, the process ends.

(2) Dead time abnormality determination process The dead time abnormality determination process is a process for determining the presence or absence of an abnormality relating to dead time. In this case, the abnormality detection circuit 5 controls the contents as shown in FIG. First, in step T1, both signal inactive sections of the monitoring signal are acquired. Measurement of both signal inactive sections can be realized by a timer function of a general microcomputer. In step T2, it is determined whether or not both signal inactive sections acquired in step T1 are within a specified range. In this case, the lower limit of the specified range is defined as the first time, and the upper limit is defined as the second time.

  The second time may be an infinite time. That is, in step T2, it may be changed so as to determine whether or not both signal inactive sections are equal to or longer than the first time. The reason for this is as follows. That is, the dead time abnormality can be considered when the dead time is shorter or longer than a desired value. However, when the dead time is long, a serious problem such as a short circuit between the upper and lower arms (a problem that requires circuit and element protection) does not occur. Therefore, it is only necessary to detect the dead time abnormality only when the dead time is shorter than a desired value. Therefore, the second time may be set to an infinite time.

  When both signal inactive sections are within the specified range, “YES” is determined in the step T2, and the process proceeds to the step T3. Step T3 is the same process as step S3. Therefore, when both signal inactive sections are within the specified range, it is determined that an abnormality relating to the dead time has not occurred, and a normal switching operation is performed. After execution of step T3, the process ends.

  On the other hand, when both signal inactive sections are outside the specified range, “NO” is determined in the step T2, and the process proceeds to the step T4. In step T4, the abnormality detection circuit 5 instructs the control circuit 3 to execute a predetermined fail-safe process. In response to this, the control circuit 3 executes fail-safe processing. The fail-safe process when an abnormality relating to dead time occurs includes, for example, a process of stopping (all turning off) the switching operation of an arm in which an abnormality relating to dead time is detected. After execution of step T4, the process ends.

  The switching abnormality determination process and the dead time determination process are executed every switching half cycle. Therefore, it is possible to reliably and quickly detect an abnormality related to the switching operation and the dead time. It should be noted that one or both of the switching abnormality determination process and the dead time determination process may be thinned out. In this case, compared with the case where the abnormality determination process is performed every switching half cycle, the speed of abnormality detection is slightly reduced, but the processing load of the microcomputer constituting the abnormality detection circuit 5 is reduced. .

  Next, a specific application example of the monitoring circuit having the above configuration will be described with reference to FIGS. 7 to 12, a portion surrounded by a dotted line is a high voltage portion that operates at a relatively high voltage, and the other portion is a low voltage portion that operates at a relatively low voltage. The high voltage part and the low voltage part are electrically insulated.

(1) First Configuration Example When Applying Monitoring Circuit to Motor Drive System A motor drive system 11 shown in FIG. 7 includes a three-phase inverter 12, a DC power supply 13 that is a battery, a control circuit 14, and a three-phase AC motor. 15 (hereinafter simply referred to as a motor 15), a monitoring circuit 16 and the like. In this case, signal input / output is performed between the high-voltage part and the low-pressure part via insulating elements 17 to 25 made of, for example, photocouplers.

  The inverter 12 is supplied with the DC voltage Vdc from the DC power supply 13 via the power supply lines 26 and 27, and receives PWM signals DUU, DVU, DWU, DUL, DVL, which are supplied from the control circuit 14 via the insulating elements 17-22. A three-phase AC voltage is output to the motor 15 according to DWL. The capacitor 28 is for smoothing and is connected between the power supply lines 26 and 27.

  Between the power supply lines 26 and 27, the upper arm IGBTs 29UU, 29VU, and 29WU and the lower arm IGBTs 29UL, 29VL, and 29WN (all corresponding to switching elements) are connected in a three-phase bridge. That is, the IGBTs 29UU and 29UL constitute a U-phase half-bridge circuit 30U, the IGBTs 29VU and 29VL constitute a V-phase half-bridge circuit 30V, and the IGBTs 29WU and 29WL constitute a W-phase half-bridge circuit 30W.

  A reflux diode is connected in parallel to the IGBTs 29UU to 29WL. Each of the IGBTs 29UU to 29WL is configured as an individual module including a current sensing IGBT. In the IGBTs 29UU to 29WL, the emitter of the current sensing IGBT (hereinafter referred to as the sensing emitter) is connected to the emitters of the IGBTs 29UU to 29WL via the shunt resistor Rs.

  The monitoring circuit 16 monitors the operation of the half bridge circuits 30U, 30V, and 30W, and includes signal generation circuits 31U, 31V, and 31W, an abnormality detection circuit 32, and the like. The signal generation circuit 31U receives the signals of the sensing emitters of the IGBTs 29UU and 29UL, and outputs a monitor signal SU that is a logical sum and an inverted signal of these input signals. The signal generation circuit 31V inputs the signals of the sense emitters of the IGBTs 29VU and 29VL, and outputs a monitoring signal SV which is a logical sum and an inverted signal of these input signals. The signal generation circuit 31W inputs the sense emitter signals of the IGBTs 29WU and 29WL, and outputs a monitor signal SW that is a logical sum and an inverted signal of the input signals. The monitoring signals SU, SV, and SW are given to the abnormality detection circuit 32 via the insulating elements 23 to 24, respectively.

  In the above configuration, the sense emitter signals of the IGBTs 29UU to 29WL change according to the PWM signals DUU to DWL, and represent the drive states of the IGBTs 29UU to 29WL. For this reason, the monitoring signals SU to SW output from the signal generation circuits 31U to 31W are equivalent to signals obtained by inverting the logical sum of two complementary PWM signals that are respectively applied to the upper and lower arms of the corresponding phase. . Therefore, the abnormality detection circuit 32 can detect an abnormality in the half bridge circuits 30U to 30W by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signals SU to SW.

(2) Second configuration example when the monitoring circuit is applied to a motor drive system A motor drive system 41 shown in FIG. 8 has insulating elements 23 to 25 compared to the motor drive system 11 of the first configuration example shown in FIG. Is different from the point that the input signals to the signal generation circuits 31U to 31W are changed. In FIG. 8, illustration of the sensing emitters and shunt resistors Rs of the IGBTs 29UU to 29WL is omitted.

  In this case, the signal generation circuit 31U receives the PWM signals DUU and DUL on the control circuit 14 side from the insulating elements 17 and 18, and outputs a monitoring signal SU that is a logical sum and an inverted signal of these input signals. The signal generation circuit 31V receives the PWM signals DVU and DVL on the control circuit 14 side from the insulating elements 19 and 20, and outputs a monitor signal SV that is a logical sum and an inverted signal of these input signals. The signal generating circuit 31W receives the PWM signals DWU and DWL on the control circuit 14 side from the insulating elements 21 and 22, and outputs a monitoring signal SW that is a logical sum and inverted signal of these input signals. The monitoring signals SU to SW are given to the abnormality detection circuit 32.

  In the above configuration, the monitoring signals SU to SW output from the signal generation circuits 31U to 31W are signals obtained by inverting the logical sum of two complementary PWM signals respectively applied to the upper and lower arms of the corresponding phase. Therefore, the abnormality detection circuit 32 can detect an abnormality in the half bridge circuits 30U to 30W by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signals SU to SW.

(3) Third configuration example when the monitoring circuit is applied to a motor drive system A motor drive system 51 shown in FIG. 9 has signal generation circuits 31U to 31U to the motor drive system 11 of the first configuration example shown in FIG. The difference is that the input signal to 31W is changed. Also in FIG. 9, illustration of the sensing emitters and shunt resistors Rs of the IGBTs 29UU to 29WL is omitted.

  In this case, the signal generation circuit 31U inputs the PWM signals DUU and DUL on the inverter 12 side from the insulating elements 17 and 18, that is, the gate voltages of the IGBTs 29UU and 29UL, and the monitoring signal SU which is the logical sum and inverted signal of these input signals. Is output. The signal generation circuit 31V inputs the PWM signals DVU and DVL on the inverter 12 side from the insulating elements 19 and 20, that is, the gate voltages of the IGBTs 29VU and 29VL, and outputs a monitoring signal SV that is a logical sum and an inverted signal of these input signals. . The signal generation circuit 31W inputs the PWM signals DWU and DWL on the inverter 12 side from the insulating elements 21 and 22, that is, the gate voltages of the IGBTs 29WU and 29WL, and outputs a monitoring signal SW that is a logical sum and an inverted signal of these input signals. . The monitoring signals SU to SW are given to the abnormality detection circuit 32 via the insulating elements 23 to 25, respectively.

  In the above configuration, the monitoring signals SU to SW output from the signal generation circuits 31U to 31W are signals obtained by inverting the logical sum of two complementary PWM signals respectively applied to the upper and lower arms of the corresponding phase. Therefore, the abnormality detection circuit 32 can detect an abnormality in the half bridge circuits 30U to 30W by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signals SU to SW.

(4) First Configuration Example When Applying Monitoring Circuit to DC / DC Converter System A DC / DC converter system 61 shown in FIG. 10 includes a DC / DC converter 62, a DC power supply 63 that is a battery, a control circuit 64, and a load. 65, capacitors 66 and 67, a monitoring circuit 68, and the like. In this case, signal input / output is performed between the high-voltage part and the low-pressure part via insulating elements 69 to 71 configured by, for example, a photocoupler.

  The DC / DC converter 62 includes IGBTs 72U and 72L and an inductor 73. The IGBTs 72U and 72L (corresponding to switching elements) have the same configuration as the IGBTs 29UU to 29WL shown in FIG. The IGBTs 72U and 72L are connected in series between the power supply lines 74 and 75, and constitute a half-bridge circuit 76. Inductor 73 is connected between power supply line 77 and interconnection node Na of IGBTs 72U and 72L.

  The DC / DC converter 62 performs a boosting operation of boosting and outputting the DC voltage Vdc supplied from the DC power supply 63 via the power supply lines 77 and 75. The DC / DC converter 62 is a synchronous rectification type DC / DC converter that performs the boosting operation by switching the IGBTs 72U and 72L according to the PWM signals DU and DL supplied from the control circuit 64 via the insulating elements 69 and 70. It is. The output voltage of the DC / DC converter 62 is given to the load 65 via the power supply lines 74 and 75. The load 65 is, for example, an inverter that drives a motor. A capacitor 66 is connected between the power lines 77 and 75, and a capacitor 67 is connected between the power lines 74 and 75.

  The monitoring circuit 68 monitors the operation of the half bridge circuit 76, and includes a signal generation circuit 78, an abnormality detection circuit 79, and the like. The signal generation circuit 78 receives the signals of the sense emitters of the IGBTs 72U and 72L, and outputs a monitoring signal Sa that is a logical sum and an inverted signal of these input signals. The monitoring signal Sa is given to the abnormality detection circuit 79 via the insulating element 71.

  In the above configuration, the sense emitter signals of the IGBTs 72U and 72L change according to the PWM signals DU and DL, and represent the drive states of the IGBTs 72U and 72L. Therefore, the monitoring signal Sa output from the signal generation circuit 78 is a signal equivalent to a signal obtained by inverting the logical sum of two complementary PWM signals DU and DL. Therefore, the abnormality detection circuit 79 can detect an abnormality in the half bridge circuit 76 by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signal Sa.

  In the above configuration, the DC / DC converter 62 can also perform a step-down operation for stepping down and outputting a DC voltage given (regenerated) from the load 65 side such as an inverter. The DC / DC converter 62 performs the switching operation of the IGBTs 72U and 72L in accordance with the PWM signals DU and DL when performing such a step-down operation as in the case of performing the step-up operation. Therefore, the abnormality detection circuit 79 can detect an abnormality related to the operation in both cases where the DC / DC converter 62 performs the step-up operation and the step-down operation.

(5) Second Configuration Example When Applying Monitoring Circuit to DC / DC Converter System The DC / DC converter system 81 shown in FIG. 11 is different from the DC / DC converter system 61 of the first configuration example shown in FIG. The difference is that the insulating element 71 is omitted and the input signal to the signal generation circuit 78 is changed. In FIG. 11, illustration of the sensing emitters and shunt resistors Rs of the IGBTs 72U and 72L is omitted. In this case, the signal generation circuit 78 receives the PWM signals DU and DL on the control circuit 64 side from the insulating elements 69 and 70, and outputs a monitoring signal Sa that is a logical sum and an inverted signal of these input signals. The monitoring signal Sa is given to the abnormality detection circuit 79.

  In the above configuration, the monitoring signal Sa output from the signal generation circuit 78 is a signal obtained by inverting the logical sum of two complementary PWM signals DU and DL. Therefore, the abnormality detection circuit 79 can detect an abnormality in the half bridge circuit 76 by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signal Sa.

(6) Third Configuration Example When Applying Monitoring Circuit to DC / DC Converter System The DC / DC converter system 91 shown in FIG. 12 is different from the DC / DC converter system 61 of the first configuration example shown in FIG. The difference is that the input signal to the signal generation circuit 78 is changed. In FIG. 12, illustration of the sense emitters and shunt resistors Rs of the IGBTs 72U and 72L is omitted. In this case, the signal generation circuit 78 inputs the PWM signals DU and DL on the DC / DC converter 62 side from the insulating elements 69 and 70, that is, the gate voltages of the IGBTs 72U and 72L, and is a logical sum and inverted signal of these input signals. The monitoring signal Sa is output. The monitoring signal Sa is given to the abnormality detection circuit 79 via the insulating element 71.

  In the above configuration, the monitoring signal Sa output from the signal generation circuit 78 is a signal obtained by inverting the logical sum of two complementary PWM signals DU and DL. Therefore, the abnormality detection circuit 79 can detect an abnormality in the half bridge circuit 76 by performing the switching abnormality determination process and the dead time abnormality determination process described above based on the monitoring signal Sa.

  Among the above configuration examples that are specific application examples of the monitoring circuit, (1), (3), (4), and (6) are configurations that perform abnormality determination based on the signal of the high-voltage unit. 2) and (5) are configurations that perform abnormality determination based on the signal of the low-pressure part. In the case of a configuration in which abnormality determination is performed based on a signal from the high voltage section, abnormality determination is performed based on a signal that more accurately represents the driving state of the switching elements that constitute the half-bridge circuit, so the determination accuracy is increased. There is an advantage. On the other hand, in the configuration in which abnormality determination is performed based on the signal of the low-voltage part, there is an advantage that the number of insulating elements can be reduced as compared with the conventional configuration in which all PWM signals are monitored.

  As described above, in the present embodiment, the two switching elements are based on the number of edges in the predetermined period of the monitoring signal generated based on the signal representing the driving state of the two switching elements constituting the half bridge circuit. Detects abnormalities related to switching operations. As described above, when an abnormality relating to switching occurs, the number of times the monitoring signal changes within a predetermined period tends to decrease. Therefore, the abnormality relating to the switching operation can be reliably detected by the above method. In the present embodiment, an abnormality relating to the dead time is detected based on the pulse width of the monitoring signal. As described above, when an abnormality relating to the dead time occurs, both signal inactive sections of the monitoring signal are not equal to the desired dead time, and thus the abnormality relating to the dead time can be reliably detected by the above method. As described above, according to the present embodiment, it is possible to accurately detect both the abnormality related to the dead time and the abnormality related to the switching operation in the half bridge circuit without increasing the signals to be monitored unnecessarily.

  Further, according to the present embodiment, as shown in FIG. 13, the control circuit 3 and the abnormality detection circuit 5 (control system), the half bridge circuit 2 and the signal generation circuit 4 (drive system) are printed separately from each other. When mounted on the wiring board (control board 92 and drive board 93), the following effects are obtained. That is, in such a case, the control board 92 and the drive board 93 are wired via the board-to-board connector 94. A signal input to the signal generation circuit 4 is a signal on the drive substrate 93. According to such a configuration, for example, the number of pins (the number of wirings) of the board-to-board connector 94 can be reduced as compared with a conventional configuration (for example, a configuration shown in FIG. 14) in which all PWM signals are monitored. Therefore, it is possible to reduce the size of the board-to-board connector 94 and the entire apparatus accordingly.

(Second Embodiment)
The signal generation circuit sets the monitoring signal to the first level in a period (both signal inactive periods) in which both of the signals representing the driving states of the two switching elements constituting the half-bridge circuit represent the off-driving state. The monitoring signal may be set to a second level different from the first level in a period in which at least one of the signals represents the ON drive state. Hereinafter, a configuration example of the monitoring circuit in which the configuration of the signal generation circuit is changed will be described with reference to FIGS.

  The signal generation circuit 102 included in the monitoring circuit 101 illustrated in FIG. 15 is configured by an OR circuit. The signal generation circuit 102 generates a monitoring signal that represents a logical sum of two input signals. The monitoring signal generated by the signal generation circuit 102 has a waveform as shown in (c) of FIGS. That is, the monitoring signal generated by the signal generation circuit 102 is a signal obtained by inverting the monitoring signal generated by the signal generation circuit 4 (see FIG. 2 to FIG. 4C). In this case, for the monitoring signal, the low level corresponds to the first level, and the high level corresponds to the second level. Therefore, the period during which the monitor signal is at the low level (first level) corresponds to both signal inactive sections. Also with the monitoring circuit 101 having such a configuration, the same operation and effect as the monitoring circuit 1 shown in FIG. 1 can be obtained.

  The switching elements constituting the half-bridge circuit 111 shown in FIGS. 19 and 20 are turned on when a low level PWM signal is applied, and are turned off when a high level PWM signal is applied (Low-Active). The signal generation circuit 113 provided in the monitoring circuit 112 illustrated in FIG. 19 is configured by a NAND circuit. The signal generation circuit 113 receives two Low-Active PWM signals or signals that change in accordance with them. The signal generation circuit 113 generates a monitor signal that is a logical product of two input signals and is inverted. The monitoring signal in such a configuration is the same signal as the monitoring signal shown in FIGS. Therefore, the monitoring circuit 112 having such a configuration can provide the same operations and effects as the monitoring circuit 1 shown in FIG.

  On the other hand, the signal generation circuit 115 included in the monitoring circuit 114 illustrated in FIG. 20 is configured by an AND circuit. The signal generation circuit 115 generates a monitoring signal that represents a logical product of two input signals. The monitoring signal in such a configuration is the same signal as the monitoring signal shown in FIG. Therefore, the same operation and effect as the monitoring circuit 1 shown in FIG.

(Third embodiment)
Hereinafter, a third embodiment in which the content of the switching abnormality determination process is changed with respect to each of the above embodiments will be described with reference to FIG.
The abnormality detection circuit according to the present embodiment performs interrupt processing (edge processing) having the contents as shown in FIG. 21 for each edge of the monitoring signal supplied from the signal generation circuit. This interrupt process is a process of incrementing the number of edges (step X1). Further, the abnormality detection circuit executes the control of the contents shown in FIG. 5 for each measurement period. In this case, however, the measurement of the number of edges in the measurement period is realized by the interrupt process shown in FIG. 21 without using the timer function of the microcomputer as in the first embodiment. Even in the present embodiment in which the content of the switching abnormality determination process is changed as described above, the same operations and effects as those of the above embodiments can be obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment in which the content of the dead time abnormality determination process is changed with respect to each of the above embodiments will be described with reference to FIGS. 22 and 23.
The dead time abnormality determination process of the present embodiment includes a dead time acquisition process and a dead time determination process. The dead time acquisition process has the contents shown in FIG. 22 and is executed every switching half cycle. When the dead time acquisition process is started, first, both signal inactive sections of the monitoring signal are acquired (step Y1). In the subsequent step Y2, both signal inactive sections acquired in step Y1, that is, the actual measurement time of the dead time are integrated. After the execution of step Y2, the process ends. Such dead time integration is not limited to software, but may be realized by a function (hardware) such as a timer provided in the microcomputer.

  The dead time determination process has a content as shown in FIG. 23 and is executed every cycle longer than the execution cycle of the dead time acquisition process. When the dead time determination process is started, step Z1 is first executed. In step Z1, it is determined whether or not the accumulated value of dead time accumulated in the dead time acquisition process is within a specified range. In this case, the lower limit of the specified range is defined as the first time, and the upper limit is defined as the second time. Note that the second time may be an infinite time for the same reason as in the first embodiment.

  When the integrated value of the dead time is a value within the specified range, “YES” is determined in the step Z1, and the process proceeds to the step Z2. In step Z2, the accumulated dead time is cleared. After execution of step Z2, the process ends. On the other hand, when the integrated value of the dead time is outside the specified range, “NO” is determined in the step Z1, and the process proceeds to the step Z3. In step Z3, a fail-safe process similar to step T4 shown in FIG. 6 is executed. After execution of step Z3, the process ends.

  Also according to the present embodiment described above, the same operations and effects as the above-described embodiments can be obtained. In addition, according to the present embodiment, since the abnormality of the dead time is determined based on the integrated value obtained by integrating the dead time in a relatively long period, erroneous determination due to the influence of noise on the PWM signal, the monitoring signal, and the like Occurrence can be prevented. Moreover, since the dead time is determined every relatively long period, the speed of abnormality detection is slightly reduced, but the processing load on the microcomputer constituting the abnormality detection circuit is reduced.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The following changes may be added to the switching abnormality determination process shown in FIG. For example, if the number of edges does not match the specified number of times, it may be determined that an abnormality relating to the switching operation has occurred and the fail-safe process may be executed. In this way, it is possible to prevent erroneous determination due to the influence of noise on the PWM signal, the monitoring signal, and the like. Further, when the measurement period is a relatively long period (for example, a period that is twice or more of the carrier period), step S4 is a process for determining whether the number of edges is a value within a specified range. It may be replaced. Even in this case, it is possible to prevent erroneous determination due to the influence of noise.

  The following changes may be made to the dead time abnormality determination process shown in FIG. For example, when both signal inactive sections are outside the specified range for two or more consecutive times, it may be determined that an abnormality relating to the dead time has occurred and the fail-safe process may be executed. In this way, it is possible to prevent erroneous determination due to the influence of noise on the PWM signal, the monitoring signal, and the like.

  In addition, after the execution of step T3, if both signal inactive sections (actual values of dead time) acquired in step T1 do not coincide with the desired dead time values (target values), the PWM is adjusted so that the difference is eliminated. Processing for correcting the signal (corresponding to dead time correcting means) may be added. In this way, even when the dead time deviates from a desired value (ideal value) due to element degradation or individual differences, the dead time correction processing (feedback control) as described above is performed, so that the half bridge It is possible to perform ideal switching in the circuit.

  The following changes may be made to the dead time abnormality determination process of the fourth embodiment. That is, in step Y1 of the dead time acquisition process, the accumulated number of dead times is stored. Then, in step Z1 of the dead time determination process, an appropriate specified range is set based on the stored integration count, and it is determined whether or not the integrated value of the dead time is a value within the set specified range. In this way, even when the switching cycle is variable, it is possible to accurately detect an abnormality relating to dead time.

  In the drawing, 1, 16, 68, 101, 112, 114 are monitoring circuits, 2, 30U-30W, 76, 111 are half bridge circuits, 3, 14, 64 are control circuits, 4, 31U-31W, 78, 102. 113, 115 are signal generation circuits, 5, 32, 79 are abnormality detection circuits, 29UU to 29WL, 72U, 72L are IGBTs (switching elements), 92 is a control board (printed wiring board), 93 is a drive board (printed wiring) Reference numeral 94 denotes a board-to-board connector.

Claims (7)

Half-bridge circuit (2, 30U-30W, 76, 111) having two switching elements (29UU-29WL, 72U, 72L) that are driven complementarily while providing a dead time in which both are turned off A monitoring circuit (1, 16, 68, 101, 112, 114) for monitoring the operation;
A signal generation circuit (4, 31U to 31W, 78, 102, 113, 115) for generating a monitoring signal based on two driving state signals representing driving states of the two switching elements;
An abnormality detection circuit (5, 32, 79) for detecting an abnormality relating to the half-bridge circuit based on the monitoring signal;
With
The signal generation circuit sets the monitoring signal to the first level during a period in which both of the two driving state signals indicate the off driving state, and a period in which at least one of the two driving state signals indicates the on driving state. In this case, the monitoring signal is set to a second level different from the first level,
The abnormality detection circuit detects an abnormality relating to the switching operation of the two switching elements based on the number of edges within the predetermined period of the monitoring signal, and detects an abnormality relating to the dead time based on the pulse width of the monitoring signal. A monitoring circuit characterized by: In the control circuit for generating a drive signal for driving the two switching elements and the half-bridge circuit, the high voltage unit operating at a relatively high voltage and the low voltage unit operating at a relatively low voltage are electrically insulated. And
The monitoring circuit according to claim 1, wherein the driving state signal is a signal of the low-voltage unit. In the control circuit for generating a drive signal for driving the two switching elements and the half-bridge circuit, the high voltage unit operating at a relatively high voltage and the low voltage unit operating at a relatively low voltage are electrically insulated. And
The monitoring circuit according to claim 1, wherein the driving state signal is a signal of the high voltage unit. The control circuit that generates a drive signal for driving the two switching elements, the abnormality detection circuit, the half-bridge circuit, and the signal generation circuit are mounted on separate printed wiring boards (92, 93). And wired via the board-to-board connector (94),
The monitoring circuit according to any one of claims 1 to 3, wherein the driving state signal is a signal on a printed wiring board on which the half-bridge circuit is mounted. The two driving state signals are logic signals indicating that the switching element is in an on state when it is at a high level and that it is in an off state when it is at a low level,
5. The signal generation circuit (4, 31U to 31W, 78, 102) is configured as an OR circuit or a NOR circuit that calculates a logical sum of the two drive state signals. The monitoring circuit according to any one of the above. The two driving state signals are logic signals indicating that the switching element is in an off state when it is at a high level and that it is in an on state when at a low level,
5. The signal generation circuit (31 </ b> U to 31 </ b> W, 78, 113, 115) is configured as an AND circuit or a NAND circuit that calculates a logical product of the two drive state signals. The monitoring circuit according to any one of the above.   Dead time correction means for measuring the dead time based on a period in which the monitoring signal is at the first level and correcting a drive signal for driving the two switching elements based on the measurement result. The monitoring circuit according to any one of claims 1 to 6, wherein the monitoring circuit is provided.

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