JP5977947B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5977947B2
JP5977947B2 JP2012001723A JP2012001723A JP5977947B2 JP 5977947 B2 JP5977947 B2 JP 5977947B2 JP 2012001723 A JP2012001723 A JP 2012001723A JP 2012001723 A JP2012001723 A JP 2012001723A JP 5977947 B2 JP5977947 B2 JP 5977947B2
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Prior art keywords
substrate
semiconductor layer
semiconductor substrate
hydrogen
semiconductor
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Expired - Fee Related
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JP2012001723A
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English (en)
Japanese (ja)
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JP2012160713A5 (enExample
JP2012160713A (ja
Inventor
純一 肥塚
純一 肥塚
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2012001723A priority Critical patent/JP5977947B2/ja
Publication of JP2012160713A publication Critical patent/JP2012160713A/ja
Publication of JP2012160713A5 publication Critical patent/JP2012160713A5/ja
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    • H10P90/1916—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H10W10/181—

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2012001723A 2011-01-14 2012-01-09 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5977947B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012001723A JP5977947B2 (ja) 2011-01-14 2012-01-09 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2011005490 2011-01-14
JP2011005490 2011-01-14
JP2012001723A JP5977947B2 (ja) 2011-01-14 2012-01-09 Ｓｏｉ基板の作製方法

Publications (3)

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JP2012160713A JP2012160713A (ja) 2012-08-23
JP2012160713A5 JP2012160713A5 (enExample) 2015-02-26
JP5977947B2 true JP5977947B2 (ja) 2016-08-24

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JP2012001723A Expired - Fee Related JP5977947B2 (ja) 2011-01-14 2012-01-09 Ｓｏｉ基板の作製方法

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US (1) US8877607B2 (enExample)
JP (1) JP5977947B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6295815B2 (ja) * 2014-05-13 2018-03-20 株式会社Sumco 貼り合わせウェーハの製造方法
JP6539959B2 (ja) * 2014-08-28 2019-07-10 株式会社Sumco エピタキシャルシリコンウェーハおよびその製造方法、ならびに、固体撮像素子の製造方法
CN110349843B (zh) * 2019-07-26 2021-12-21 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、生物识别器件、显示装置
JP7551371B2 (ja) * 2020-07-15 2024-09-17 太陽誘電株式会社 ウエハの製造方法、弾性波デバイスおよびその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
US20020089032A1 (en) 1999-08-23 2002-07-11 Feng-Yi Huang Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen
JP4507395B2 (ja) * 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
US6583440B2 (en) 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP2004039735A (ja) * 2002-07-01 2004-02-05 Fujitsu Ltd 半導体基板及びその製造方法
CN100397595C (zh) 2003-02-14 2008-06-25 三菱住友硅晶株式会社 硅片的制造方法
JP2011151318A (ja) * 2010-01-25 2011-08-04 Renesas Electronics Corp 半導体装置およびその製造方法
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法

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Publication number Publication date
JP2012160713A (ja) 2012-08-23
US8877607B2 (en) 2014-11-04
US20120184085A1 (en) 2012-07-19

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