JP5968693B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device having a cache memory.

Conventionally, a method for speeding up memory access is known.
In the memory access method of Patent Document 1 (Japanese Patent Laid-Open No. 2001-142698), the main storage device stores a program described by a plurality of instruction codes, and the central processing unit is stored in the storage device. The program is read and the instruction is executed according to the instruction code described in the read program. The instruction memory can be read faster than the main memory, and the address where the instruction code of the next instruction to be executed next to the instruction being executed by the central processing unit is stored is the address of the instruction being executed. For an address discontinuous instruction that is not continuous with the address where the instruction code is stored, the instruction code of the address discontinuous instruction is stored. The high-speed access control unit detects that the next instruction is an address discontinuous instruction, and in the case of an address discontinuous instruction, searches the instruction code of the address discontinuous instruction stored in the instruction memory to search the instruction memory. The instruction code of the address discontinuous instruction is obtained from the data, and the obtained instruction code is transferred to the central processing unit.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2006-293748) reads the number of skip bits set for the head address by enabling the number of skip bits to be set in the input interface of the information processing module. An information processing apparatus is described in which processing can be started after skipping, so that input data can be correctly supplied from an area that is not n-bit aligned.

JP 2001-142698 A JP 2006-293748 A

  However, in the methods of Patent Document 1 and Patent Document 2, instructions such as branch destination instructions may be registered across a plurality of cache lines, the cache hit rate does not increase, and memory access wait occurs. There's a problem.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a main memory having a bit width of N bits, a cache memory having a cache line of L (N × X: X is an integer of 2 or more) bit width, and a cache control unit. When registering an M-bit (2 × M ≦ L) instruction stored in the main memory in the cache memory, the cache control unit includes N-bit read unit data including the head of the instruction and the following (X -1) Register N-bit read unit data in one cache line.

  According to one embodiment, the cache hit rate can be improved.

It is a figure showing the structure of the semiconductor device of 1st Embodiment. It is a figure showing the structure of the semiconductor device of 2nd Embodiment. It is a figure showing the instruction | command memorize | stored in the instruction | indication memory of 2nd Embodiment. (A) is a figure showing the valid bit (V0, V1) memorize | stored in V bit memory, and the tag address (A3-A24) memorize | stored in a tag memory. (B) is a diagram showing data of one cache line stored in the cache data memory. It is a figure showing the example of 1 structure of an address comparator. It is a figure for demonstrating the example in which a branch destination instruction is cached in the conventional cache system. It is a figure for demonstrating another example by which the branch destination instruction is cached in the conventional cache system. It is a figure for demonstrating the example by which the branch destination instruction is cached in the cache system of 2nd Embodiment. It is a figure for demonstrating another example in which the branch destination instruction is cached in the cache system of 2nd Embodiment. It is a figure for demonstrating operation | movement of the sequencer which controls the process which registers a branch destination instruction into cache memory. It is a figure which shows the operation example in case a branch destination instruction hits. It is a figure which shows the operation example when a branch destination instruction misses. It is a figure showing the structure of the address comparator of 3rd Embodiment. It is a figure showing the input-output control part of 3rd Embodiment. It is a figure showing the storage state in case two branch destination instructions are stored in one cache line. It is a figure showing the structure of the semiconductor device of 4th Embodiment. It is a figure showing the instruction | command memorize | stored in the instruction | indication memory of 4th Embodiment. (A) is a figure showing the valid bit (V0, V1, V2) memorize | stored in V bit memory, and the tag address (A2-A24) memorize | stored in a tag memory. (B) is a diagram showing data of one cache line stored in the cache data memory. It is a figure for demonstrating operation | movement of the sequencer which controls the process which registers a branch destination instruction into cache memory. It is a figure showing the structure of the semiconductor device of 5th Embodiment. It is a figure for demonstrating registration to a cache data memory. It is a figure for demonstrating reading from a cache data memory.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment.

  Referring to FIG. 1, the semiconductor device 1 includes an instruction memory 8 that is a main memory and a CPU 2.

  The CPU 2 includes a CPU core 4, a cache memory 3, and a cache control unit 81.

The instruction memory 8 has a bit width of N bits. It is assumed that the position of an instruction is designated by s bits in N-bit read unit data. For example, s = log ₂ (N / 8). When N = 64, it is 3.

  The cache memory 3 has a cache line of L (N × X: X is a natural number of 2 or more) bit width. The cache memory 3 stores a tag address representing the storage position of the data of each cache line in the instruction memory.

  When registering an M-bit (2 × M ≦ L) instruction stored in the instruction memory 8 in the cache memory, the cache control unit 81 follows the N-bit read unit data including the head of the instruction, (X-1) N-bit read unit data is registered in one cache line. However, X is a natural number of 2 or more.

  More specifically, the cache control unit 81 reads the N-bit read unit data specified by the first address with the lower s bits of the address specifying the instruction as 0, and the following (X-1 ) N-bit read unit data is registered in the cache line. In addition, the cache control unit 81 registers the portion excluding the lower s bits of the first address in the cache memory 3 as a tag address designating the cache line.

  As described above, according to this embodiment, since the entire instruction is registered in one cache line, the cache hit rate can be improved.

[Second Embodiment]
In the second embodiment, a preferred configuration for caching a branch destination instruction will be described.

FIG. 2 is a diagram illustrating the configuration of the semiconductor device according to the second embodiment.
Referring to FIG. 2, the semiconductor device 1 includes a CPU (Central Processing Unit) 2, a ROM (Read Only Memory) 5, a RAM (Random Access Memory) 7, and a CIF (Cpu InterFace) 6.

  The CIF 6 controls the exchange of data and instructions between the RAM 7 and ROM 5 and the CPU 2. The ROM 5 includes an instruction memory 8 that stores instructions.

  The CPU core 4 and the ROM 5 and the CPU core 4 and the RAM 7 are connected via a CIF 6 via a 64-bit bus.

  The CPU 2 includes a CPU core 4, a cache memory 3, and a cache control unit 81.

The CPU core 4 decodes and executes the instruction.
The cache memory 3 includes a cache data memory 9, a tag memory 11, and a V bit memory 13.

  The cache control unit 81 includes an LRU (Least Recently Used) 15, an input / output control unit 10, an address comparator 12, a V bit control unit 14, an LRU control unit 16, a first queue 17, and a second queue. 18 and a sequencer 19.

  The instruction memory 8 has a bit width of 64 bits. The position of the instruction is specified by 3 bits (A0 to A2) in the 64-bit read unit data. The position of the instruction in the instruction memory 8 is specified by a 25-bit address (A0 to A24). The address of the read unit data in the instruction memory 8 is specified by a 22-bit address (A3 to A24).

  The cache data memory 9 has a 128-bit width cache line. That is, two consecutive read unit data in the instruction memory 8 are stored. Of the two read unit data of the cache line, the read unit data stored in the instruction memory 8 with the smaller address is the first 64-bit data, and the read unit data stored in the instruction memory 8 with the larger address Is called the latter 64-bit data.

  The tag memory 11 stores tag addresses (A3 to A24). The tag address represents an address in the instruction memory 8 of 64-bit data in the first half of the corresponding cache line.

  The V bit memory 13 stores valid bits V0 and V1. When the valid bit V0 is "1", the first 64-bit data of the corresponding cache line is valid, and when the valid bit V0 is "0", the first 64-bit data of the corresponding cache line is invalid. . When the valid bit V1 is “1”, the 64-bit data in the latter half of the corresponding cache line is valid. When the valid bit V1 is “0”, the 64-bit data in the latter half of the corresponding cache line is invalid. .

  One cache line, a tag address corresponding to the cache line, and a valid bit corresponding to the cache line constitute one entry.

The LRU 15 stores information representing lines that have not been used recently.
When registering the branch destination instruction stored in the instruction memory 8 in the cache data memory 9, the input / output control unit 10 stores the 64-bit read unit data including the head of the branch destination instruction and the subsequent 64-bit data. The read unit data is registered in one cache line. Specifically, the I / O controller 10 reads the 64-bit read unit data specified by the first address with the lower three bits of the address specifying the branch destination instruction as 0, and the next 64 bits. Are registered in the cache line. Further, the input / output control unit 10 registers the portion excluding the lower 3 bits of the first address in the tag memory 11 as a tag address designating the cache line.

  Further, the input / output control unit 10 reads 128-bit data of the designated cache line from the cache data memory 9.

  The address comparator 12 compares the tag address (A3 to A24) stored in the tag memory 11 with the address JADDR [24: 3] excluding the lower 3 bits of the address JADDR of the branch destination instruction.

  The V bit control unit 14 controls the update of the valid bits V0 and V1 in the V bit memory 13.

The LRU control unit 16 controls updating of data in the LRU 15.
The first queue 17 temporarily holds 64-bit data of the first half of the cache line read from the cache data memory 9 when the cache hits. The second queue 18 temporarily holds 64-bit data in the latter half of the cache line read from the cache data memory 9 when the cache hits.

FIG. 3 is a diagram showing instructions stored in the instruction memory 8.
The instruction memory 8 stores a variable length instruction, that is, an instruction of 8 bits, 16 bits, 24 bits, 32 bits, 40 bits, 48 bits, 56 bits, or 64 bits. Data is read from the instruction memory 8 in 64-bit units through a 64-bit instruction bus. The addresses (A3 to A24) for designating the position for reading data from the instruction memory 8 are 0b0... 00000000, 0b0 representing the beginning of 64-bit read unit data # 0, data # 1, data # 2,. ... 00001000, 0b0 ... 00010000, ...

  FIG. 4A shows valid bits (V0, V1) stored in the V-bit memory 13 and tag addresses (A3 to A24) stored in the tag memory.

  FIG. 4B shows data of one cache line stored in the cache data memory 9.

  The data of one cache line consists of 128-bit data (D0 to D127). Of the data on one cache line, 64-bit data (D0 to D63) constitutes the first half of 64-bit data, and 64-bit data (D64 to D127) constitutes the second half of 64-bit data.

FIG. 5 is a diagram showing the configuration of the address comparator 12.
Referring to FIG. 5, address comparator 12 includes comparators 21_1 to 21_N, logical product circuits 22_1 to 22_N, and logical sum circuit 23. N is the total number of lines that can be stored in the cache data memory.

  The comparator 21_i (i = 1 to N) compares the tag addresses A3 to A24 of the i-th entry with the address JADDR [24: 3] excluding the lower 3 bits of the address JADDR of the branch destination instruction, and matches. If it does, an “H” level signal is output, and if they do not match, an “L” level signal is output.

The AND circuit 22_i outputs a logical product of the output of the comparator 21_i and the valid bit V0. The OR circuit 23 outputs a logical sum of the AND circuits 22_1 to 22_N. This output is a signal indicating a cache hit or miss. When it is at “H” level, it indicates that the cache has been hit, and when it is at “L” level, it indicates that the cache has been missed. In addition, the cache line corresponding to the tag address of the hit entry is read by the input / output control unit 10.
(Conventional cache method)
FIG. 6 is a diagram for explaining an example in which a branch destination instruction is cached in the conventional cache method.

  In the conventional cache system, the data reading position (alignment boundary) from the instruction memory is fixed. As shown in FIG. 6, when registering the branch destination instruction 100 in the cache data memory, 128-bit data with the start address of 0b0... 00010000 as the alignment boundary is stored in one cache line of the cache data memory. Registered as data.

  FIG. 7 is a diagram for explaining another example in which a branch destination instruction is cached in the conventional cache method.

As shown in FIG. 7, when registering the branch destination instruction 200 in the cache data memory, first, 128-bit data having a start address of 0b0... 00000000 as an alignment boundary is stored in one cache data memory. In this case, only a part of the branch destination instruction 200 is registered in the cache data memory. Therefore, even when the branch destination instruction 200 hits the cache at the time of jump to the branch destination instruction, there is a problem that the performance is not improved due to waiting for memory access.
(Cache method of this embodiment)
FIG. 8 is a diagram for explaining an example in which a branch destination instruction is cached in the cache system according to the present embodiment.

  In the cache system of the present embodiment, the data reading boundary (alignment boundary) from the instruction memory 8 is not fixed. As shown in FIG. 8, when registering the branch destination instruction 100 in the cache data memory 9, 64-bit read unit data including the head of the branch destination instruction 100 (specified by address 0b0... 00010000) Are registered in the first half of the cache line and become the first half of 64-bit data (D0 to D63). Further, the next 64-bit read unit data (specified by 0b0... 00011000) is registered in the second half of the cache line, and becomes the second half 64-bit data (D64 to D127).

  FIG. 9 is a diagram for explaining another example in which a branch destination instruction is cached in the cache system according to the present embodiment.

As shown in FIG. 9, when registering the branch destination instruction 200 in the cache data memory 9, first, 64-bit read unit data (address 0b0... 00001000 including the head of the branch destination instruction 200 is specified. Are registered in the first half of the cache line and become the first half of 64-bit data (D0 to D63). Further, the next 64-bit read unit data (specified by 0b0... 00010000) is registered in the second half of the cache line, and becomes the second half 64-bit data (D64 to D127). In this case, since all of the branch destination instructions 200 are registered in the cache data memory 9, the conventional memory access wait does not occur.
(Register to branch destination instruction cache memory)
FIG. 10 is a diagram for explaining the operation of the sequencer 19 that controls the process of registering the branch destination instruction in the cache memory.

The sequencer 19 controls the following processes (1) to (3).
(1) Register tag address, clear valid bit, update LRU.
(2) Write the first half of 64-bit data to the cache data memory and write the valid bit V0.
(3) Write the latter half of 64-bit data to the cache data memory and write the valid bit V1.

  The sequencer 19 is normally in the “IDLE state” and starts registration when a cache miss occurs. When the registration starts, the sequencer 19 executes the above (1) and shifts to the “D0 waiting state”. Thereafter, when the sequencer 19 receives the first half of the data, it executes (2) and shifts to the “D1 waiting state”. Finally, when the sequencer 19 accepts the second half of the data, it executes (3) and returns to the “IDLE” state.

  Note that the sequencer 19 performs a branch when waiting for registration data, and may end registration without filling one cache line when a branch destination instruction hits the cache. The sequencer 19 may branch when waiting for registration data, and may start registration of another cache line when a branch destination instruction misses in the cache.

(Action when hit)
FIG. 11 is a diagram illustrating an operation example when a branch destination instruction hits.

  Referring to FIG. 11, CPU core 4 executes branch instruction JUMP specifying branch destination address JADDR (here, address @A of instruction A).

  The address comparator 12 sets the cache hit signal brahit to the “H” level because any of the tag addresses matches the portion JADDR [24: 3] excluding the lower 3 bits of the branch destination address.

  Since the valid bit V 0 is “1” indicating that the valid bit V 0 is valid, the sequencer 19 sends the first half 64-bit data brad0 [63: 0] of the hit cache line in the cache data memory to the first queue 17. Here, the first half of 64-bit data includes instruction A and instruction B.

  Further, since the valid bit V1 is “1” indicating that the valid bit V1 is valid, the sequencer 19 sends the second half 64-bit data bradat1 [127: 64] of the hit cache line in the cache data memory to the second queue 18. Here, it is assumed that the latter 64-bit data includes instruction C and instruction D.

The LRU control unit 16 registers the address of the instruction A at the head of the LRU.
The sequencer 19 sequentially sends the instructions in the first queue 17 and the second queue 18 to the CPU core 4, and the instructions are decoded by the CPU core 4. After the instruction C is decoded, the CPU core 4 executes the branch instruction JUMP specifying the branch destination address JADDR (here, the address @E of the instruction E).

  The address comparator 12 sets the cache hit signal brahit to the “H” level because any of the tag addresses matches the portion JADDR [24: 3] excluding the lower 3 bits of the branch destination address.

  Since the valid bit V 0 is “1” indicating that the valid bit V 0 is valid, the sequencer 19 sends the first half 64-bit data brad0 [63: 0] of the hit cache line in the cache data memory to the first queue 17. Here, the first half of 64-bit data includes instruction E and instruction F.

  Since the valid bit V1 is “0” indicating invalidity, the sequencer 19 does not send the second half 64-bit data bradat1 [127: 64] of the hit cache line in the cache data memory to the second queue 18.

The LRU control unit 16 registers the address of the instruction E at the head of the LRU.
The sequencer 19 sequentially sends the instructions in the first queue 17 to the CPU core 4, and the instructions are decoded by the CPU core 4.

(Operation at the time of mistake)
FIG. 12 is a diagram illustrating an operation example when a branch destination instruction misses.

  Referring to FIG. 12, CPU core 4 executes a branch instruction JUMP that designates branch destination address JADDR (here, address @A of instruction A).

  In the address comparator 12, the portion JADDR [24: 3] excluding the lower 3 bits of the branch destination address does not match any of the tag addresses, so the cache hit signal brahit does not become “H” level.

  The sequencer 19 writes the portion excluding the lower 3 bits of the branch destination address JADDR as tag addresses A3 to A24.

The LRU control unit 16 registers the address of the instruction A at the head of the LRU.
The CPU core 4 outputs a request signal REQ and receives a response signal ACQ transmitted from the instruction memory 8 in response thereto. The V bit control unit 14 clears the valid bits V0 and V1 to “0” and “0”.

  When the CPU core 4 receives the first-half 64-bit data D0 from the instruction memory 8, the CPU core 4 writes the first-half 64-bit data D0 in the first-half position of the corresponding cache line of the cache data memory. When receiving the completion signal END from the instruction memory 8, the V bit control unit 14 sets the valid bit V 0 to “1”.

  The CPU core 4 further outputs a request signal REQ, and receives a response signal ACQ transmitted from the instruction memory 8 in response thereto. When the CPU core 4 receives the latter half 64-bit data D1 from the instruction memory 8, it writes the latter half 64-bit data D1 in the latter half position of the corresponding cache line of the cache data memory. When receiving the completion signal END from the instruction memory 8, the V bit control unit 14 sets the valid bit V 1 to “1”.

  As described above, according to the present embodiment, the entire branch destination instruction can be held in one cache line regardless of where the head of the branch destination instruction is in the instruction memory. As a result, when a cache hit occurs, execution of the branch destination instruction can be started without waiting for memory access.

[Third Embodiment]
In the second embodiment, the head of the branch destination instruction in the first half of the cache line is searched at the time of jump. However, another branch destination instruction may be stored in the second half of the cache line. By making this branch destination instruction a search target, the hit rate can be improved. In the third embodiment, an address corresponding to the latter 64-bit data is calculated from the tag address and used for hit determination.

FIG. 13 is a diagram illustrating the configuration of the address comparator according to the third embodiment.
Referring to FIG. 13, address comparator 512 includes comparators 21_1 to 21_N, 25_1 to 25_N, AND circuits 22_1 to 22_N, 26_1 to 26_N, OR circuits 23 and 27, and adders 24_1 to 24_N. , An OR circuit 28 and an AND circuit 29 are provided. However, N is the total number of cache lines that can be stored in the cache data memory. The comparator 21_i (i = 1 to N) is a subordinate of the tag addresses A3 to A24 of the i-th entry and the address JADDR of the branch destination instruction. The address JADDR [24: 3] excluding 3 bits is compared, and if they match, an “H” level signal is output, and if they do not match, an “L” level signal is output.

  The AND circuit 22_i outputs a logical product of the output of the comparator 21_i and the valid bit V0. This output is a signal indicating the hit or miss of the first half of the cache line. When it is at “H” level, it indicates that the first half of one of the cache lines has been hit. Indicates that the first half of the cash line missed.

The logical sum circuit 23 outputs a logical sum of the outputs of the logical product circuits 22_1 to 22_N.
The adder 24_i adds “1” to the tag addresses A3 to A24 of the i-th entry, and outputs the next address of the tag address. Since the address in the instruction memory 8 of the first 64-bit data of the cache line with the tag address is indicated, the address next to the tag address is the address in the instruction memory 8 of the second half 64-bit data of the same cache line. Indicates.

  The comparator 25_i compares the address next to the tag addresses A3 to A24 of the i-th entry output from the adder 24_i and the address JADDR [24: 3] excluding the lower 3 bits of the address JADDR of the branch destination instruction. If they match, an “H” level signal is output, and if they do not match, an “L” level signal is output.

  The AND circuit 26_i outputs a logical product of the output of the comparator 25_i and the valid bit V1.

  The OR circuit 27 outputs a logical sum of the outputs of the AND circuits 26_1 to 26_N. This output is a signal indicating a hit or miss in the second half of the cache line. When it is at the “H” level, it indicates that the second half of any cache line has been hit. Indicates that the second half of the cash line has missed.

  The logical sum circuit 28 outputs a logical sum of the output of the logical sum circuit 23 and the output of the logical sum circuit 28. This output is a signal indicating a hit or miss of the cache line. When it is “H” level, it indicates that one of the cache lines hit in the first half or the second half, and when it is “L” level, Indicates that the cache line has missed. In addition, the cache line corresponding to the tag address of the hit entry is read by the input / output control unit 10.

FIG. 14 is a diagram illustrating an input / output control unit according to the third embodiment.
The input / output control unit 10 includes a selector 70 and a shifter 51.

  The selector 70 outputs 128-bit data “D0 to D127” of the hit cache line.

  When the first half of the cache line hits, the output of the selector 70 is sent to the CPU core 4 as in the second embodiment.

  When data in the latter half of the cache line is hit, the shifter 51 right-shifts “D0 to D127” output from the selector 70 by 64 bits. As a result, the 0th to 63rd bits are sent to the CPU core 4 as “D64 to D127” (the latter 64 bits of data), and the 64th to 127th bits as dummy data.

  FIG. 15 is a diagram illustrating a storage state when two branch destination instructions are stored in one cache line.

  The beginning of the branch destination instruction 100 is located in the first half of the cache line, and the beginning of the branch destination instruction 200 is located in the second half of the cache line.

  In the second embodiment, even if two branch destination instructions are registered in one cache line, only the branch destination instruction 100 whose head is included in 64-bit data in the first half of the cache line is subject to cache hit determination. Become. On the other hand, in the present embodiment, the branch destination instruction 200 whose head is included in the latter half of the 64-bit data of the cache line is also subject to cache hit determination.

  As described above, according to the present embodiment, the address obtained by adding 1 to the tag address can be increased in the cache hit rate as compared with the second embodiment by adding to the address comparison.

[Fourth Embodiment]
In this embodiment, a case where the unit of reading data from the instruction memory is smaller than that in the second embodiment will be described.

FIG. 16 is a diagram illustrating the configuration of the semiconductor device of the fourth embodiment.
The semiconductor device 101 in FIG. 16 is different from the semiconductor device 1 in FIG. 2 as follows.

  The CPU core 4 and the ROM 5 and the CPU core 4 and the RAM 7 are connected via a CIF 6 by a 32-bit instruction bus.

  The instruction memory 108 has a bit width of 32 bits. The position of the instruction is designated by 2 bits (A0 to A1) in the 32-bit read unit data. The position of the instruction in the instruction memory 108 is designated by a 25-bit address A0 to A24.

  The cache data memory 9 has a 128-bit width cache line. That is, the cache data memory 9 stores four consecutive read unit data in the instruction memory 108. For the four read unit data in the cache line, the first 32-bit data, the second 32-bit data, and the third 32 in order from the read unit data stored in the instruction memory 108 with the smaller address. It will be referred to as bit data, the fourth 32-bit data.

  The V bit memory 113 stores valid bits V0, V1, and V2. The valid bit V0 is a bit indicating whether the first 32-bit data of the cache line is valid or invalid. The valid bit V1 is a bit indicating whether the second 32-bit data of the cache line is valid or invalid. The valid bit V2 is a bit indicating whether the third 32-bit data of the cache line is valid or invalid. The valid bit V3 is a bit indicating whether the fourth 32-bit data of the cache line is valid or invalid.

  The tag memory 111 stores the tag address (A2 to A24) of each cache line of the cache data memory 9. The tag address represents the address in the instruction memory 8 of the first 32-bit data of the corresponding cache line.

  When the branch destination instruction stored in the instruction memory 108 is registered in the cache data memory 9, the input / output control unit 110 includes 32-bit read unit data including the head of the branch destination instruction and the subsequent three 32-bit read unit data is registered in one cache line. Specifically, the input / output control unit 110 reads 32-bit read unit data specified by the first address with the lower two bits of the address specifying the branch destination instruction set to 0, and the next three Are registered in the cache line. Further, the input / output control unit 110 registers the portion excluding the lower 2 bits of the first address in the tag memory 111 as a tag address for designating the cache line.

  Further, the input / output control unit 110 reads 128-bit data of the designated cache line from the cache data memory 9.

FIG. 17 is a diagram showing instructions stored in instruction memory 108.
The instruction memory 108 stores variable length instructions, ie, 8-bit, 16-bit, 24-bit, 32-bit, 40-bit, 48-bit, 56-bit, or 64-bit instruction. Data is read from the instruction memory 108 in units of 32 bits through a 32-bit instruction bus. The address for designating the reading position of the data from the instruction memory 108 is 0b0... 0000000, 0b0... 0000100, 0b0, which represents the head of 32-bit data # 0, data # 1, data # 2,. ..0001000, ...

  FIG. 18A shows valid bits (V0, V1, V2) stored in the V-bit memory 113 and tag addresses (A2 to A24) stored in the tag memory 111.

  FIG. 18B shows data of one cache line stored in the cache data memory 9.

  The data for one cache line consists of 128-bit data (D0 to D127). Among the data of one cache line, 32-bit data (D0 to D31) constitutes the first 32-bit data, and 32-bit data (D32 to D63) constitutes the second 32-bit data, The 32-bit data (D64 to D95) constitutes the third 32-bit data, and the 32-bit data (D96 to D127) constitutes the fourth 32-bit data.

(Register to branch destination instruction cache memory)
FIG. 19 is a diagram for explaining the operation of the sequencer 119 that controls the process of registering the branch destination instruction in the cache memory.

The sequencer 119 controls the following processes (1) to (5).
(1) Register tag address, clear valid bit, update LRU.
(2) Write the first 32-bit data to the cache data memory and write the valid bit V0.
(3) Writing the second 32-bit data to the cache data memory and writing the valid bit V1.
(4) Writing the third 32-bit data to the cache data memory and writing the valid bit V2.
(5) Write the fourth 32-bit data to the cache data memory and write the valid bit V3.

  The sequencer 119 is normally in the “IDLE state” and starts registration when a cache miss occurs. The sequencer 119 executes the above (1) by starting registration, and shifts to “D0 waiting state”. After that, when the sequencer 119 receives the first 32-bit data, the sequencer 119 executes (2) and shifts to the “D1 wait state”. After that, the sequencer 119 receives the second 32-bit data. , (3) are executed, and a transition is made to “D2 waiting state”. After that, when the sequencer 119 receives the third 32-bit data, it executes (4) and shifts to the “D3 waiting state”. Finally, when the sequencer 119 receives the fourth 32-bit data, it executes (5) and returns to the “IDLE” state.

  As described above, in this embodiment, even if the bit width of the instruction memory is 1/4 of the bit width of the cache line and 1/2 of the maximum length of the instruction, the same as in the second embodiment. In addition, the entire branch destination instruction can be held in one cache line regardless of where the head of the branch destination instruction is in the instruction memory. As a result, when a cache hit occurs, execution of the branch destination instruction can be started without waiting for memory access.

[Fifth Embodiment]
In the fifth embodiment, the branch destination instruction is shifted and stored in the cache memory.

  In the present embodiment, unlike the first embodiment, the branch destination instruction read from the instruction memory is shifted and stored in the cache memory, so that the branch destination instruction can be stored in a small area of the cache memory. it can.

FIG. 20 is a diagram illustrating the configuration of the semiconductor device of the fifth embodiment.
The semiconductor device 201 in FIG. 20 is different from the semiconductor device 1 in FIG. 2 as follows.

  The cache data memory 209 has a 64-bit width cache line. That is, one read unit data in the instruction memory 8 is stored.

  The branch destination instruction address memory 211 stores branch destination instruction addresses (A0 to A24). The branch destination instruction address includes a tag address (A3 to A24) and an address (A0 to A2) indicating the position of the branch destination instruction in the read data unit.

  The V bit memory 213 stores a valid bit V0. When the valid bit V0 is “1”, the 64-bit data of the corresponding cache line is valid, and when it is “0”, the 64-bit data of the corresponding cache line is invalid.

  One cache line, a branch destination instruction address corresponding to the cache line, and a valid bit corresponding to the cache line constitute one entry.

  When registering the branch destination instruction stored in the instruction memory 8 in the cache data memory 209, the input / output control unit 210 sets the lower three bits of the address designating the branch destination instruction to 0. The 64-bit read unit data designated by the address and the next 64-bit read unit data are read. The input / output control unit 210 shifts the read 128-bit data so that the head of the branch destination instruction comes to the head of the cache line, and registers it in the cache line.

  Further, the input / output control unit 210 uses the portion excluding the lower 3 bits of the first address as a tag address for designating the cache line, and uses the lower 3 bits of the address of the branch destination instruction as the branch destination instruction in the read unit data. Stored in the branch destination instruction address memory 211 as an address representing a position.

  In addition, the input / output control unit 210 reads 64-bit data of the specified cache line from the cache data memory 209.

  The address comparator 212 compares the tag addresses (A3 to A24) stored in the branch destination instruction address memory 211 with the address JADDR [24: 3] excluding the lower 3 bits of the address JADDR of the branch destination instruction. .

  The V bit control unit 214 controls updating of the valid bit V 0 in the V bit memory 213.

FIG. 21 is a diagram for explaining registration in the cache data memory.
Input Output controller 210 includes a shifter 61, shifter 61, only the lower 3 bits of the address JADDR the branch target instruction, to shift the read data of 128 bits read out from the instruction memory 8, 64 Output to a bit-width cache line.

  For example, when the lower 3 bits of the address of the branch destination instruction are “000”, the shifter 61 registers the read 128-bit read data in a 64-bit cache line without shifting.

  When the lower 3 bits of the address of the branch destination instruction are “001”, the shifter 61 right-shifts the read 128-bit read data by 8 bits and registers it in the 64-bit cache line. Similarly, when the lower 3 bits of the address of the branch destination instruction are “010”, the shifter 61 right-shifts the read 128-bit read data by 16 bits and registers it in the 64-bit cache line. To do. When the lower 3 bits of the address of the branch destination instruction are “011”, the shifter 61 right-shifts the read 128-bit read data by 24 bits and registers it in the 64-bit cache line. When the lower 3 bits of the address of the branch destination instruction are “100”, the shifter 61 right-shifts the read 128-bit read data by 32 bits and registers it in the 64-bit cache line. When the lower 3 bits of the address of the branch destination instruction are “101”, the shifter 61 right-shifts the read 128-bit read data by 40 bits and registers it in the 64-bit cache line. When the lower 3 bits of the address of the branch destination instruction are “110”, the shifter 61 right-shifts the read 128-bit read data by 48 bits and registers it in the 64-bit cache line. When the lower 3 bits of the address of the branch destination instruction are “111”, the shifter 61 right-shifts the read 128-bit read data by 56 bits and registers it in the 64-bit cache line.

  As a result, even if the branch destination instruction is maximum (64-bit length), it can be registered in one cache line.

FIG. 22 is a diagram for explaining reading from the cache data memory.
Input Output controller 210 includes a shifter 62, shifter 62, only the value of the lower 3 bits of the branch destination instruction stored in the branch target instruction address memory 211 (A0-A2), read from the cache data memory 209 The outputted 64-bit data is shifted and output to the CPU core 4.

  For example, when the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “000”, the shifter 62 does not shift the branch destination instruction output from the cache data memory 209, and the CPU core 4 Output to. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “001”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 8 bits, and the CPU core Output to 4. Similarly, when the lower 3 bits (A0 to A2) of the branch destination instruction address are “010”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 16 bits. And output to the CPU core 4. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “011”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 24 bits, and the CPU core Output to 4. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “100”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 32 bits to obtain the CPU core. Output to 4. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “101”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 40 bits to obtain the CPU core. Output to 4. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “110”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 48 bits to obtain the CPU core. Output to 4. When the lower 3 bits (A0 to A2) of the address of the branch destination instruction are “111”, the shifter 62 shifts the branch destination instruction output from the cache data memory 209 to the left by 56 bits to obtain the CPU core. Output to 4.

  As described above, according to the present embodiment, the area of the cache memory for storing the branch destination instruction is reduced as compared with the first to fourth embodiments by shifting and storing the instruction at the time of data input / output. can do.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

In addition, a part of the contents described in the embodiment will be described below.
(1) The semiconductor device includes a main memory having a bit width of N bits and a cache memory having a cache line having a bit width of N bits. Further, when registering an M-bit (M ≦ N) instruction stored in the main memory in the cache memory, the semiconductor device includes N-bit read unit data including the head of the instruction and the subsequent N A cache control unit that reads out the read unit data of bits and shifts and registers the read 2N-bit data so that the head of the instruction becomes the head of the cache line.

  1, 101, 201 Semiconductor device, 2 CPU, 3 cache memory, 4 CPU core, 5 ROM, 6 CIF, 7 RAM, 8, 108 Instruction memory, 9,209 Cache data memory, 10, 110, 210 Input / output control unit 11, 111 Tag memory, 12, 212, 512 Address comparator, 13, 113, 213 V bit memory, 14, 114, 214 V bit control unit, 15 LRU, 16 LRU control unit, 17 First queue, 18 2 queues, 19, 119 sequencer, 81 cache control unit, 21_1 to 21_N, 25_1 to 25_N comparator, 24_1 to 24_N adder, 22_1 to 22_N, 26_1 to 26_N AND circuit, 61, 62 shifter, 70, 90 selector, 23, 27, 28 OR circuit, 211 minutes Previous instruction address memory.

Claims (9)

A main memory having a bit width of N bits;
A cache memory having a cache line of L (N × X: X is a natural number of 2 or more) bit width;
When registering an M-bit (2 × M ≦ L) instruction stored in the main memory in the cache memory, N-bit read unit data including the head of the instruction and subsequent (X−1) ) pieces of Bei example a cache control unit for registering a reading unit data of N bits into a single cache line,
When the position of the instruction in each read unit data of the main memory is designated by s bits,
The cache control unit includes N-bit read unit data specified by a first address in which the lower s bits of an address specifying the instruction are set to 0, and the next (X-1) N bits The read unit data is registered in the cache line . The cache control unit, the registers in the cache memory the portion excluding the lower s bits of the first address as a tag address for specifying the cache line, the semiconductor device according to claim 1, wherein. The semiconductor device according to claim 2 , wherein the instruction is a branch destination instruction specified by a branch instruction. When the cache control unit jumps to the address of the branch destination instruction specified by the branch instruction, the cache control unit corresponds to the tag address when the portion except the lower s bit of the address matches the tag address. The semiconductor device according to claim 3 , wherein data of a cache line to be read is read. The semiconductor device according to claim 3 , wherein X = 2. When the cache control unit jumps to the address of the branch destination instruction specified by the branch instruction, if the portion excluding the lower s bits of the address matches the next address of the tag address, 4. The semiconductor device according to claim 3 , wherein data of a cache line corresponding to the address is read. The semiconductor device according to claim 5 , wherein the cache control unit outputs N-bit data corresponding to a next address among the read cache line data to the CPU core.   The semiconductor device according to claim 1, wherein the main memory stores a variable length instruction.   The semiconductor device according to claim 1, wherein the cache control unit registers data indicating whether or not each read unit data registered in the cache line is valid in the cache memory.

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