JP5206385B2 - Boundary execution control system, boundary execution control method, and boundary execution control program - Google Patents

Description

  The present invention relates to a boundary execution control system, a boundary execution control method, and a boundary execution control program. The boundary execution speedup of boundary generation and execution of subsequent scalar load instructions during execution of a vector store instruction and a reduction in the amount of hardware. The present invention relates to an execution control system, a boundary execution control method, and a boundary execution control program.

  As a technique related to vector processing, a boundary execution control system including a scalar processor, a vector processor, an L2 cache, and a memory is known.

  In this system, the scalar processor includes a snoop processing circuit and an L1 cache, and after the scalar processor executes a vector store instruction (hereinafter referred to as VST), a subsequent scalar load instruction (hereinafter referred to as LDS) for the L1 cache. Must be issued after guaranteeing that the data to be loaded is the latest.

  Therefore, the scalar processor waits for the completion of the snoop of the cache by the snoop processing circuit, and confirms that the data to be loaded is not updated by the VST. As a result, a SIMD computer (Single Instruction / Multiple Data computer) including a vector computer stores a large amount of data at one time, so that it takes time to complete the snoop and the subsequent LDS issuance is delayed.

  FIG. 11 shows an example of a snoop processing circuit. The snoop processing circuit includes an address calculator 81, a snoop address register 82, a tag copy storage 83 that stores a copy of the tag of the L1 cache, and a comparator 84. The snoop address generated by the address calculator 81 is stored in the register 82, a copy of the tag in the storage 83 designated by the lower bit is read, and the read tag and the upper bit of the snoop address are Comparison is performed by the comparator 84. If they match as a result of the comparison, the entry in the L1 cache is assumed to be updated by the VST, and the entry is invalidated (flushed). In the example shown in FIG. 11, since a plurality of copy storage units 83 that can operate independently and simultaneously are provided, this snoop process can be performed on a plurality of addresses simultaneously.

  However, as described above, the VST stores a large amount of data at one time, so that it takes time to complete the snoop, and the subsequent LDS issuance is delayed.

  Therefore, a boundary check method is known as a method in which hardware guarantees that data to be loaded has not been updated by VST and a subsequent LDS is issued without waiting for completion of snoop.

  FIG. 12 shows an example of a boundary-type boundary execution control system 120. In the boundary check method, the scalar processor 121 includes a boundary check circuit 1212 in addition to the snoop processing circuit 1211 and the L1 cache 1213. The boundary check circuit 1212 includes a boundary generation unit 1216, an LDS issue control unit 1214, and an address storage unit 1215. When the VST is executed, the boundary generation unit 1216 stores the minimum and maximum addresses to be updated in the address storage unit 1215 as the boundary. Then, the LDS issue control unit 1214 can determine that the LDS that accesses the outside of the stored boundary range can be executed without waiting for the completion of the snoop.

  As a related technique, Patent Document 1 discloses a technique for performing boundary control on a plurality of vector store instructions with a minimum amount of hardware.

  FIG. 15 shows a boundary execution control device 15 of Patent Document 1.

  First, the boundary control unit 156 calculates the end address of the currently executing vector store request. Next, the boundary control unit 156 registers the start point and end point addresses of the boundary section of the vector store request, and compares the start address of the subsequent vector store request with the registered start point address. Then, the registered address is changed, the address of the subsequent scalar load request is compared with the address of the start and end points of the registered boundary section, and the output destination of the subsequent scalar load request is instructed to the memory request control unit As a result, the scalar load request is output to either the cache memory or the main storage unit 154 so that the scalar load instruction can be executed during execution of a plurality of vector store instructions.

  Furthermore, as a related technique, Patent Document 2 discloses an address decoder having a small circuit scale and an expandable address area.

JP2001-195389 JP 7-44455 A

  However, in the boundary check as described above, it is necessary to compare the boundary and the LDS address at least twice, which is disadvantageous in terms of both delay time and circuit scale, and hinders the design of a small and fast processor. It becomes. Further details will be described below.

  FIG. 13 shows an example of the boundary check circuit 1212.

  The boundary generation unit 1216 includes an address calculator 131 that calculates B + ((VL−1) × D). The boundary generation unit 1216 registers a table 132 indicating addresses in the address storage unit 1215. The LDS issue control unit 1214 includes a comparator 133. Based on the comparison result, it is determined whether or not to permit the issuance of LDS.

B represents a base address, D represents a distance, and VL represents a vector length, and data of addresses B, B + D, B + 2D,..., B + ((VL−1) × D) is updated by VST. And In this case, the minimum value of the address to be updated is B (B + ((VL−1) × D) when D is negative), and the maximum value is B + ((VL−1) × D) (when D is negative). B). The boundary generation unit 1216 calculates B + ((VL−1) × D), and registers the calculation result as a boundary with B in the address storage unit 1215. The address storage unit 1215 is provided with entries for storing a plurality of boundaries in preparation for a case where there are a plurality of VSTs in the middle of snooping. When a subsequent LDS is issued, the LDS issue control unit 1214 determines whether an address designated by the LDS (hereinafter referred to as Addr_lds) is within the boundary range. LDS is B ≦ Addr_lds ≦ B + ((VL−1) × D) (Formula 1)
If the above condition is satisfied, the data at the address Addr_lds may be updated by the preceding VST, so that the completion of the snoop is awaited. Conversely, if (Equation 1) is not satisfied, data is not updated by VST, and LDS can be issued without waiting for completion of snoop.

  The hardware newly required for providing the boundary check circuit 1212 in the scalar processor 121 mainly includes an address calculator 131 for calculating B + ((VL−1) × D) in the boundary generation unit 1216, and an address storage unit. 1215 is the storage capacity of 2 boundary addresses × (number of entries in the address storage unit), and the LDS issue control unit 1214 is 2 × (number of entries in the address storage unit) for comparing 133 with the boundary and Addr_lds. is there.

  FIG. 14 shows the configuration of the comparator. In the case of an N-bit comparator, a logical operation of about 2 logN + 2 stages is required. Considering the case of 32 bits, the comparator requires about 12 stages of logical operations. Further, the LDS issue control unit 1214 has an AND circuit that receives the results of the two comparators and an address storage unit 1215. Therefore, the LDS issue control unit 1214 requires about 15 stages of logical operations.

  Thus, in realizing the high-performance and small-scale processor, the above-described boundary check method has problems in both delay time and hardware amount.

  In the technique described in Patent Document 1, it is necessary to compare the boundary and the LDS address at least twice, which causes problems in both delay time and circuit scale.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, speed up boundary generation during execution of a vector store instruction and issue control of a subsequent scalar load instruction, and reduce the amount of hardware. An object of the present invention is to provide an execution control method and a boundary execution control program.

  A first boundary execution control system according to the present invention includes a cache, a snoop processing circuit that performs a snoop process on the cache, and an address to be updated when a vector store instruction that is an instruction for storing a plurality of data in parallel is executed. At least one of the minimum and maximum values is stored as a boundary, a mask is generated from the result of the exclusive OR operation between the minimum and maximum values, and when a scalar load instruction is issued to the cache, the boundary is And a boundary check circuit that determines whether or not to issue a scalar load instruction without waiting for the completion of the snoop process based on the mask.

  The second boundary execution control system according to the present invention includes an address to be updated when a cache, a snoop processing circuit that performs a snoop process on the cache, and a vector store instruction that is an instruction for storing a plurality of data in parallel are executed. At least one of the minimum value and the maximum value is stored as a boundary, and the number of bits from which the minimum value and the maximum value coincide with the most significant bit is detected, and the detection result and the boundary are detected. And a boundary check circuit that determines whether or not to issue a scalar load instruction without waiting for the completion of the snoop process.

  A boundary control method according to the present invention is a boundary execution control method in a boundary execution control system including a cache, a boundary check circuit, and a snoop processing circuit, wherein the boundary check circuit is a command for storing a plurality of data in parallel. At the time of execution of the store instruction, at least one of the minimum value and the maximum value of the address to be updated is stored as a boundary in the address storage unit, and a mask is generated from the result of the exclusive OR operation between the minimum value and the maximum value. A boundary generation step, a snoop processing step in which a snoop processing circuit performs a snoop process on the cache, and a boundary check circuit that snoops based on the boundary and mask of the address storage unit when issuing a scalar load instruction to the cache. And boundary checking step determines whether or not to permit the issuance of scalar load instruction without waiting for the physical completion, characterized in that it comprises a.

  A boundary control program according to the present invention stores at least one of a minimum value and a maximum value of an address to be updated when a boundary check circuit executes a vector store instruction that is an instruction for storing a plurality of data in parallel. A boundary generation step for storing a mask in the address storage unit and generating a mask from the result of an exclusive OR operation between the minimum value and the maximum value, and a snoop processing step in which the snoop processing circuit performs a snoop process on the cache. The boundary check circuit determines whether or not to allow the issuance of the scalar load instruction without waiting for the completion of the snoop process, based on the boundary and mask of the address storage unit when the issuance of the scalar load instruction to the cache is requested. Boundary check step and And wherein the Rukoto.

  The present invention has an effect that the boundary generation and the issue control of the subsequent scalar load instruction at the time of executing the vector store instruction can be accelerated and the amount of hardware can be reduced.

  Next, the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a first embodiment of the boundary execution control system of the present invention.

  Referring to FIG. 1, the boundary execution control system 1 according to the present embodiment includes a scalar processor 11, a vector (SIDM) processor 12, an L2 cache 13, and a memory 14. The L1 cache 113 is used by the scalar processor 11, and the L2 cache 13 is used by the scalar processor 11 and the vector processor 12.

  The scalar processor 11 also includes a snoop processing circuit 111 and a boundary check circuit 112 that perform a snoop process. The boundary check circuit 112 includes a boundary generation unit 1121, an address storage unit 1122, and an LDS issue control unit 1123. The boundary generation unit 1121 includes a mask generation circuit 1124. The boundary execution control system 1 according to the present embodiment is different from the system of FIG. 12 in that the boundary generation unit 1121 includes a mask generation circuit 1124.

  FIG. 2 shows a detailed circuit diagram of the boundary check circuit 112 in the present embodiment.

  In FIG. 2, the boundary generation unit 1121 includes an address calculator 21 and a mask generation circuit 22 that calculate B + ((VL−1) × D). The boundary generation unit 1121 registers the table 23 including the base address B and the mask value in the address storage unit 1122. The LDS issue control unit 1123 includes a comparator 24. Based on the comparison result in the comparator 24, it is determined whether or not to permit the issuance of LDS.

  In the present embodiment, when the scalar processor 11 issues a VST, the vector processor 12 executes the VST, and the scalar processor 11 performs boundary generation and performs LDS issue control.

  In the present embodiment, by using a mask during the LDS issue control of the scalar processor 11, it is possible to reduce the delay time and the amount of hardware as described below.

  First, a mask generation method will be described. In the following description, B, D, and VL represent a base address, a distance, and a vector length, respectively.

  In the boundary generation unit 1121, the value of B + ((VL−1) × D) is calculated by the computing unit 21, and then the exclusive OR of the calculation result and B is taken. A mask value is generated in which the portion that is continuously 0 from the most significant bit is 1 and the other portions are 0. The boundary generation unit 1121 registers B and the generated mask value in association with each other in the address storage unit 1122.

  The LDS issuance control unit 1123 compares the B bit portion corresponding to the bit portion having a generated mask value of 1 and the bit portion of Addr_lds (address designated by LDS). If they match, the address data loaded by the LDS may be updated by the VST, so the LDS is not issued until the snoop is completed. In the case of a mismatch, there is no possibility that the address data loaded by the LDS has been updated by the VST, so that the LDS can be issued.

  FIG. 3A shows an example of mask generation. Here, B is “110010010010”, and B + ((VL−1) × D) is “110011000100”.

  First, the exclusive OR of these two addresses is taken, the result value is “000001010110”, and the value of the 5-bit part from the most significant is 0 continuously, so the mask value is “111110000000” Become. In this case, the LDS issue control unit 1123 compares the upper 5 bits of B with the upper 5 bits of Addr_lds. If the comparison results in a match, the LDS issue control unit 1123 issues an LDS after waiting for the snoop result, and if not, the LDS issue control unit 1123 determines that the LDS can be issued without waiting for the snoop result.

  In the following, the validity of issue control by means of coincidence comparison between B and Addr_lds using such a mask value will be described.

A value in which all the bit portions truncated using the mask value are “0” is set as BL, and a value in which all the bit portions truncated using the mask value are “1” is set as BH. In the example of FIG. 3A, BL is “110010000000” and BH is “110011111111” (see FIG. 3B). Since the bit portion of the mask value “1” indicates that the corresponding bit portion of B and B + ((VL−1) × D matches,
BL ≦ B, B + ((VL−1) × D) ≦ BH (Formula 2)
This holds true even when D is negative.

In addition, when B and Addr_lds match for the bit part set to “1” in the mask value,
BL ≦ Addr_lds ≦ BH (Formula 3)
Is established. If (Equation 3) is not satisfied, that is, if B and Addr_lds do not match for the bit portion with the mask value “1”, it can be said that (Equation 1) is not satisfied.

  In the example of FIGS. 3A and 3B, BL is “110010000000” and BH is “110011111111”. For example, consider a case where Addr_ld is “11001xxxxxxx” (Addr_lds0) and “11011xxxxxxx” (Addr_lds1). . Since the upper 5 bits of the mask value are “1”, the LDS issue control unit 1123 determines whether the upper 5 bits of Addr_lds0 and Addr_lds1 match the upper 5 bits of B “110010010010”. judge. Since Addr_lds0 matches, it is determined that it is necessary to wait for snoop completion, and Addr_lds1 does not match, so it is determined that LDS can be issued.

  FIG. 4 shows a flowchart for boundary generation and LDS issue control.

  When the VST is issued by the scalar processor 11 (S400), the vector processor 12 executes the VST, whereby data in a vector register (not shown) is stored in the L2 cache 12 (S401). Simultaneously with S401, the scalar processor 11 starts a snoop process (S402), and a boundary and a mask are generated (S403). In the snoop process of S402, the addresses (B, B + D, B + 2D,..., B + (VL-1) * D)) are calculated, and the same address as the calculated address is stored in the L1 cache 113. If so, the entry is invalidated.

  Next, when the boundary and the mask are generated in S403, the boundary generation unit 1121 registers the base address B and the mask value in the address storage unit 1122 (S404).

  Next, when the scalar processor 11 makes an LDS issue request (S405), the LDS issue control unit 1123 of the scalar processor 11 uses the address designated by the LDS, the base address B read from the address storage unit 1122, and the mask value. Whether or not LDS issuance is determined (S406, S407).

  If the determination result is “issue permission”, the LDS is issued as it is based on the LDS issue request (S407, S408), and loading from the L1 cache 113 is started (S409). On the other hand, if the determination result is “issue not permitted”, the L1 cache may be invalidated by the preceding VST, so the LDS is issued after waiting for the completion of the snoop (S407, S410, S411). . Thereafter, loading is started from the L1 cache 113 (S412).

  In the boundary check method of FIG. 12, the LDS issue control unit requires 2 × (number of entries in the address storage unit) comparators. However, in the boundary check method according to the present embodiment, the LDS issue control unit includes ( The number of entries in the address storage unit) is only required, and as a result, the amount of hardware required for the configuration of the LDS issue control unit can be reduced.

  Further, the LDS issue control unit 1123 in the present embodiment can be configured with about 10 stages of logical operations.

  Thus, in this embodiment, both the delay time and the hardware amount can be reduced as compared with the boundary check method of FIG.

  Note that the address storage unit 1122 is realized using, for example, Ternary CAM (TCAM). The TCAM is obtained by adding an area for storing a mask value to a normal CAM (associative memory) that searches data with a key and accesses data. When reading the TCAM, the key is masked with a mask value for access. However, in this embodiment, there is no area for storing data, and only a hit or a miss hit is output. Note that the method of realizing the address storage unit 1122 is not limited to this.

  In this embodiment, VST and LDS are issued from the scalar processor 11, the vector processor 12 executes VST, and the scalar processor 11 performs LDS issue control. However, the present invention is not limited to this.

  Next, a second embodiment of the present invention will be described.

  In the first embodiment, when the timing at which the vector length VL is determined is later than the timing at which the base address B and the distance D are determined, boundary generation and mask generation cannot be performed until the vector length VL is determined. Delay occurs. Therefore, the second embodiment aims to further reduce the delay time even when the timing at which the vector length VL is determined is later than that of the base address B and the distance D.

  FIG. 5 shows a configuration of a boundary check circuit according to the second embodiment.

  In the second embodiment, in addition to the configuration of the boundary check circuit of the first embodiment, an encoder 51 and a selector 52 are provided. Thereby, before the vector length VL is determined, a plurality of mask candidates are created using only the base address B and the distance D, and when the vector length VL is determined, the plurality of created candidates are determined based on the value of the vector length VL. One of the masks is selected. As a result, in the second embodiment, compared to the circuit diagram (FIG. 2) in the first embodiment, it is necessary to add hardware for preparing a plurality of arithmetic units, but the vector length VL is found. Then, the process from the generation of the mask to the generation of the mask can be accelerated.

  Specifically, in the second embodiment, the address calculator 21a performs an address calculation with a vector length VL of 4D. The address calculator 21b performs an address calculation with a vector length VL of 16D. The address calculator 21c performs an address calculation with a vector length VL of 64D. The address calculator 21d performs an address calculation with a vector length of 256D.

  The encoder 51 has a table (not shown) indicating the correspondence between the vector length VL and the address calculator. Since the boundary when the vector length VL is 1 to 3D is included in the boundary when the vector length VL is 4D, in the above table, the vector length VL is 1 to 4D and the address calculator 21a is associated. Further, since the boundary when the vector length VL is 5 to 15D is included in the boundary when the vector length VL is 16D, in the above table, the vector length VL is 5 to 16D and the address calculator 21b is associated. Further, since the boundary when the vector length VL is 17 to 63D is included in the boundary when the vector length VL is 64D, in the above table, the vector length VL is 17 to 64D and the address calculator 21c is associated. Further, since the boundary when the vector length VL is 65 to 255D is included in the boundary when the vector length VL is 256D, in the above table, the vector length VL is 65 to 256D and the address calculator 21d is associated.

  When reading the vector length VL, the encoder 51 generates a select signal indicating which mask is to be selected based on the table. Next, the selector 52 selects one of a plurality of masks generated in advance using the select signal. For example, when the vector length VL read by the encoder is 2D, the encoder 51 generates a select signal indicating that the mask generated from the address calculator 21a is selected based on the table.

  The encoder 51 can be composed of a logic operation circuit having about 8 stages of gates, and the selector 52 can be composed of a logic operation circuit having about 4 stages of gates when one is selected from four masks.

  In the second embodiment, by generating mask value candidates before the vector length VL is determined, the boundary generation can be accelerated.

  Next, a third embodiment of the present invention will be described.

  In the third embodiment, the mask value is compressed in order to reduce the capacity of the address storage unit 1122.

  FIG. 6 shows an example in which a 12-bit mask value is divided into 4-bit units and each 4 bits are compressed into 1 bit. In this example, the least significant bits of the 4 bits to be compressed are collectively registered in the address storage unit 1122 as a 3-bit mask value. At the time of mounting, only the bits that are registered when the mask value is generated may be generated. As a result, in the third embodiment, the storage capacity for the mask value in the address storage unit can be reduced to about a quarter.

  The LDS issue control unit 1123 reads out the compressed mask value from the address storage unit 1122, expands each bit of the mask value to 4 bits of the same value, and uses it as a mask after decompression. In the example of FIG. 6, the mask after decompression is “111100000000”. Comparing the uncompressed mask value “111110000000” with the decompressed mask value “111100000000”, the decompressed mask has the fifth bit from “1” to “0” from the top. As a result, the accuracy of selecting an LDS that can be issued is lowered, but the capacity of the address storage unit can be reduced. In the third embodiment, the case of compressing 4 bits to 1 bit has been described. However, when higher accuracy is required, the overall compression rate can be reduced (from 2 bits to 1 bit) ), The compression rate may be lowered only at the upper level.

  The compression rate can be arbitrarily selected by the designer depending on the required accuracy and circuit scale.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 7 shows “addresses updated by VST” and “range in which it is determined that LDS overtaking is impossible” in the first and second embodiments. In the first and second embodiments, there is a problem that there are many areas that are determined as “impossible to overtake LDS” even though they are not “addresses updated by VST”. In the fourth embodiment, by using two types of masks, it is possible to reduce an area that is determined as “impossible to overtake LDS” even though it is not an “address updated by VST”, and to improve determination accuracy. With the goal.

  When the distance D is a power of 2, the boundary check can be performed not only with comparison with the upper bits of the address but also with comparison with the lower bits of the address. The addresses that are actually updated by the VST are updated at equal intervals of the distance D. In particular, when the value of D is a power of 2 (a power of 2, 4, 8, 16,... 2 to the nth power), the lower bits of the address to be updated are always constant.

  For example, when the distance D of the VST is “10” (binary and decimal 2) and the base address B is an even number (binary and the least significant bit is “0”), the address that may be updated Are only even addresses. Therefore, if the address of the subsequent LDS is an odd number (the least significant bit is “1”), the LDS can be overtaken and executed. Conversely, if the base address B is an odd number (the least significant bit is “1”), it can be executed if the LDS address is an even number (the least significant bit is “0”). That is, if the least significant bit of the base address B does not match the LDS address, LDS can be executed. Similarly, when D is “100” (4 in decimal), the least significant 2 bits are compared, and if they do not match, LDS can be executed.

  The lower number of bits of the address to be updated is determined by D. If the lower bit of D is “10”, it is 1 bit, “100” is 2 bits, and “1000” is 3 bits.

  FIG. 8 shows an example in which B is “110010010010” and D is “000000010000”. Since the lower bits of D are “10000”, the lower 4 bits of B, B + D, B + 2D, and B + 3D should match. When actually calculated, B is “110010010010”, B + D is “110010100010”, B + 2D is “110010110010”, B + 3D is “110011000010”, and the lower 4 bits match.

  The boundary execution control system according to the fourth embodiment is different from the first to third embodiments only in the configuration of the boundary generation unit.

  FIG. 9 shows a boundary generation unit 91 and an address storage unit 92 in the fourth embodiment.

  The boundary generation unit 91 includes an address calculator 911 and a mask generation circuit 912. The mask generation circuit 912 generates a first mask from B and B + ((VL−1) × D) and generates a second mask from the distance D as in the first embodiment. The second mask is such that all bit portions corresponding to bit portions that are continuously zero from the least significant bit at distance D are all “1”, and all other corresponding bit portions are “0”. Generated. Next, the mask generation circuit 912 generates an exclusive OR of the first mask and the second mask and registers it in the address storage unit 92. The LDS issue control unit 1123 compares only the bits that are “1” in the exclusive OR of the first mask and the second mask. Since other processes are the same as those in the first embodiment, detailed description thereof is omitted.

  FIG. 10 shows “address updated by VST” and “range determined to be overtaken by LDS” in the fourth embodiment. In the fourth embodiment, as shown in FIG. 10, by using two types of masks, an area that is determined as “LDS overtaking impossible” despite being not “address updated by VST” is reduced. The determination accuracy can be improved.

  A combination of the fourth embodiment and the second embodiment, a combination of the fourth embodiment and the third embodiment, and the like are also possible.

  In the combination of the fourth embodiment and the third embodiment (the above example in which a 12-bit mask value is divided into 4-bit units and each 4 bits is compressed to 1 bit), the second mask is Of the 4 bits to be compressed, the most significant bit, not the least significant bit, may be registered in the address storage unit 1122 as a 3-bit mask value. About others, it is the same as that of 4th Embodiment and 3rd Embodiment.

It is a block diagram which shows the boundary execution control system in the 1st Embodiment of this invention. 2 is a detailed circuit diagram of a boundary check circuit 112. FIG. It is a figure which shows an example of mask generation. It is a figure which shows the flowchart about boundary generation and LDS issue control. It is a figure which shows the structure of the boundary check circuit in the 2nd Embodiment of this invention. It is a figure which shows the example which compresses a mask value. It is a figure which shows the "address updated by VST" in the 1st and 2nd embodiment of this invention, and the "range determined as LDS overtaking impossible." It is a figure which shows the address updated when B is "110010010010" and D is "000000010000". It is a figure which shows the boundary production | generation part 91 and the address memory | storage part 92 in the 4th Embodiment of this invention. It is a figure which shows "the address updated by VST" in the 4th Embodiment of this invention, and the "range judged as LDS overtaking impossible." It is a figure which shows the example of the snoop processing circuit in related technology. It is a figure which shows an example of the boundary type | mold boundary execution control system 120 in related technology. It is a figure which shows an example of the boundary check circuit 1212 in related technology. It is a figure which shows the structure of a comparator. It is a figure which shows the boundary execution control apparatus 15 of patent document 1. FIG.

Explanation of symbols

1 Boundary execution control system 11 Scalar processor 111 Snoop processing circuit 112 Boundary check circuit 1121 Boundary generation unit 1122 Address storage unit 1123 Scalar load instruction issue control unit (LDS issue control unit)
1124 Mask generation circuit 113 L1 cache 12 Vector processor 13 L2 cache 14 Memory 21 Address calculator 22 Mask generation circuit 23 Table 24 Comparator 51 Encoder 52 Selector 91 Boundary generation unit 911 Address calculation unit 912 Mask generation circuit 92 Address storage unit 120 Boundary Execution control system 121 Scalar processor 1211 Snoop processing circuit 1212 Boundary check circuit 1213 Boundary generation unit 1214 LDS issue control unit 1215 Address storage unit 1216 Boundary generation unit 122 Vector processor 123 L2 cache 124 Memory 13 Boundary check circuit 131 Boundary generation unit 132 Table 133 Comparator

Claims (28)

Cache,
A snoop processing circuit for performing a snoop process on the cache;
When executing a vector store instruction that is an instruction for storing a plurality of data in parallel, at least one of the minimum and maximum addresses to be updated is stored as a boundary, and the minimum value and the maximum value are exclusive. A mask in which all the bit parts that are consecutively 0 from the most significant bit in the result of the logical OR operation are set to 1 and the other bit parts are set to 0,
When issuing a scalar load instruction to the cache, a bit part of the minimum value or maximum value of the boundary corresponding to a bit part which is 1 in the mask and a bit part of an address designated by the scalar load instruction A boundary check circuit that compares and determines whether or not to issue the scalar load instruction without waiting for the completion of the snoop process based on the comparison result;
A boundary execution control system comprising: The boundary execution control system according to claim 1, wherein the boundary generation unit generates the boundary and the mask based on information including a base address, a distance, and a vector length constituting a vector. The boundary generation unit generates a plurality of mask candidates based on the information including the base address and the distance, and when the information indicating the vector length is found, includes the base address, the distance, and the vector length. 3. The boundary execution control system according to claim 2, wherein a mask is selected from the candidates based on information. The boundary generation unit compresses the generated mask and stores it in the address storage unit,
4. The boundary execution control system according to claim 1, wherein the scalar load instruction issue control unit performs the determination by decompressing the compressed mask. 5. 5. The boundary execution control system according to claim 4, wherein the boundary generation unit lowers the compression rate only for a predetermined high-order bit of the generated mask. The boundary generation unit generates another mask based on the information indicating the distance when the information indicating the distance is a power of 2 among the base address, the distance, and the vector length constituting the vector,
The scalar load instruction issuance control unit determines whether to permit the issuance of the scalar load instruction without waiting for the completion of the snoop process, based on the boundary, the mask, and the other mask. 6. A boundary execution control system according to claim 2, wherein The boundary generation unit generates the other mask in which the bit portion that is continuously 0 from the least significant in the information indicating the distance is set to 1, and the other bit portions are set to 0, and the other mask is generated. And the mask and the exclusive OR
The scalar load instruction control unit compares the minimum or maximum value of the boundary with the address of the scalar load instruction only for the bit portion that is 1 in the exclusive OR operation result, and the comparison 7. The boundary execution control system according to claim 6, wherein whether to issue the scalar load instruction is permitted without waiting for completion of the snoop process based on a result. The boundary generation unit compresses the generated other mask and stores it in the address storage unit,
8. The boundary execution control system according to claim 6, wherein the scalar load instruction issue control unit performs the determination by decompressing the compressed other mask. 9. The boundary execution control system according to claim 8, wherein the boundary generation unit lowers the compression rate only for a predetermined lower bit among the generated other masks. In a boundary execution control method in a boundary execution control system including a cache, a boundary check circuit, and a snoop processing circuit,
When the boundary check circuit executes a vector store instruction which is an instruction for storing a plurality of data in parallel, at least one of the minimum value and the maximum value of the address to be updated is stored as a boundary in the address storage unit, The bit portion that is continuously 0 from the most significant bit in the result of the exclusive OR operation of the minimum value and the maximum value is set to 1,
A boundary generation step for generating a mask in which the other bit portions are set to 0;
A snoop processing step in which the snoop processing circuit performs snoop processing on the cache; and
When the boundary check circuit issues a scalar load instruction issuance request to the cache, only the minimum or maximum value of the boundary and the address specified by the scalar load instruction of the bit part which is 1 in the mask. A boundary check step for comparing the bit part and determining whether to allow the issue of the scalar load instruction without waiting for the completion of the snoop process based on the comparison result;
A boundary execution control method comprising: The boundary execution control method according to claim 10, wherein, in the boundary generation step, the boundary and the mask are generated based on information including a base address, a distance, and a vector length constituting a vector. In the boundary generation step, a plurality of mask candidates are generated based on information including the base address and the distance, and when the information including the vector length is found, the base address, the distance, and the vector length are determined. 12. The boundary execution control method according to claim 11, wherein a mask is selected from the candidates based on information included. In the boundary generation step,
13. The boundary execution control method according to claim 10, wherein the generated mask is compressed and stored, and the compressed mask is decompressed at the time of the determination. In the boundary generation step,
14. The boundary execution control method according to claim 13, wherein the compression rate is lowered only for a predetermined upper bit of the generated mask. In the boundary generation step,
Information indicating the distance among the base address, distance, and vector length constituting the vector is 2
Generating another mask based on the information indicating the distance when it is a power of
In the boundary check step, it is determined whether or not to issue the scalar load instruction without waiting for the completion of the snoop process based on the boundary, the mask, and the other mask. The boundary execution control method according to claim 11. In the boundary generation step,
In the information indicating the distance, the bit portion that is continuously 0 from the lowest is set to 1,
After generating the other mask with the other bit parts set to 0, an exclusive OR of the other mask and the mask is generated,
In the boundary check step,
Only for the bit portion that is 1 in the exclusive OR operation result, the minimum value or maximum value of the boundary is compared with the bit portion of the address specified by the scalar load instruction, and based on the comparison result 16. The boundary execution control method according to claim 15, wherein it is determined whether or not to issue the scalar load instruction without waiting for the completion of the snoop process. In the boundary generation step,
17. The boundary execution control method according to claim 15, wherein the generated other mask is compressed and stored in the address storage unit, and the compressed other mask is decompressed at the time of the determination. 18. The boundary execution control method according to claim 17, wherein, in the boundary generation step, the compression rate is lowered only for a predetermined lower bit among the other generated masks. On the computer,
The boundary check circuit stores at least one of a minimum value and a maximum value of an address to be updated as a boundary in an address storage unit when executing a vector store instruction that is an instruction for storing a plurality of data in parallel. All the bit parts that are continuously 0 from the most significant bit in the result of the exclusive OR operation of the minimum value and the maximum value are set to 1,
A boundary generation step for generating a mask in which the other bit portions are set to 0;
A snoop processing step in which the snoop processing circuit performs snoop processing on the cache; and
The boundary check circuit designates the minimum or maximum bit portion of the boundary corresponding to the bit portion that is 1 in the mask and the scalar load instruction when the scalar load instruction is issued to the cache. A boundary check step for comparing the bit part of the address and determining whether to allow the issue of the scalar load instruction without waiting for the completion of the snoop process based on the comparison result;
Boundary execution control program characterized in that 20. The boundary execution control program according to claim 19, wherein, in the boundary generation step, the boundary and the mask are generated based on information including a base address, a distance, and a vector length constituting a vector. In the boundary generation step, a plurality of mask candidates are generated based on information including the base address and the distance, and when the information including the vector length is found, the base address, the distance, and the vector length are determined. 21. The boundary execution control program according to claim 20, wherein a mask is selected from the candidates based on information included therein. In the boundary generation step,
The boundary execution control program according to any one of claims 19 to 21, wherein the generated mask is compressed and stored, and the compressed mask is decompressed at the time of the determination. In the boundary generation step,
23. The boundary execution control program according to claim 22, wherein the compression rate is reduced only for a predetermined higher-order bit in the generated mask. In the boundary generation step,
Information indicating the distance among the base address, distance, and vector length constituting the vector is 2
Generating another mask based on the information indicating the distance when it is a power of
In the boundary check step,
24. The method according to any one of claims 20 to 23, wherein whether or not to issue the scalar load instruction is permitted without waiting for completion of the snoop process based on the boundary, the mask, and the other mask. The boundary execution control program according to any one of the above. In the boundary generation step,
In the information indicating the distance, the bit portion that is continuously 0 from the lowest is set to 1,
After generating the other mask with the other bit parts set to 0, generate the exclusive OR of the other mask and the mask,
In the boundary check step,
Only for the bit portion that is 1 in the exclusive OR operation result, the minimum value or maximum value of the boundary is compared with the bit portion of the address specified by the scalar load instruction, and based on the comparison result 25. A boundary execution control program according to claim 24, wherein it is determined whether or not to issue the scalar load instruction without waiting for completion of the snoop process. In the boundary generation step,
26. The boundary execution control program according to claim 24, wherein the generated other mask is compressed and stored in the address storage unit, and the compressed other mask is decompressed at the time of the determination. 27. The boundary execution control program according to claim 26, wherein, in the boundary generation step, the compression rate is lowered only for a predetermined lower bit of the generated other masks. Cache,
A snoop processing circuit for performing a snoop process on the cache;
When executing a vector store instruction that is an instruction for storing a plurality of data in parallel, at least one of the minimum value and the maximum value of the address to be updated is stored as a boundary,
Generating a mask in which all bit portions that are continuously 0 from the most significant bit as a result of an exclusive OR operation of the minimum value and the maximum value are set to 1 and the other bit portions are set to 0; The bit portion of the boundary corresponding to the bit portion that is 1 in the mask is compared with the bit portion of the address specified by the scalar load instruction, and based on the comparison result,
A boundary check circuit that determines whether or not to allow the scalar load instruction to be issued without waiting for the completion of the snoop process;
A boundary execution control system comprising:

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