JP2954178B1 - Variable cache method - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a cache memory so that an optimum cache configuration can be obtained according to the characteristics of a program. The number of entries in a basic block (A) is B (B
.Gtoreq.2), a cache memory 10 having a basic configuration having C (C.gtoreq.2) levels, and a cache configuration indication field for storing information indicating that n basic blocks are used as a block unit to be stored in the cache memory 10. 31 and the contents stored in the cache configuration instruction field 31, the configuration of the cache memory 10 is changed such that n basic blocks (A) are in block units and the number of ways at that time is C / n. And a cache configuration changing unit 33 for performing the setting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a cache memory used in an information processing apparatus.

[0002]

2. Description of the Related Art In an information processing apparatus such as a computer system, between a main storage device having a relatively low processing speed and an arithmetic processing device having a relatively high processing speed, the storage capacity is higher than that of the main storage device. Place a small cache memory,
A copy of the information in the main storage device is temporarily stored in the cache memory so as to increase the apparent speed of the main storage device as viewed from the arithmetic processing unit. There are several methods (mapping methods) for associating data in the main memory with data in the cache memory and transferring data blocks from the main memory to the cache memory. Even so, conventionally, the block unit, the number of entries, and the number of levels to be stored in the cache memory are fixedly determined.

However, if the block unit, the number of entries and the number of levels to be stored in the cache memory are fixedly determined, the data registered in the cache in block units cannot be effectively used depending on the nature of the program to be executed. Create problems. For example, in the case of handling a large array as in the case of scientific and technical calculations, the performance is improved when the block unit of the cache memory is large, and the performance is improved when the block unit is small but the number of ways of the cache memory is large. A case arises. Which case depends on the program or algorithm.

FIG. 5 is a block diagram showing a configuration of a conventional cache system. Here, it is assumed that the arithmetic processing unit of the information processing device is a scalar processing device that performs only the processing of the scalar instruction.
It is assumed that the cache memory 50 is interposed. The cache memory 50 includes a tag memory 51 and a data memory 5.
And 2. The data memory 52 stores a copy of data in the main storage device in block units. Also, the tag memory 51 is
2 holds real address information of data stored in each block.

An address register 60 for holding an address generated for accessing data is provided. From this address register 60, an address in a block is output to a data memory 52, and a set address is stored in a tag memory 51. Output to Further, a comparator 61 for comparing the address information read from the tag memory 51 with the real address of the data to be accessed, and a selection circuit for selecting data read from the data memory 52 according to the result of the comparison by the comparator 61 62 are provided.

FIG. 6 is a diagram showing an example of the contents of each of the tag memory 51 and the data memory 52 in the cache system shown in FIG. The tag memory 51 and the data memory 52 each have an entry. The tag memory entry 100 holds address information of data stored in a data memory entry corresponding to the tag memory entry. On the other hand, data memory entry 200
Is composed of a plurality of data. Here, each data memory entry 200 is composed of eight byte data, and one data memory entry is 64 bytes.
Assume the byte configuration. Also, “000” to “1” are assigned to the eight data of the data memory entry 200.
11 "(binary notation) in the block.

Next, a specific operation of the conventional cache system will be described.

[0008] The cache memory 50 from the scalar processing device
When accessing the above data, the address to be accessed is set in the address register 60 and the tag memory 5 is accessed.
1 and the data memory 52 are accessed. In the case of the example described here, the number of entries in the vertical direction of the data memory 52 is eight.
Level, and since each data memory entry has eight 8-byte data, if the address register 60 is an address register having a 32-bit width,
The setting in the tag memory 51 is specified by the 23rd to 25th bits (total 3 bits) of the address, and the address in the block of the data memory 52 is the 26th to 28th bits (total 3 bits) of the address. Is specified by

Here, assuming that the number of levels in the horizontal direction of the tag memory 51 and the data memory 50 is a two-way configuration (way 1 and way 2) as shown in the figure, the tag memory 51 having an address specified is Data memory 52
From the tag memory 5
The comparator 61 compares the address information of two levels read from 1 with the real address. The comparator 61 sends a comparison result indicating which way it matches to the selection circuit 62. The selection circuit 62 outputs the comparator 6 of the 8-byte data of two levels read from the data memory 52.
In accordance with the comparison result from 1, one of the eight levels is selected, and the data is sent to the scalar processing device. If the address information of the two ways read from the tag memory 51 does not match the actual address, the data to be accessed is not registered in the data memory 52. , And for the specified tag memory entry and data memory entry, the data is registered in one way of those entries. 1 from main storage
Transfer 64 bytes of data to one data memory entry. To specify the way to register the data,
For example, an LRU (Leas) in which data is newly stored in a block that has passed the longest time since it was last used.
t Recently Used) method is known.

Now, the operation of the conventional cache system shown in FIG. 5 will be described by taking as an example the case of processing an actual program. Here, it is assumed that a program written in the FORTRAN language shown in FIG. 7 is processed. This program computes X (I) * Y (I) + Z (I) and substitutes it for W (I), where I is 1 to 3
This is sequentially repeated for integers up to 2. Here, X, Y, and Z each indicate an array, and each array has 512
X (1), Y
Assume that (1) and Z (1) are the first address on a 64-byte boundary. W is also an array.

First, when I = 1, the scalar processing device
(1) is loaded from the main storage device, but the cache memory 50 is first accessed. At this time, the address information of X (1) is held in the address register 60, but the array is 5
Since the data is aligned on a 12-byte boundary, the 23rd to 25th bits of the address of the address register 60 at this time are "000". Then, entry 1 of way 1 of tag memory 51 and entry 1 of way 2
0 is read out, and the comparator 61 compares these entries with the real address of X (1). Since the data is not registered in the cache memory 50 at the beginning of the program processing, the address read from the tag memory 51 and the real address do not match (cache miss), and the data is read from the main storage device and read. The 64-byte data (X (1) to X (8) data) is registered in the way 1 entry 00 of the memory 52, the address information is registered in the way 1 entry 00 of the tag memory 51, and the X ( Send the data of 1).

Next, the data of Y (1) is similarly loaded from the main storage device. At this time, the address of Y (1) 2
Since the third to 25th bits are also “000”, the address information and the 64-byte data (Y (Y ()) are stored in the entry 10 of a different way (way 2) in the tag memory 51 and the data memory 52. 1) to Y (8) data)
Is registered. Here, the scalar processing device is X (1) and Y
(1) is multiplied. When this point as the time A, the data memory 5 2, data as shown in FIG. 8 (a) is registered in each entry.

Subsequently, data of Z (1) is loaded. At this time, since the 23rd to 25th bits of the address of Z (1) are also “000”, the addresses of entry 00 of way 1 and entry 10 of way 2 of tag memory 51 are read out and compared. In the unit 61, the actual address of Z (1) is compared. Since the entry 00 stores the address information of X (1) and the entry 10 stores the address information of Y (1), the comparison result of the comparator 61 indicates a mismatch, and as a result, the main storage device 64-byte data including Z (1) is transferred to the data memory 52 and stored in the data memory 52, and Z (1) is sent to the scalar processing device. The data transferred from the main storage device is stored in the entry 00 or the entry 10. Assuming that the storage destination is determined by the LRU method, the 64-byte data including Z (1) is , And the entry 00 in the tag memory 51,
The address information of (1) is stored. The scalar processing device
Z (1) is added to the result of the previous multiplication, and the result is stored in the main storage device. Here, assuming that writing is performed by the store-through method, the store data is not registered in the cache memory, but is stored in W (1) of the area specified in the array W on the main storage device. This point is time B.
In the data memory 51, as shown in FIG.
Data is registered in each entry.

Next, when I is updated and I = 2, X
(2) is loaded, but the address of X (2) is a value obtained by adding 8 bytes to the address of X (1), and the 23rd to 25th bits of the address of X (2) are set to “000”. Has become. Therefore, in the tag memory 51 and the data memory 52, the entry 00 of way 1 and the entry 10 of way 2
Is used. The addresses of the entry 00 and the entry 10 of the tag memory 51 are read out, and the X
The comparison with the real address of (2) is performed. At this point, the address information of Z (1) is stored in the entry 00, and the Y address is stored in the entry 10.
Since the address information of (1) is stored, the comparator 61
Indicates a mismatch. As a result, 64-byte data including X (2) is read from the main storage device, registered in the data memory 52, and X (2) is sent to the scalar processing device. First, when X (1) is stored in the data memory 52, the continuous 64-byte data is stored in the entry 00.
, The data of X (2) is once registered in the data memory 52 at that time. However,
During the subsequent loading of Z (1),
When the data of X (2) is actually required, it has not been registered in the cache memory, and a cache miss occurs. Therefore, when loading X (2), the main storage must be accessed again. 64 containing X (2) read from main storage
The byte data is stored in the entry 10 of the data memory 52, and the entry 10 of the tag memory 51 stores the address information of X (2). This point is time C.
In the data memory 51, as shown in FIG.
Data is registered in each entry.

Subsequently, Y (2) is loaded. Since no data is registered in the cache memory for Y (2) as in X (2), the main memory is accessed. To store the data containing Y (2) in the data memory 52.
, And the address information of Y (2) is stored in way 00 entry 00 of the tag memory 51 .

Thereafter, even when I = 3, 4, 5, 6,..., 32, respectively, cache miss processing is similarly performed.

As described above, according to the conventional technique, when the head addresses of a plurality of arrays all use the same entry address, or when a program that accesses the main storage device in the entry direction (vertical direction) is executed. In addition, the data registered in the cache memory in block units (64 bytes in this example) is rewritten by the subsequent processing, and the data once registered in the cache memory cannot be used effectively.

In order to solve such a problem of the conventional cache memory, Japanese Patent Application Laid-Open No. H5-40694 discloses
A technique is disclosed in which the structure of a cache memory is made variable so that the structure of the cache memory can be selected in accordance with a program. That is, according to the technique described in this publication, a plurality of entries in the entry direction are stored in one entry when accessing continuous data of a block unit or more.
By using one block size, the amount of data registered in the cache memory by one cache miss can be increased, and the number of cache misses can be reduced. However, in the technique described in Japanese Patent Application Laid-Open No. 5-40694, the configuration in the level direction (horizontal direction) cannot be changed. Therefore, in a program in which an array using the same entry address is equal to or more than the number of levels, as described above. There is a drawback in that data once registered in the cache memory is rewritten by subsequent processing, and a cache miss occurs frequently.

[0019]

In general, an unspecified number of application programs are executed in a data processing apparatus, but the access method (pattern) to a main storage device differs depending on the processing characteristics of the application programs. ing. On the other hand, in the conventional cache memory,
The block unit, the number of entries and the number of levels are fixed and cannot be flexibly changed.
Even in Japanese Unexamined Patent Application Publication No. H5-40694, the number of levels is uniquely fixed even if the block unit is variable. As a result, when a cache memory configured to increase the block unit and reduce the number of levels is provided, when a program in which there are a plurality of arrays using the same entry address is executed, Since the data registered in the cache memory is rewritten by the processing, the data registered in the cache memory cannot be effectively used, and cache mishit processing occurs frequently, resulting in a decrease in throughput.
Conversely, when a cache memory is configured to reduce the block unit and increase the number of levels, when accessing a large amount of continuous data on the main storage device, Since the amount of data that can be registered is small, it is necessary to perform registration in the cache memory many times. Since which cache configuration is better depends on the program, the conventional cache system may have an inappropriate cache configuration depending on the characteristics of the program, and may degrade the performance of the cache memory.

An object of the present invention is to provide a variable cache system which can have an optimal cache configuration according to the characteristics of a program and can improve the performance of a cache memory.

[0021]

According to the variable cache method of the present invention, the configuration of a cache memory can be changed according to the nature of a program to be executed. More specifically, variable cache system of the present invention, variable cache scheme odor which is disposed between the processing apparatus for processing loads the data from the main memory and the main memory
Scalar processing device where the processing device processes scalar instructions
And the number of entries in the basic block (A) is B (B is 2
A cache memory capable of storing a copy of data stored in the main storage unit in units of blocks, wherein the basic configuration has C (C is an integer of 2 or more) levels having a set of A cache configuration instruction field for storing information indicating that n basic blocks are used as a block unit to be stored in the cache memory, and n basic blocks (A) are divided into blocks according to the contents stored in the cache configuration instruction field. Unit
As the number of ways that time becomes C / n, and a cache configuration changing means for instructing the cache memory to vary the configuration of the cache memory, a program source
To compile source code and execute it on the processing unit
When generating code, optimal depending on the nature of the program
, The value of n is determined.
It is characterized by that .

According to the present invention, the block configuration of the cache memory is made variable, and the number of levels is made variable in accordance with the block unit, thereby making it possible to obtain an optimum cache configuration according to the characteristics of the program. This improves the performance of the cache memory. In particular, when compiling a program, an optimum cache block unit is recognized according to the program properties such as the array access direction and the number of used arrays, and the cache configuration is determined based on the recognition result as a configuration (block unit × By changing to (the number of entries × the number of levels), data in block units registered in the cache memory can be used effectively, and the cache performance can be improved.

[0023]

Next, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a variable cache system according to an embodiment of the present invention. Here, it is assumed that the cache memory 10 is interposed between the main storage device and the scalar processing device, assuming that the arithmetic processing device of the information processing device is a scalar processing device that performs only scalar instruction processing. The cache memory 10 includes a tag memory 11 and a data memory 12. The data memory 12 stores a copy of data in the main storage device in block units. Also, tag memory 1
1 holds real address information of data stored in each block of the data memory 12. Here, the tag memory 11 and the data memory 12 have a configuration of a basic block A, the number of entries (vertical direction) B, and the number of levels (the number of ways in the horizontal direction) C, respectively.
Output signal 3 from the cache configuration changing means 33 described later
The configuration (values of A, B, and C) can be changed according to 00.

An address register 20 for holding an address generated for accessing data is provided. From this address register 20, an address in the block is output to the data memory 12, and a set address is stored in the tag memory 11. Output to Tag memory 1
And a comparator 21 for comparing the address information read from No. 1 with the real address of the data to be accessed.
And a selection circuit 22 for selecting data to be read from the data memory 12 in accordance with the result of the comparison.

Further, in this variable cache system,
A process status word 30 implemented as a register or the like;
A cache configuration changing unit 33 is provided. The process state word 30 is provided in the system to indicate the process state of the system or to indicate the transition to a specific process state, and is visible from software (ie, software visible,
For example, a value can be entered or a value can be read as a save instruction to a register, a load instruction from a register, and the like. The process state word 30 includes a cache configuration instruction field 31 for determining how many (n) basic blocks (A) are to be used as one block unit in the cache memory 10. The cache configuration changing means 33 responds to an output signal from the cache configuration
The cache 10 is divided into blocks A × n, the number of entries B,
The configuration is such that the number of levels is C / n, and the data registration and data index to the cache 10 are controlled to correspond to this configuration. Here, if a group of the block unit × the number of entries is called a way, the number of levels is the number of ways. FIG. 2 shows the relationship between the basic block (A), the number of entries (B), the number of levels (C), and each way in the tag memory 11 and the data memory 12.

The address register 20 also determines the number of address bits used for designating an address in a block in the data memory 12 and the level position of the tag memory 11 and the data memory 12 according to the output signal 301 from the cache configuration changing means 33. The address bit position used for designation is configured to be changed. In the tag memory 11, the output signal 302 from the cache
, The way read from the tag memory 11 to the comparator 21 is selected.

FIG. 3 shows each entry of the tag memory 11 and the data memory 12 and the cache configuration instruction field 3
3 is a diagram showing the relationship with the contents of FIG.
Indicates that the cache configuration instruction field 33 is "
1 ”,“ 2 ”, and“ 4 ”are shown.
In FIG. 3, reference numerals 401 to 407 denote tag memory entries, and reference numerals 501 to 507 denote data memory entries.

The tag memory entries 401 to 407 hold the address information of the data stored in the data memory entry corresponding to the tag memory entry. Also, data memory entries 501 to 507
Is composed of a plurality of data. Here, it is assumed that the basic size of one data memory entry is a 32-byte configuration composed of four 8-byte data. An address in the block is assigned to the four data of the data memory entry. In this cache system, the number of bits of the address in the block changes according to an output signal 301 from the cache configuration changing unit 33.

The number of entries in the vertical direction of the data memory 12 is eight levels, and the bit width of the address register 20 is 32.
If the cache configuration instruction field 31 specifies that one basic block A is used as a block unit (the cache configuration instruction field 3
1 is "1"), the entry address is specified using three bits of the 24th to 26th bits of the address held in the address register 20, and the specified entry (for example, entry 00) , A block address is stored in the tag memory 11 (tag memory entry 401), and 32 bytes of data (illustrated, data 1 to data 4) in the corresponding data memory entry 501 (for example, Entry 00), and this data is given an address in the block of "00" to "11" in binary. In order to specify an address in a block, two bits of the 27th bit and the 28th bit of the address stored in the address register 20 are used.

When the cache configuration instruction field 31 specifies that two basic blocks A are used as a block unit (the content of the cache configuration instruction field 31 is "2"), the address 23 in the address register 20 is used.
The entry address of the entry in the vertical direction is specified using the three bits from the bit to the 25th bit, and the tag memory 1 corresponding to the specified entry (for example, entry 00)
The block address is stored in 1 (tag memory entry 402), and the tag memory entry 403 (for example, entry 10) adjacent in the way direction is not used. Also, 64 bytes of data (illustrated, data 1 to data 8) from the block address stored in the tag memory entry 402 are stored in the corresponding data memory entry 502 (for example, entry 00) of the data memory 12 and the adjacent data memory. It is stored in the entry 503 (for example, entry 10) and is "000" in binary.
ア ド レ ス “111” in the block. In order to specify an address in a block, the address in the address register 20 must be set in the 3rd bit of the 26th to 28th bits.
Use bits.

When the cache configuration instruction field 31 specifies that four basic blocks A are used as a block unit (the content of the cache configuration instruction field 31 is “4”), the address 22 in the address register 20 is used.
The entry address of the vertical entry is specified using the three bits from the bit to the 24th bit, and the block address is assigned to the tag memory 11 (tag memory entry 404) corresponding to the specified entry (eg, entry 00). Is stored. The data memory entries 405 to 407 (for example, entry 10, entry 20, and entry 30) of three ways (way 2 to way 4) following the tag memory entry 404 are not used. Also, 128 bytes of data (shown in the figure, data 1) from the block address stored in the tag memory entry 404
To data 16) are the corresponding data memory entry 504 (for example, entry 00) of the data memory 12 and the following three data memory entries 505 to 507.
(For example, entry 10, entry 20, entry 30)
, And the addresses in the block from "0000" to "1111" are given in binary. In order to specify the address in the block, four bits from the 25th bit to the 28th bit of the address in the address register 20 are used.

Next, a more specific operation will be described. Here, it is assumed that the basic block A of the tag memory 11 and the data memory 12 has a 32-byte configuration, the number of entries (the number of entries in the vertical direction) B is eight, and the number of levels (the number of ways in the horizontal direction) C is four.

Software-visible process state word 3
0, the cache configuration changing means 30 specifies that one basic block is used as a block unit in the cache configuration instruction field 31.
An output signal 300 is sent to the cache memory 10 to change the configuration of the cache memory 10 including the tag memory 11 and the data memory 12 into A (32 bytes) in block units, B entries, and C (4 Way). At the same time, output signals 301 to 303 indicating that the block unit is A (32 bytes) in the configuration of the cache memory 10 are transmitted.

When accessing data in the cache memory 10 from the scalar processing device, the address of the data to be accessed is set in the address register 20, and according to the output signal 301, the three bits of the 24th to 26th bits of the address are used. , The address in the vertical direction (entry direction) of the tag memory 11 and the data memory 12 is designated, and information for the C level (4 ways) is read from the tag memory 11 and the data memory 12 to which the address is designated. At this time, reading of the address information for four ways from the tag memory 11 is specified by the output signal 302. 4 read from the tag memory 11
The address information of the way and the real address are compared by the comparator 21, and the comparison result indicating which way matches is sent to the selection circuit 22.

From the data memory 12, the 27th and 28th bits of the address in the address register 20
The 8-byte data corresponding to the address in the block specified by the bit is read for four ways. Then, the selection circuit 22 selects one of the four bytes of 8-byte data read from the data memory 12 according to the comparison result from the comparator 21, and sends the selected data to the scalar processing device. . If the address information of the four ways read from the tag memory 11 does not match the real address, the data to be accessed is not registered in the data memory 12, and the data is read from the main storage device. The address information and the data are registered in the designated way of the designated tag memory entry and the designated memory memory entry, respectively. At that time, according to the output signal 303 from the cache configuration changing unit 33, 32 bytes of data are transferred from the main storage device to one data memory entry.

If it is specified in the cache configuration instruction field 31 that two basic blocks are used as a block unit, the cache configuration changing means 33
Sends out the output signal 300 to change the configuration of the cache memory 10 including the tag memory 11 and the data memory 12,
The configuration is changed so that the block unit is A × 2 (64 bytes), the number of entries is B, and the number of levels is C / 2 (2 ways). The cache configuration changing unit 33 also sends output signals 301 to 303 indicating that the block unit is A × 2 (64 bytes).

When accessing the data in the cache memory 10 from the scalar processing device, the address of the data to be accessed is set in the address register 20, and from the 23rd bit of the address to 25 th according to the output signal 301.
With the three bits up to the bit, the address in the vertical direction (entry direction) of the tag memory 11 and the data memory 12 is specified, and from the tag memory 11 and the data memory 12 to which the address is specified, the C / 2 level (2 way) is specified. ) Minute information is read. At this time, reading out the address information for two ways from the tag memory 11 is based on the output signal 30.
2, and the way (way 1 and way 2 ) in which the address information is stored is designated to be read. The comparator 21 compares the address information of the two ways read from the tag memory 11 with the real address, and a comparison result indicating which way it matches is sent to the selection circuit 22.

From the data memory 12, 3rd of the 26th to 28th bits of the address in the address register 20
The 8-byte data corresponding to the address in the block specified by the bit is read for two ways. Then, the selection circuit 22 selects one of the two-way 8-byte data read from the data memory 12 according to the comparison result from the comparator 21 and sends the selected data to the scalar processing device. . If the two-way address information read from the tag memory 11 does not match the real address, the data to be accessed is not registered in the data memory 12, and the data is read from the main storage device. The address information and the data are registered in the designated way of the designated tag memory entry and the designated memory memory entry, respectively. At that time, according to the output signal 303 from the cache configuration changing means 33, 64-byte data is transferred from the main storage device to two data memory entries that are continuous in the level direction.

If it is specified in the cache configuration instruction field 31 that four basic blocks are used as a block unit, the cache configuration changing means 33
Sends out the output signal 300 to change the configuration of the cache memory 10 including the tag memory 11 and the data memory 12,
The configuration is changed so that the block unit is A × 4 (128 bytes), the number of entries is B, and the number of levels is C / 4 (1 way). The cache configuration changing unit 33 also sends output signals 301 to 303 indicating that the block unit is A × 4 (128 bytes).

When accessing the data in the cache memory 10 from the scalar processing device, the address of the data to be accessed is set in the address register 20 and, according to the output signal 301, the three bits of the 22nd to 24th bits of the address are used. , An address in the vertical direction (entry direction) of the tag memory 11 and the data memory 12 is specified, and information corresponding to the C / 4 level (one way) is read from the tag memory 11 and the data memory 12 to which the address is specified. . At this time, the reading of the address information for one way from the tag memory 11 is specified by the output signal 302, and the way (way 1) in which the address information is stored is specified to be read. One-way address information read from the tag memory 11 is compared with the real address by the comparator 21, and a comparison result indicating whether the addresses match is sent to the selection circuit 22.

From the data memory 12, the address of the address in the address register 20 is stored in the fourth bit of the 25th to 28th bits.
The 8-byte data corresponding to the address in the block specified by the bit is read for one way. Selection circuit 22
Sends the 8-byte data read from the data memory 12 to the scalar processing device if the addresses match in the comparator 21. If the one-way address information read from the tag memory 11 does not match the real address, the data to be accessed is not registered in the data memory 12, and the data is read from the main storage device. The address information and the data are registered in the designated way of the designated tag memory entry and the designated memory memory entry, respectively. At this time, in accordance with the output signal 303 from the cache configuration changing means 33, 128 bytes of data are transferred from the main storage device to four data memory entries that are continuous in the level direction.

Next, the operation of the cache system according to the present embodiment will be described by taking as an example a case where an actual program is processed. Here, it is assumed that a program written in the FORTRAN language shown in FIG. 7 is used, which is also used in the description of the operation in the above-described conventional technique.
This program repeats the calculation of X (I) * Y (I) + Z (I) and substituting it for W (I) for integers from 1 to 32. Where X, Y,
Z indicates an array, and each array is aligned (aligned) on a 512-byte boundary, and X (1), Y (1), and Z
Assume that (1) is the start address of a 64-byte boundary. W is also an array.

First, when compiling the source code of this program using compiler software to generate an execution code, the characteristics of each array are examined.
In the case of the program used here, the size and alignment of the array are determined at the time of compilation. The compiler recognizes that in this program, since each array is aligned to 512 bytes, there are a plurality of arrays that use the same entry address on the cache, and the larger the number of ways in small block units, the higher the cache performance. The execution code is generated so that "1" is stored in the cache configuration instruction field 31 in the process state word 30 of the system which is software visible. When the generated execution code is actually executed, “1” is stored in the cache configuration instruction field 31 in the process status word 30, and the information of the cache configuration instruction field 31 is received. Changes the cache memory 10 to a configuration in which the block unit is A (32 bytes), the number of entries is B (8), and the number of levels is C (4 ways), according to the output signal 300.

When I = 1, the scalar processing device
(1) is loaded from the main storage device, but first accesses the cache memory 10. The address information of X (1) is held in the address register 20. At this time, the 24th to 26th bits of the address of the address register 20 are "
000 "(since the array is aligned on a 512-byte boundary), the way 1 of the tag memory 11
, The entry 10 of the way 2, the entry 20 of the way 3, and the entry 30 of the way 4 are read and compared by the comparator 21 with the real address of X (1).
Since data is not registered in the cache memory 10 at the first time of the program execution, the tag memory 11
And the real address do not match (cache miss). Therefore, the data is read from the main storage device, registered in the entry 00 of the way 1 of the data memory 12 as 32-byte data (data of X (1) to X (4)), and stored in the way of the tag memory 11. The address information is registered in the entry 00 of No. 1 and X is stored in the scalar processing device.
The data of (1) is sent.

Next, the data of Y (1) is similarly loaded from the main storage device. At this time, the address of Y (1) 2
Since the fourth to 26th bits are also “000”, the X and X in the tag memory 11 and the data memory 12 are
Entry 10 of a different way (way 2) from the case of (1)
Address information and 32-byte data (Y (1) to Y (1) to Y
(4)) is registered. The scalar processing device multiplies X (1) by Y (1).

Next, the data of Z (1) is similarly loaded from the main storage device. At this time, since the 24th to 26th bits of the address of Z (1) are also “000”, X (1) and Y in the tag memory 11 and the data memory 12 are stored.
Address information and 32-byte data (data of Z (1) to Z (4)) are registered in an entry 20 of a way (way 3) different from (1). Assuming that this time is time A, data as shown in FIG. 4A is registered in each entry in the data memory 11. The scalar processing device adds the previous multiplication result and Z (1), and stores the result (W (1)) in the main storage device. Here, assuming that the operation mode of the cache memory is the store-through mode, the store data is not registered in the cache memory 10 but is stored directly at the specified address of the main storage device.

When I = 2 after updating I, the data of X (2) is loaded. At this time, the address of X (2) is obtained by adding 8 bytes to the address of X (1). Since the value becomes the value, the 24th to 26th bits of the address of X (2) are “000”, and the in-block address (27th to 28th
Bit) becomes “01”. 24th bit of address
Since the 26th bit is “000”, the entry 00, the entry 10, the entry 20, and the entry 30 of the tag memory 11 are set.
Is read out and compared by the comparator 21 with the real address of X (2). At this time, since the address matches the address of entry 00 of way 1, comparator 21 sends the comparison result to selection circuit 22. Data memory 1
The 8-byte data specified by the in-block address “01” is read for four ways from the second entry 00, the entry 10, the entry 20, and the entry 30. The selection circuit 22 reads the comparison result from the comparator 21. Originally, the 8-byte data stored in the entry 00 of the way 1, that is, X (2) is selected and sent to the scalar processing device. Thereafter, similarly, since the data of Y (2) and Z (2) are registered in the cache memory 10, the data is transmitted from the cache memory 10 to the scalar processing device without accessing the main storage device.

Thereafter, when I is updated to become I = 5,
24th bit to 2 of each address of X (5), Y (5), Z (5)
The fifth bit becomes "001", and the entry addresses for accessing the tag memory 11 and the data memory 12 change to become entry 01, entry 11, entry 21 and entry 31, and X (1), Y (1), Z ( As in the case of processing (1), a cache miss occurs. But,
When processing I = 6, 7, and 8 further, a cache hit occurs. Assuming that the time when the process of I = 32 is completed is time B, at this time, the data memory 12
The data as shown in (b) is registered in each entry.

In this embodiment, by changing the configuration of the cache memory according to the program to be executed, the cache mishit process is performed every time I is updated in the conventional cache system. The cache mishit process needs to be performed only once, and the cache performance can be improved.

[0051]

As described above, according to the present invention, according to the contents stored in the cache configuration instruction field,
Since the configuration of the cache memory can be changed so that n basic blocks (A) are in block units and the number of ways at that time is C / n, the feature of the array when compiling a program by software is obtained. The optimal cache block unit is recognized based on the number of arrays and the number of used arrays, and the cache configuration can be changed to the optimal configuration for the program (block unit × number of entries × number of levels). As a result, the data registered in the cache memory can be used effectively, and the performance of the cache memory is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a basic block A, the number of entries B, the number of levels C, and each way of a cache memory.

FIG. 3 is a diagram showing an example of the contents of a cache memory, where (a), (b), and (c) indicate that the cache configuration fields are “1”, “2”, and “4”, respectively. FIG.

4A and 4B are diagrams for explaining the progress of processing in the cache system shown in FIG. 1, wherein FIG. 4A shows the contents of the data memory at time A, and FIG. 4B shows the contents of the data memory at time B; FIG.

FIG. 5 is a block diagram showing a configuration of a conventional cache system.

FIG. 6 is a diagram showing an example of the contents of a cache memory in the cache system shown in FIG.

FIG. 7 shows an example of a program for performing an assignment operation to an array.

8A and 8B are diagrams for explaining the processing progress in the cache method shown in FIG. 5, wherein FIG. 8A shows the contents of the data memory at time A, and FIG. 8B shows the contents of the data memory at time B; FIG. 3C is a diagram showing the contents of the data memory at time C.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Cache memory 11 Tag memory 12 Data memory 20 Address register 21 Comparator 22 Selection circuit 30 Process state word 31 Cache configuration instruction field 33 Cache configuration change means 300-303 Output signals 401-407 Tag memory entries 501-507 Data memory entries

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-157182 (JP, A) JP-A-5-225060 (JP, A) JP-A-51-32241 (JP, A) JP-A-4- 217051 (JP, A) JP-A-9-282225 (JP, A) Etsuko Shimizu et al., "Multiprocessor Cache Evaluation Environment with Variable Structure ATTE MPT-1," IEICE Technical Report, IEICE Communication Society, April 26, 1996, Vol. 96, No. 23, (CP SY96-14-27), p. 25-32 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/08-12/12 G06F 9/45

Claims (1)

(57) [Claims] 1. A variable cache scheme which is disposed between the processing apparatus for processing and loading data from said main memory and the main memory, a scalar processor for the processing device performs the processing of scalar instructions
A basic configuration having a set of C (C is an integer of 2 or more) levels in which the number of entries of the basic block (A) is B (B is an integer of 2 or more) is stored in the main storage device. A cache memory capable of storing a copy of data in a block unit, a cache configuration instruction field storing information indicating that n basic blocks are used as a block unit to be stored in the cache memory, and the cache According to the contents stored in the configuration instruction field, the cache memory is configured to change the configuration of the cache memory so that n basic blocks (A) are in block units and the number of ways at that time is C / n. And a cache configuration changing means for instructing the processing device to compile the source code of the program and
When generating executable code to be executed in the
The optimum cache block unit is recognized according to the characteristics of the RAM.
And the value of n is determined .