JP5480793B2 - Programmable controller - Google Patents

Description

  The present invention relates to a programmable controller equipped with a bit arithmetic processor that performs high-speed sequence control on plants and various machines such as steel, electric power, and water and sewage.

  In a programmable controller, a ladder language that can efficiently describe sequence control has been used. In the ladder language, information represented by 1 bit such as an open / closed state of a switch is input, and information represented by 1 bit such as a relay (relay) output is often output. For this reason, the programmable controller is often equipped with a dedicated bit arithmetic processor in order to perform 1-bit data processing unique to the ladder language at high speed.

  The bit arithmetic processor supports a dedicated instruction set suitable for handling 1-bit data. However, since the operation result is stored in a general-purpose memory element, a memory element such as 8-bit or 16-bit is used. Must match the access unit size. To write 1-bit data to a general-purpose memory device, a read-modify-write operation, that is, an operation of reading the memory with the access unit size, changing a part of the read data, and writing again with the access unit size Therefore, the ladder language processing has a feature that the number of memory accesses is larger than that of the general-purpose language processing.

  As a prior art related to the speeding up of a bit arithmetic processor, Patent Document 1 discloses that a memory access address and data in units of words for the past multiple times are stored in a buffer that can be accessed at high speed, and a bit to be accessed is stored. When the address of the word data to be included coincides with the address stored in the buffer, a device for reducing the number of memory accesses by using data on the buffer instead of the memory is described.

  On the other hand, in the field of general-purpose computers, cache memory has been used for speeding up memory access. However, with recent miniaturization of semiconductors, measures against soft errors in cache memory internal SRAM (Static Random Access Memory) In many cases, the cache memory is protected by adding ECC (Error Check and Correct) to the cache memory. Since the ECC addition unit is often designed to be about 4 bytes, the unit of writing to the cache memory is also 4 bytes or more. Even general-purpose computer instructions support writing of 1 byte or 2 bytes. However, if a write of a size smaller than the ECC additional unit is to be performed, a read-modify-write is performed on the cache memory.

  When read-modify-write is performed with a cache memory having a simple configuration, the cache memory is occupied for two or more cycles, and the pipeline processing of the processor is interrupted during that time. As a device for preventing the pipeline processing from being interrupted even if there is a read-modify-write, a store buffer having a plurality of stages is provided and the store processing is left behind. Patent Document 2 describes a configuration of a store buffer of a cache memory to which ECC is added. Since store processing by the store buffer is performed using the free time of the cache memory when executing instructions other than load / store instructions, the interruption of pipeline processing is definitely eliminated. Rather, it is a device that reduces the probability of interruption as much as possible.

  Japanese Patent Laid-Open No. 2004-228561 has a multi-port cache memory and separates the operand fetch (read) pipeline stage and the operand write pipeline stage, thereby efficiently executing instructions for data transfer between memories. Although the device is described, the operation at the time of cache miss and the operation at the time of address conflict between operand fetch and write are not described, and the read modify write processing is not mentioned at all.

Japanese Patent Laid-Open No. 11-39160 International Publication No. 2007/085597 Japanese Patent Laid-Open No. 4-40524

  It is conceivable to adopt pipeline processing and cache memory for speedup even in the bit arithmetic processor for ladder language processing. However, as described above, read modify write occurs frequently in ladder language processing. It is necessary to prevent stalling (interruption) of pipeline processing. If a multi-stage store buffer with an address comparator as in Patent Document 2 is used, the probability that the pipeline processing is interrupted can be reduced. However, the program written in the ladder language is bit-wise compared to the general-purpose language. The ratio of store instructions tends to be high, and the number of stages of the store buffer must be increased, resulting in an increase in the circuit scale necessary for implementation.

  On the other hand, most current general-purpose processors have the instruction set of RISC (Reduced Instruction Set Computer), so that arithmetic processing and load / store processing are executed with different instructions. It is like that. In other words, arithmetic processing is performed between general-purpose registers by arithmetic instructions, and load / store between the memory and the registers is performed by different instructions. For this reason, the pipeline for general-purpose processors has a configuration suitable for register-to-register operations, but ladder language processing is centered on operations between memory and accumulators, and the pipeline configuration for general-purpose processors is not necessarily processing efficiency. Is not good.

  Specific problems will be described in the case where ladder language processing is performed by a pipeline and memory configuration according to the prior art. FIG. 14 shows a typical RISC processor pipeline configuration. PC (Program Counter) is a stage for calculating an instruction address, IF (Instruction Fetch) is a stage for fetching an instruction, D (Decode) is a stage for decoding a fetched instruction, and EX (Execute) is an operation between registers or memory address calculation. , M (Memory) is a stage where the memory is read or written to the memory, and WB (Write Back) is a stage where the calculation result or read value is written back to the register. When performing read modify write accompanying bit data calculation, the M stage is divided into two, M1 and M2, and read is performed in the M1 cycle, and bit data is merged and written in the M2 cycle.

  Here, consider a case where the ladder diagram illustrated in FIG. 7A is executed with the pipeline structure of the above-described prior art. FIG. 7B is an example of a program obtained by converting the ladder diagram illustrated in FIG. 7A into a normal ladder language instruction sequence. FIG. 7C shows an example of a program in which it is converted into an instruction sequence for execution in the conventional pipeline configuration.

  Variables X0 to X3 represent inputs, and variables Y2 to Y3 represent outputs, each of which is stored in two word data in the memory as 1-bit data. FIG. 8 shows how these variables are allocated and stored in the memory. In FIG. 7B, LD (Load) is a load instruction from the memory to the accumulator, AND is an instruction for storing the logical product of the value loaded from the memory and the accumulator value in the accumulator, and ST (Store) is the accumulator value in the memory. The store instruction, OR, is an instruction for storing the logical sum of the value loaded from the memory and the accumulator value in the accumulator. In FIG. 7C, LD is a load instruction from the memory to the register, AND is an instruction for storing the logical product of two register values in the register, ST is an instruction for storing the register value in the memory, and OR is 2 This is an instruction for storing a logical sum of two register values in a register.

  FIG. 15 is a time chart showing an operation when the instruction sequence shown in FIG. 7C is executed in the pipeline configuration of FIG. As shown in FIG. 15, the first and second LD instructions start from cycles t0 and t1, respectively, and are executed as they are until cycles t5 and t6, and data is loaded into the registers R1 and R2. The third AND instruction is executed as it is from cycle t2 to t4. However, since the data of variable X1 necessary for the EX stage of cycle t5 has not been read yet, the pipeline stalls for one cycle ("-"). mark). The data of the variable X1 becomes available at the next cycle t6 when the execution of the M stage of the second LD instruction is completed, and thereafter is executed as it is until the cycle t8. The fourth ST instruction starts from cycle t3, but stalls together with the stall of the previous instruction in cycle t5. Subsequently, after cycles t6 and t7 are executed, in the M stage, read-modify-write is executed over two cycles of cycles t8 and t9. Therefore, the fifth LD instruction stalls at cycle t9 in addition to cycle t5.

  Similarly, the sixth LD instruction stalls at cycles t5 and t9, and the seventh OR instruction and the eighth ST instruction stall at cycles t9 and t11, respectively. The eighth ST instruction is subjected to read-modify-write over two cycles t14 and t15. As described above, in the conventional pipeline configuration, the normal ladder language requires 8 instructions to execute the processing described in 6 instructions, and a pipeline stall occurs in 3 cycles. Therefore, a total of 17 cycles are required to complete all the processes.

  An object of the present invention is to propose a pipeline configuration suitable for a programmable controller having a bit arithmetic processor for processing a ladder language and which does not cause a stall of pipeline processing by read-modify-write or the like. It is another object of the present invention to propose a pipeline and a cache memory configuration suitable for a bit arithmetic processor including a cache memory.

  In order to prevent pipeline processing from stalling in a bit operation processor that processes the ladder language, the operation result of the EX stage can be used in the EX stage of the next instruction executed in the next cycle, and the read modify write can be performed. The R (Read) stage, which is a new stage for pre-reading the contents of the target memory, is provided, the bit operation and bit data merging are performed at the next EX stage, and the result is the last W (Write ) Store in memory on stage.

Therefore, in order to achieve the above object, the present invention is a programmable controller that reads and writes a memory in units of words in which a plurality of 1-bit data to be subjected to bit operation processing are collected, and is included in a program The bit operation processor includes a bit operation processor that executes a bit operation instruction sequence in parallel by a pipeline processing mechanism, and the pipeline stage included in the bit operation processor decodes and decodes each instruction constituting the bit operation processing instruction. instructions are: a read stage of the decode stage for generating data addresses when involving memory access, the following the calculation stage of the read stage of reading from the memory the data to be bit operation target word by word, the operation stage Followed by the computation stage. It characterized in that there is a write stage for writing word data including the result of the bit operation to the same address as read data in the read stage.
Here, the memory holds a first address holding register holding an address of data read in the read stage, and an address of the data copied from the first address holding register until the write stage , And an address holding circuit having a second address holding register used as a write destination address of the write stage .

Further, the present invention, the memory is at least 2-way or more set associative or fully associative cache memory der Rutotomoni,
A first index holding register for holding index information extracted from the address of the cache entry read in the read stage ;
A first way holding register for holding way information hit in the read stage ;
A second index holding register for holding the index information copied from the first index holding register up to the write stage ;
A second way holding register for holding the way information copied from the first way holding register up to the write stage;
An address holding circuit that uses a combination of the index information in the second index holding register and the way information in the second way holding register as a write destination address of the write stage;
It is characterized by that.

  Further, in order not to stall pipeline processing even when instructions accessing the memory are continuous, the memory can independently perform one or more reads and one or more writes within a single pipeline processing cycle time. The memory is preferably more than a port.

  Note that Patent Document 3 describes a pipeline configuration in the order of cache read, operation, and cache write. However, since the purpose is to perform read and write independently, there is a difference between read and write. An address can be specified, so that a cache hit determination is performed even during a cache write. That is, it does not consider performing read-modify-write, and a 3-port memory of 2 reads + 1 writes is required, and the object and configuration are different from the present invention.

  According to the present invention, a program executed in a programmable controller having a bit arithmetic processor does not cause a stall of pipeline processing due to read-modify-write, so that a program written in a ladder language can be processed efficiently. it can. Similarly, since a stall of pipeline processing does not occur in a bit arithmetic processor having a cache memory, a program written in a ladder language can be processed efficiently. Also, by performing a cache hit determination at the preceding read stage at the time of execution of the store instruction, the cache replacement process at the write stage becomes unnecessary, so that pipeline control is simplified.

The figure which shows the internal structure and pipeline structure of a bit arithmetic processor with which the programmable controller which concerns on 1st Embodiment is provided. The figure which shows the whole structure of the programmable controller which concerns on 1st Embodiment. Block diagram showing the configuration when a 2-port memory is used as the data memory The figure which shows the detailed structure of the operation stage of the bit operation processor which concerns on 1st Embodiment. The figure which shows the structure of the cache memory which concerns on 2nd Embodiment. The figure which shows the detailed structure of the operation stage of the bit operation processor which concerns on 2nd Embodiment. Ladder diagram for explaining the operation of bit arithmetic processor and its program example The figure which shows the allocation to the memory of the variable used with the program of FIG. The figure which shows the instruction format of the instruction executed by the bit arithmetic processor The figure which shows a mode that the instruction code sequence with respect to the program of FIG. 7 was stored in memory. Time chart showing an operation example of the bit arithmetic processor according to the first and second embodiments Time chart showing an operation example when a cache miss occurs in the bit arithmetic processor according to the second embodiment The figure which expressed the pipeline structure which concerns on 1st Embodiment in contrast with FIG. A diagram showing a pipeline configuration of a typical RISC processor Time chart showing an example of operation of a bit arithmetic processor according to the prior art

Hereinafter, embodiments for carrying out the present invention will be described with reference to FIGS. 1 to 13.
<< First Embodiment >>
FIG. 1 is a diagram illustrating an internal configuration and a pipeline configuration of a bit arithmetic processor provided in the programmable controller according to the first embodiment of the present invention. FIG. 13 represents the pipeline configuration according to the first embodiment in comparison with the prior art of FIG. As shown in FIGS. 1 and 13, the pipeline configuration according to the present embodiment includes (1) a program counter (PC) stage, (2) an instruction fetch (IF) stage, (3) a decode (D) stage, ( 4) 6 stages of memory read (R) stage, (5) operation execution (EX) stage, and (6) memory write (W) stage.

  The PC stage includes an adder 102 for adding a constant “1” or a designated register value to a PC (program counter) 101 value indicating the immediately preceding instruction address, and a selector for selecting a register value indicating an addition result or a branch destination address. The instruction address of the instruction to be executed next to the instruction selected immediately before is set in the instruction address register 111 as the output of the stage. The IF stage reads an instruction corresponding to the instruction address set in the instruction address register 111 from the instruction buffer 30 and sets it in the instruction register 121.

  The D stage includes a decoder 122 that interprets the read instruction, and an adder 123 that adds the specified register value to the address extracted from the instruction by the decoder 122. If the decoded instruction involves memory access, the data address Is set in the data address register 131. Although not shown, control information necessary for subsequent stage control such as register selection and arithmetic function selection is extracted according to the decoding result.

  The R stage reads data corresponding to the data address indicated by the data address register 131 from the data memory 20. The read data is set in the word buffer 141 via the selector 132 that selects the bypass data from the next EX stage. Further, the data address indicated by the data address register 131 is set in the address holding circuit 22 provided in the data memory 20 so that it can be used again in the W stage.

  The EX stage has an ALU (Arithmetic Logic Unit: arithmetic unit) 142 and a bit merge mechanism 143, and performs an operation instructed by an instruction using a data value set in the word buffer 141 and / or a specified register value. Do. At this time, when performing bit data calculation, the bit data at the designated bit position is extracted from the word data to be calculated, and the calculation is performed, and the bit merge mechanism 143 is used to perform the calculation at the bit position. Word data is generated by embedding the resulting bit data. When the result is stored in the register, the register file 152 is written. When the result is stored in the data memory 20, the operation result data to be stored is written in the write buffer 151.

  The W stage stores the data set in the write buffer 151 at the data address set in the address holding circuit 22 in the R stage, that is, the same data address in the data memory 20 from which data was read out in the R stage.

  FIG. 2 is a diagram illustrating an overall configuration of the programmable controller according to the first embodiment. As shown in FIG. 2, the programmable controller 1000 is detachable from the CPU (Central Proseccing Unit) module 1, I / O (Input / Output) modules 2A and 2B, the I / O bus 3 connecting them, and the CPU module 1. And a program input device 4 connected to the computer. Each of the I / O modules 2A and 2B has an I / O bus connection circuit and an I / O interface circuit, and the type and number can be changed according to the required I / O specifications and the number of contacts. ing.

  The CPU module 1 includes a bit arithmetic processor 10, a data memory 20, an instruction buffer 30, an I / O bus control circuit 40, a memory controller 50, an external RAM (Random Access Memory) 60, a ROM (Read Only Memory) 70, and a general-purpose microprocessor. 80 and a communication I / F (Interface) 90.

  Data groups in a predetermined address range stored in the data memory 20 correspond to input data or output data exchanged with external devices (not shown) connected to the I / O modules 2A and 2B, respectively. The I / O bus control circuit 40 controls the I / O bus 3, writes input data obtained from an external device connected to the I / O modules 2A and 2B into the data memory 20, and reads out from the data memory 20. The output data is output to an external device connected to the I / O modules 2A and 2B via the I / O bus 3.

  The instruction buffer 30 returns the instruction for the instruction address requested from the bit arithmetic processor 10 if it is stored in the buffer, and returns the instruction from the external RAM 60 to the memory controller 50 if the instruction is not in the buffer. Request reading. The memory controller 50 reads / writes the external RAM 60 or the ROM 70 in response to requests from the bit arithmetic processor 10, the instruction buffer 30, the I / O bus control circuit 40, and the general-purpose microprocessor 80. The general-purpose microprocessor 80 controls the entire programmable controller 1000 such as writing a ladder program loaded from the program input device 4 to the external RAM 60 via the communication I / F 90. A program for operating the general-purpose microprocessor 80 is stored in the ROM 70.

  In this embodiment, the bit arithmetic processor 10, the data memory 20, the instruction buffer 30, the I / O bus control circuit 40, and the memory controller 50 are incorporated in a system LSI (Large Scale Integration) 100. To do.

  FIG. 3 is a diagram showing a configuration when a suitable 2-port memory is used as the data memory 20 according to the present embodiment. As shown in FIG. 3, the data memory 20 includes an address selector 201, an address holding circuit 22 having address holding registers 221 and 222, a write address selector 215, a write data selector 204, and a memory array 21.

  The address selector 201 selects either the value of the data address register 131 (FIG. 1) of the bit arithmetic processor 10 or the I / O data address output from the I / O bus control circuit 40. The address holding registers 221 and 222 hold the data address used for the execution of the R stage until the W stage after two cycles. That is, the data address is held in the first stage address holding register 221 as output data of the R stage, and the value is copied and held in the second stage address holding register 222 as output data of the EX stage. Make it available on stage.

  The write address selector 215 selects either the value of the data address register 131 or the value of the address holding register 222. The write data selector 204 selects either the value of the write buffer 151 or the value of I / O data output from the I / O bus control circuit 40.

  The memory array 21 is composed of a two-port memory in which two ports, a read port 1 and a write port 2, can be accessed within a single cycle. Therefore, it is possible to execute the R stage process of a certain instruction to be pipelined and the W stage process of another instruction to be executed in parallel in the same cycle. Although the memory array 21 is a two-port memory here, it may be a three-port or more memory that can be accessed by one or more read ports and one or more write ports in a single cycle. Note that the address holding circuit 22 is not used because reading and writing are performed independently during memory access from the I / O bus control circuit 40.

  FIG. 4 is a diagram showing a detailed configuration of an operation stage (EX stage, including some elements of other stages) of the bit operation processor according to the first embodiment. As shown in FIG. 4, in addition to the ALU 142, the operation stage receives selectors 144 and 145 for selecting the input of the ALU 142, 1-word (16 bits) data read from the data memory 20, or the operation result of this operation stage. A selector 132 (an element of the R stage) that selects any of the bypass data to be used for the operation again in the next instruction, the word buffer 141 that holds the selected word data, and the output of the ALU 142 that is the operation result are input. A bit merge mechanism 143 for merging with the word data, a write buffer 151 for holding the bit-merged data, and a register file 152 (W-stage element) for holding data such as an accumulator and a general-purpose register. The ALU 142 can perform a 1-bit or 1-word or 16-bit operation.

  FIG. 9 is a diagram illustrating an instruction format of an instruction executed by the bit arithmetic processor 10. As shown in FIG. 9, there are two types of instructions, both of which have a fixed length of 32 bits. The instruction format 1 includes a 5-bit instruction code (OP: Operation), a 4-bit bit position field (BA: Bit Address), and a 23-bit word address field (WA: Word Address), and targets bit data. . The instruction format 2 includes a 5-bit instruction code (OP), a 4-bit register designation field (RA), and a 23-bit word address field (WA), and targets word data.

  Next, taking the ladder program shown in FIGS. 7 and 8 as an example, the operation of the bit arithmetic processor 10 according to this embodiment will be described using the time chart of FIG. 11 with reference to FIG. FIG. 10 shows a state in which the instruction code string of the above-described instruction format 1 for the ladder program of FIG. 7B is stored in the program memory (external RAM 60). Assume that it is stored.

  First, the first LD instruction starts from cycle t0 and is executed as it is until cycle t5. At this time, in cycle t0 (PC stage), the address of the LD instruction is calculated and set in the instruction address register 111. In cycle t 1 (IF stage), the instruction is read from the instruction buffer 30 and set in the instruction register 121. In cycle t2 (D stage), the instruction is decoded and recognized as an LD instruction. In the first LD instruction, since the word address to be read is directly specified in the instruction, the corresponding word address is set in the data address register 131. In cycle t3 (R stage), data for one word including the target bit data is read from the data memory 20 and set in the word buffer 141. In cycle t4 (EX stage), the bit of the target variable X0 is extracted and set in the accumulator included in the register file 152. No operation is performed in cycle t5 (W stage) (shaded display portion in the figure).

  The second AND instruction starts from cycle t1 and is executed as it is until cycle t6. Note that no operation is performed in cycle t6 (W stage). At this time, the PC stage to the R stage are executed in the same manner as the first LD instruction. In cycle t5 (EX stage), after extracting the bit of the target variable X1, the ALU 142 calculates the logical product with the contents of the accumulator, and sets it again in the accumulator. In this embodiment, since word data including the variable X1 is read in the R stage executed before the EX stage, the pipeline processing is stalled at the EX stage of the AND instruction as in the conventional example (FIG. 15). Never do.

  The third ST instruction starts from cycle t2 and is executed as it is until cycle t7. The PC stage to the R stage are executed in the same manner as the first LD instruction. A major feature of this embodiment is that data is read in advance at the R stage even in the ST instruction. In cycle t6 (EX stage), the accumulator value (1 bit) is read, and the result merged with the value (1 word) of the word buffer 141 is set in the write buffer 151. In the W stage of cycle t7, the contents of the write buffer 151 are stored in the data memory 20. At that time, the contents stored in the address holding circuit 22 holding the value used in the R stage are used as the memory address of the storage destination. As described above, according to the pipeline configuration of the present embodiment, stalling of pipeline processing does not occur even when 1-bit data is written.

  By the same operation, the fourth LD instruction is cycled from cycle t3 to cycle t8, the fifth OR instruction is cycled from cycle t4 to cycle t9, and the sixth ST instruction is cycled from cycle t5 to cycle t10. It runs without stalling. As described above, according to the present embodiment, pipeline processing stall does not occur at all during execution of six instructions, and it is necessary to execute the process described by the six instructions shown in FIG. 7B. The number of cycles can be reduced from 17 cycles of the prior art to 11 cycles.

  As described above, according to the programmable controller including the bit arithmetic processor according to the first embodiment, the bit arithmetic processing peculiar to the ladder language processing can be executed at one cycle pitch without stalling the pipeline processing. A program written in a language can be executed at high speed.

<< Second Embodiment >>
Next, a second embodiment of the present invention in which the data memory 20 (see FIG. 2) in the first embodiment is configured by a cache memory will be described. FIG. 5 is a diagram illustrating a configuration of the cache memory according to the second embodiment. As shown in FIG. 5, the cache memory 20A as the data memory 20 is a two-way set associative cache memory, and includes an address selector 201A, index holding registers 221A and 222A, a way selector 203, a write data selector 204A, and a way 0. Tag memory 205, way 1 tag memory 206, LRU (Least Recently Used) memory 207, way 0 data memory 208, way 1 data memory 209, hit determination circuit 210, write-back control circuit 211, way data selector 212, way holding register 213 and 214 are provided. The address holding circuit 22 in FIG. 1 includes an address holding circuit 1 (22A) having index holding registers 221A and 222A and an address holding circuit 2 (22B) having way holding registers 213 and 214.

  The way data memories 208 and 209 each have 256 entries, and each entry holds 16 bytes (8 words) of data. The access unit of the cache memory is 16 bytes, and this 16-byte unit data is called one line. Each of the tag memories 205 and 206 has 256 entries, and each entry includes a valid bit V (Valid), a dirty bit D (Dirty), and a tag address (abbreviated as “tag” in FIG. 5). The LRU memory 207 has 256 entries and holds recently used ways.

  The address selector 201A selects either the value of the data address register 131 (FIG. 1) of the bit arithmetic processor 10 or the I / O data address output from the I / O bus control circuit 40, and from that, 12-bit A tag address and an 8-bit index value are extracted. The index holding registers 221A and 222A hold the index value portion (8 bits) extracted from the data address used for the execution of the R stage until the W stage after two cycles. Similarly, the way holding registers 213 and 214 hold the way hit in the R stage up to the W stage.

  The way selector 203 uses the index value stored in the second-stage index holding register 222A and the hit way stored in the second-stage way holding register 214 as the index value and way to write in the W stage as way data. The data is output to the memories 208 and 209. The write data selector 204A selects either the value of a write buffer 151A described later or the value of I / O data for one line output from the I / O bus control circuit 40.

  The hit determination circuit 210 compares the upper 12 bits of the data address to be accessed with the tag values output from the tag memories 205 and 206 for each way to determine a hit or a miss. The way data selector 212 selects either line data of way 0 data or way 1 data according to the output of the hit determination circuit 210. Note that the address holding circuits 1 and 2 (22A and 22B) are not used because the cache read and write are performed independently during the cache access from the I / O bus control circuit 40.

  The write-back control circuit 211 indicates that the target entry of the eviction way (the way that is not the most recently used way) indicated by the output of the LRU memory 207 at the time of a cache miss is included in the address range that is the target of the write-back mode. If there is, that is, if the data has been updated, the data read simultaneously with the tag is sent to the memory controller 50 to update the stored contents of the external RAM 60 (FIG. 2). Note that, for a predetermined address range corresponding to the I / O data address, the operation is switched to the write-through mode and the stored contents are immediately updated, so the write-back operation is not performed. Further, the read control circuit (not shown) reads the line data that caused the cache miss into the evicted target entry.

  The tag memories 205 and 206 and the way data memories 208 and 209 constituting the cache memory 20A are memories of two or more ports that can be accessed in parallel by a read port and a write port in a single cycle. This makes it possible to eliminate pipeline processing stalls caused by contention for access to the memory. Here, the cache memory 20A is a two-way set associative method, but may be a three-way or more set associative method or a full associative method.

  FIG. 6 is a diagram showing a detailed configuration of an operation stage (EX stage, including some elements of other stages) of the bit operation processor according to the second embodiment. As shown in FIG. 6, this operation stage configuration changes the size of input and output data in the operation stage configuration (FIG. 4) according to the first embodiment to one line length (16 bytes = 128 bits). Means for merging the word data of the operation result while holding data of one line length is added, and the other components are the same as in FIG.

  The selector 132A (the element of the R stage) uses one word (16 bits) in the data of one line length (16 bytes) read from the cache memory 20A or the operation result of this operation stage for the next instruction for the operation again. To select one of the bypass data. The line buffer 146 holds the read data of one line length. Further, the word merge mechanism 147 merges the word data of the operation result that is the output of the bit merge mechanism 143 into the line data held in the line buffer 146. The write buffer 151A holds merged data for one line.

  Here, as described above, the operation of the bit arithmetic processor according to the present embodiment will be described using the ladder program shown in FIGS. 7 and 8 as an example. The operation when the cache memory 20A is configured by a two-port memory capable of executing a read operation and a write operation in a single cycle, and all the target data hits the cache is as shown in FIG. It is the same as the time chart. The operation of this embodiment differs from that of the first embodiment in that data reading and writing in the R stage and W stage are performed in units of one line, and in the EX stage, the target word extracted by the selector 132A is added to the target word. The operation is performed on the data, and the word data of the operation result is merged with the line data stored in the line buffer 146 to generate line data to be written.

  Next, the operation when a cache miss occurs in the third ST instruction in the ladder program of FIG. 7B will be described using the time chart of FIG. The operations of the first LD instruction and the second AND instruction are the same as in FIG. When a cache miss occurs in the R stage (cycle t5) of the third ST instruction, the pipeline process stalls from cycle t5 to cycle t14, for example, in order to read data in the external RAM 60 via the memory controller 50. However, after the R stage is resumed at cycle t15, the pipeline process is executed without stalling. Thus, even when a cache miss occurs for the ST instruction, it is only necessary to replace the cache line in the R stage, so that the cache control is simplified.

  Even if the data address accessed by the next instruction of the ST instruction has the same index value as that of the ST instruction and the next instruction is a cache miss, if the cache memory is 2 way set associative or more, The entry is not purged before the ST instruction overwrites the line data at the W stage.

  As described above, according to the programmable controller including the bit arithmetic processor incorporating the cache memory according to the second embodiment, the bit arithmetic processing peculiar to the ladder language processing can be performed at one cycle pitch without stalling the pipeline processing. Since it can be executed, a program written in a ladder language can be executed at high speed.

  Although the description of the embodiment of the present invention has been completed above, the embodiment of the present invention is not limited to this, and various modifications can be made without departing from the spirit of the present invention.

1 CPU module 2A, 2B I / O module 3 I / O bus 4 Program input device 10-bit arithmetic processor 20 Data memory 20A Cache memory 21 Memory array 22, 22A, 22B Address holding circuit 30 Instruction buffer 40 I / O bus control circuit 50 Memory controller 60 External RAM
70 ROM
80 General-purpose microprocessor 90 Communication I / F
100 system LSI
1000 Programmable controller

Claims (5)

A programmable controller that reads and writes a memory in a unit of a word in which a plurality of 1-bit data to be subjected to bit operation processing are collected,
A bit operation processor that executes a bit operation processing instruction sequence included in the program in parallel by a pipeline processing mechanism;
The pipeline stage included in the bit operation processor has a read stage next to a decode stage that decodes each instruction constituting the bit operation processing instruction and generates a data address when the decoded instruction involves memory access. , are: the operation stage of the read stage of reading data to be calculated in units of words from the memory, the next computation stage, the read stage of the word data including the result of the computed bit calculated by the calculation stage There is a write stage that writes to the same address as the data read in
The memory is
A memory with two or more ports that can perform one or more reads and one or more writes within a single pipeline stage processing cycle time,
A first address holding register that holds an address of data read in the read stage, and an address of the data copied from the first address holding register up to the write stage, and a write destination address of the write stage A programmable controller comprising: an address holding circuit having a second address holding register to be used . A programmable controller that reads and writes a memory in a unit of a word in which a plurality of 1-bit data to be subjected to bit operation processing are collected,
A bit operation processor that executes a bit operation processing instruction sequence included in the program in parallel by a pipeline processing mechanism;
The pipeline stage included in the bit operation processor has a read stage next to a decode stage that decodes each instruction constituting the bit operation processing instruction and generates a data address when the decoded instruction involves memory access. , are: the operation stage of the read stage of reading data to be calculated in units of words from the memory, the next computation stage, the read stage of the word data including the result of the computed bit calculated by the calculation stage There is a write stage that writes to the same address as the data read in
The memory is
A two-port or more memory capable of performing one or more reads and one or more writes within a single pipeline stage processing cycle time, and at least two-way set associative or full associative of cache memory der Rutotomoni,
A first index holding register for holding index information extracted from the address of the cache entry read in the read stage ;
A first way holding register for holding way information hit in the read stage ;
A second index holding register for holding the index information copied from the first index holding register up to the write stage ;
A second way holding register for holding the way information copied from the first way holding register up to the write stage;
A programmable memory device comprising: an address holding circuit that uses a combination of the index information in the second index holding register and the way information in the second way holding register as a write destination address of the write stage. controller. The bit arithmetic processor is:
When executing a bit data store instruction in the bit operation processing instruction sequence ,
Read the original word data including the bits to be stored in the read stage and hold it in the storage unit,
The programmable controller according to claim 1 or 2, wherein the bit data obtained as a result of the bit operation calculated in the operation stage is merged with the original word data held. Cache hit determination is performed in the read stage, and in the write stage, the cache indicated by the index information held in the second index holding register of the address holding circuit and the way information held in the second way holding register The programmable controller according to claim 2, wherein line data in which word data including the result of the bit operation is merged is written in the entry. The programmable controller according to claim 2, wherein the write-through mode and the write-back mode are switched according to an address range to be stored.

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