JP4918535B2 - Cache memory, cache memory device and allocation method - Google Patents

Description

The present invention
The present invention relates to a cache memory connected to a microprocessor, and more particularly to the configuration of the data memory.

  In general, a cache data memory is read and written in one cycle, thereby reducing the number of MPU (microprocessor) wait cycles and realizing high-speed operation.

FIG. 2 is a configuration diagram of a conventional set associative cache memory.
The illustrated example has a 4-way set associative configuration. The data memory macros (units) 20 to 23 of way 1, the data memory macros 30 to 33 of way 2, and the data memory macros 40 to 43 of way 3 in the figure are as follows: The data memory macros 10 to 13 of the way 0 have the same configuration. The write data D0 to D3 are configured to be input to the data memory macros 10 to 43 with values selected from the data in the line buffer 1 or the MPU write data by the selectors 50 to 53, respectively. The read data from 43 is output via selectors 60-63, 70.

  In the cache memory, in order to output read data in one cycle, data memory macros 10 to 43 are prepared for every word (4 words in the figure) of all ways. By inputting an address to the address input terminal A of all the data memory macros 10 to 43 and asserting chip enable 0 to 3 [0: 3] to the chip enable input terminal CE, it is possible to read simultaneously. [0: 3] represents [0] to [3]. For the read data, one necessary data is selected from the word address and the way number where the cache hit occurs, and is returned to the MPU.

  Writing to each of the data memory macros 10 to 43 occurs due to a write request from the MPU or a cache miss. In the case of a cache miss, it occurs after the data read from the memory system is stored in the line buffer 1. When all the word data is prepared, writing is performed to the data memory macros 10 to 43 of all the words in any one way. For example, when writing to way 0, in order to write all words simultaneously in one cycle, an address is input to address input terminal A of data memory macros 10 to 13, and write data D0 to D3 are respectively input to data input terminal D. All the words are written simultaneously by asserting chip enable 0 [0: 3] to the chip enable input terminal CE of all words in way 0 and write enable 0 [0: 3] to the write enable input terminal WE. be able to.

FIG. 3 is an explanatory diagram of an address format.
The address output by the MPU is divided into a tag data part X1, an index address part X2, a word address part X3, and a byte address part X4 in the cache. The tag data part X1 is data stored in the tag memory of the cache. When the access request address from the MPU matches the valid tag memory data, a cache hit occurs. The index address part X2 is the number of bits indicating the number of lines that can be registered in one way of the cache. The word address portion X3 is the number of bits indicating the number of words in one line, and the byte address portion X4 is the number of bits indicating the number of bytes in one word.

FIG. 4 is an explanatory diagram of data storage positions of the data memory macros 10 to 43 of the ways 0 to 3.
For example, the data memory macros 10 to 13 each store data corresponding to data 0 to 3 in the word address part X3 of FIG. The memory address is made equal to the index address part X2. The same applies to the data memory macros 20 to 43 of the ways 1 to 3. As an example, the data storage position at the time of reading / writing is indicated by a shaded portion. When the MPU read request address is index address = 0 and word address = 2, data (x, 0, z) in FIG. 4 is read. When the index address of the read miss address = 511 and the write way = 0, the data in the line buffer is written at the location (0,511, z) in FIG.

FIG. 5 is an explanatory diagram of a conventional floor plan example.
Here, only the cache TAG memory unit 81, the MPU 82, the control unit 83, and the data memory unit 84 are shown. Reference numeral 80 denotes an LSI die size. In the data memory unit 84, 16 data memory macros 85 are arranged. These data memory macros 85 represent the data memory macros 10 to 13, 20 to 23, 30 to 33, and 40 to 43 in FIG.

FIG. 6 is a time chart when the data memory macros 10 to 43 are read / written.
The data memory macros 10 to 43 operate in synchronization with the clock. At the time of reading, the address RA1 and chip enable 0 to 3 [0: 3] are asserted and input to the clock edge T2. The read data RD1 is output so that the MPU can be latched at the clock edge T3. When writing (in this example, writing to way 0), address WA2, write data 0 to 3WD2, chip enable 0 [0: 3] are asserted and write enable 0 [0: 3] is asserted with respect to clock edge T4. And input. As a result, the values of the write data 0 to 3WD2 are written into the data memory macro.

  However, in the conventional configuration, it is necessary to prepare and connect the data memory macros 10 to 43 by the number of ways × the number of words (16 in the above example), and the MPU 82 and the data memory macro are connected as in the floor plan example of FIG. A portion where the wiring between 85 becomes long is formed, resulting in a delay, which hinders high-speed operation. In addition, there is a problem that the LSI unit price increases due to an increase in the area of the LSI.

The present invention employs the following configuration in order to solve the above-described problems.
<Configuration 1>
It is set to store cache data based on the N-way set associative method, and includes a plurality of data memory macro units each having a plurality of storage positions respectively corresponding to a plurality of cache data. Is determined by the way number used to identify each, the index number determined by the portion corresponding to the address where each cache data in the main memory is stored, and the other portion corresponding to the address in the main memory. A plurality of data memory macro units in a cache memory that can be accessed simultaneously, so that N cache data can be simultaneously written to the plurality of data memory macro units. A plurality of multiplexers respectively connected to any one of the data input terminals are provided, and the respective cache data designated by the same index number and different word numbers are stored in common in each data memory macro unit, and the same Each cache data designated by an index number and a different way number is stored in a different data memory macro unit.

<Configuration 2>
Another invention comprises a number of data memory macro units configured to store data from main memory based on an N-way set associative scheme, the number of data memory macro units being equal to the number of ways N; In a cache memory in which a plurality of storage locations are allocated so that the data memory macro unit can store data, each storage location is set to store a part of the data and identifies one of the N ways Is determined by the way number used for this purpose, the index number determined by the part corresponding to the address of the main memory where a part of the data is stored, and the other part of the corresponding address in the main memory. The same index number and different word numbers. Each data specified by the data memory macro unit is stored in common in each data memory macro unit, and each data specified by the same index number and different way numbers is stored in different data memory macro units. To cache memory.

<Configuration 3>
Another invention includes a microprocessing unit (MPU), a main memory combined with the MPU, and a cache memory set to store data from the main memory so that the data can be processed by the MPU. The cache memory includes a plurality of data memory macro units for storing data based on an N-way set associative method, and the number of the plurality of data memory macro units is equal to the number of ways N. apparatus.

<Configuration 4>
Yet another invention is a method of assigning storage locations to a cache memory having a plurality of data memory macro units, wherein the number of data memory macro units is equal to the number of ways N, and each storage location is stored in cache data. Is determined to be stored in accordance with the way number used to identify one of the N ways and the part corresponding to the address of the main memory in which each part of the cache data is stored. The data from the main memory is stored in the cache memory according to the assigned storage location specified by the index number being assigned and the word number determined by the other part of the corresponding address in the main memory An allocation method characterized by:

  According to the present invention, even if it is an N-way set associative cache memory, it is sufficient to provide at least N data memory macros, so that access can be made at high speed and the arrangement space can be reduced. it can.

Hereinafter, embodiments of the present invention will be described in detail using specific examples.
"Concrete example"
FIG. 1 is an explanatory diagram of data storage positions in the cache memory of the present invention. Prior to this, the configuration of the cache memory will be described.

FIG. 7 is a configuration diagram of a cache memory of a specific example.
The illustrated cache memory includes a line buffer 1, data memory macros 100 to 103, and selectors 200 to 203, 300 to 303, and 400. The line buffer 1 is a line buffer that stores a plurality of word data, as in the prior art, and is configured to store 4 words in this specific example. Each of the data memory macros 100 to 103 is a memory block that can be accessed at the same time, and is provided more than the number of ways of the cache memory. In this specific example, four data memory macros 100 to 103 are provided. Each of these data memory macros 100 to 103 has a capacity four times that of the conventional data memory macro shown in FIG. However, since the number of data memory macros is 1/4, the total capacity of the memory does not change.

  Each of the data memory macros 100 to 103 has addresses 0 to 3 at its address input terminal A, outputs of the selectors 300 to 303 at the data input terminal D, and chip enables 0 to 3 at the chip enable input terminal CE. Write enable 0 to 3 are input to the write enable input terminal WE, and the output Q is input to the selector 400. Details of these data storage positions will be described later with reference to FIG.

  The selectors 200 to 203 are selectors for selecting the write data D0 to D3 of each word output from the line buffer 1, and the selection outputs are input to the selectors 300 to 303. The selectors 300 to 303 are selectors for selecting the MPU write data and the outputs of the selectors 200 to 203, respectively, and the selection outputs are input to the data input terminals D of the data memory macros 100 to 103, respectively. It has become. The selector 400 is a selector that receives the output Q of each of the data memory macros 100 to 103 and sends the selected output as read data.

Next, the data storage state of each of the data memory macros 100 to 103 according to this specific example will be described with reference to FIG.
As shown in FIG. 1, each data memory macro 100-103 of this specific example has a different way number for each word address of the same index address, and data of the same word address in the same index of each way is stored in each data memory. The macros 100 to 103 are configured to be stored. For example, data of index address 0 and word address 0 of way 0 is stored in memory address 0 of data memory macro 100. In this specific example, memory address 1 is assigned data of index address 0 and word address 1 of way 1, and memory address 2 is assigned data of index address 0 and word address 2 of way 2. A word address is incorporated and assigned to each of the data memory macros 100 to 103. Therefore, the memory address is composed of the index address part X2 and the word address part X3 so as to correspond to this data storage position. For example, in the specific example, there are 512 index addresses and 4 word addresses, so the memory addresses are 0-2047.

  In addition, each data memory macro 100 to 103 can read four ways of data with the same index address and the same word address, and each data memory macro 100 to 103 has a way number with the same index address and the same word address. Are assigned one by one.

  That is, the data memory macros 100 to 103 of this specific example can read data of all ways of a specific index and a specific word when reading, and all words of a specific index and a specific way when writing. In this configuration, the number of data memory macros can be minimized.

The addresses at the time of reading / writing with respect to the data memory macros 100 to 103 allocated in this way are as follows.
● Memory address at read = Index address and word address part of MPU request address ● Memory address at write Index part = Index address part of cache missed word Word part = (Way number to write-Data memory number + 4) ÷ remainder of 4

Further, the data selected by the selector 400 at the time of reading and the data selected by the selectors 200 to 203 at the time of writing are operated according to the following equations.
-Way number of data read from each data memory macro 100-103 = (word address + data memory number) ÷ 4 remainder-Word number of write data to each data memory macro 100-103 = word part of write address the same

<Operation>
In the cache memory configured as described above, the memory address and the data selection operation at the time of reading / writing enable the reading from all the ways and the writing of all the words to one way in the same manner as in the past. .

  For example, when the MPU read request address is index address = 0 and word address = 2, (2, 0, 2), (3, 0, 2), (3, 0) of each of the data memory macros 100 to 103 shown in FIG. 0, 0, 2) and (1, 0, 2) are read (shown in shaded area A in the figure). Therefore, the order of ways corresponding to the data memory macros 100 to 103 is 2, 3, 0, 1. Further, when the index address of the read miss address = 511 and the write way = 0, (0,511,0), (0,511,3), (0,511,2) of each data memory macro 100-103. ), (0, 511, 1), the data (write data 0 to 3) of the line buffer 1 are respectively written (shown in the shaded area B in the figure). At this time, the order of the word addresses corresponding to the data memory macros 100 to 103 is 0, 3, 2, 1.

FIG. 8 is an explanatory diagram of a floor plan example of this specific example.
Since the number of data memory macros is four as compared with the prior art, the data memory unit 91 becomes smaller. Therefore, the die size 90 of this example can be made smaller than the die size 80 of the conventional LSI.

FIG. 9 is a time chart at the time of reading / writing of this specific example.
The data memory macros 100 to 103 operate in synchronization with the clock. At the time of reading, addresses 0 to 3 and chip enables 0 to 3 are asserted and input to the clock edge T2. At this time, the addresses 0 to 3 may be the same address. The read data is output as valid data at a timing that can be sampled at the clock edge T3. At this time, each data memory macro 100 to 103 outputs data of each way designated by the address.

  At the time of writing, addresses 0 to 3 and write data 0 to 3 are input to the clock edge T4. At this time, the index addresses 0 to 3 are the same, and the word address supplies a value determined by the way number to be written. Also, one of the write data 0 to 3 corresponding to the determined word address is selected and becomes the write data to the data memory macros 100 to 103. At the same timing, chip enable 0-3 and write enable 0-3 are asserted. As a result, data is written to the data memory macros 100 to 103.

<effect>
As described above, according to the specific example, the data storage position in each data memory macro is set to a different way number for each word address of the same index, and the data of the same word address in the same index of each way is each data Since the data is stored for each memory macro, the number of data memory macros can be reduced from 16 to 4 as a result. As a result, as shown in FIG. 8, for example, MPU and data memory macros 100 to 103 are used. The wiring between them can be shortened. As a result, the delay due to the wiring delay and the repeater can be suppressed to be small, and the performance can be improved. Further, in general, the area of the data memory macro is smaller when the same capacity is realized by one rather than by a plurality. This is because the number of parts (signals, power supply wirings, etc.) that can be shared increases by combining them into one, and the area can be reduced accordingly. As a result, the area of the LSI can be reduced, and the LSI unit price can be reduced. In addition, since data of all ways of a specific word can be read at the same memory address, high speed performance as a cache memory is not impaired.

<< Usage form >>
In the data storage positions of the data memory macros 100 to 103 in the specific example, the word address is assigned to the LSB side of the memory address, but may be assigned to other bits.
Further, the specific example of the data memory macro has been described as being used inside the LSI. However, the present invention is not limited to this. For example, the data memory macro can be applied as an SRAM IC component outside the LSI. In this case, the number of ICs can be reduced.

  In the above specific example, the number of ways is 4 and the number of words is 4. However, other ways and words are also applicable. In this case, the number of data memory macros is equal to or greater than the number of ways, and if the number of words is greater than the number of ways, the bit width of one data memory macro is set to two or more words. These words are the same way. For example, when the number of ways is 4 and the number of words is 8, the data memory macro is 4 and the bit width of one data memory macro is 2 words.

FIG. 10 is an explanatory diagram of data storage positions when the number of ways is 4 and the number of words is 8.
As shown in the figure, two words are assigned to the same memory address of each of the data memory macros 100 to 103. Thereby, at the time of reading, reading is performed in units of the same two words of each way, and at the time of writing, all words (0 to 7) of the target way are written.

  In the above specific example, the data storage state is as shown in FIG. 1, but the data storage position in each data memory block is set to a different way number for each word address (of the same index), and As long as the data of the same index and the same word address is stored separately for each data memory, it is not limited to such allocation.

FIG. 11 is an explanatory diagram showing a modification of the data storage position.
In this example, the data memory macros 100 to 103 are arranged to be accessed at the same memory address during writing (indicated by B in the figure). In this case, addresses at the time of reading / writing with respect to the data memory macros 100 to 103 are as follows.
● Memory address at the time of reading Index part = Same as index address of MPU request address Word part = (word address of MPU request address-data memory number + 4) ÷ 4 remainder ● Memory address at the time of writing Index part = address where cache missed Index address Word part = Way number

Further, the data selected by the selector 400 at the time of reading and the data selected by the selectors 200 to 203 at the time of writing are operated according to the following equations.
● Way number of data read from each data memory macro 100-103 = (MPU request address word address−data memory number + 4) ÷ 4 remainder ● Word number of write data to each data memory macro 100-103 = ( Way number + data memory number) ÷ 4 remainder

  For example, when the MPU read request address is index address = 0 and word address = 2, (2, 0, 2), (1, 0, 2), (1,0) of each of the data memory macros 100 to 103 shown in FIG. Data of (0, 0, 2) and (3, 0, 2) are read (shown in shaded area A in the figure). Therefore, the order of ways corresponding to the data memory macros 100 to 103 is 2, 1, 0, 3. If the index address of the read miss address = 511 and the write way = 0, (0, 511, 0), (0, 511, 1), (0, 511, 1) of each data memory macro 100-103. ) And (0, 511, 3), the data (write data 0 to 3) of the line buffer 1 are respectively written (shown in the shaded area B in the figure). At this time, the order of the word addresses corresponding to the data memory macros 100 to 103 is 0, 1, 2, 3.

It is explanatory drawing of the data storage position in the cache memory of this invention. It is a block diagram of the conventional cache memory. It is explanatory drawing of an address format. It is explanatory drawing of the conventional data storage position. It is explanatory drawing of the example of the conventional floor plan. It is a time chart at the time of the read / write of a prior art example. It is a block diagram of the cache memory of an example. It is explanatory drawing of the example of a floor plan of a specific example. It is a time chart at the time of read / write of a specific example. It is explanatory drawing of the data storage position in the case of 4 ways and 8 words. It is explanatory drawing which shows the modification of a data storage position.

Explanation of symbols

  100 to 103 data memory macro

Claims (10)

A plurality of data memory macro units each configured to store cache data based on an N-way set associative method and having a plurality of storage positions respectively corresponding to the plurality of cache data;
Each storage location has a way number used to identify one of the N ways;
An index number determined by a portion corresponding to an address in which each of the cache data of the main memory is stored;
Specified by a word number determined by another part of the corresponding address of the main memory;
The plurality of data memory macro units are each in a cache memory that can be accessed simultaneously,
A plurality of multiplexers respectively connected to any one data input terminal of the plurality of data memory macro units in order to permit simultaneous writing of N pieces of cache data to the plurality of data memory macro units;
The respective cache data designated by the same index number and different word numbers are stored in common in the respective data memory macro units, and the respective cache data designated by the same index number and different way numbers Are stored in different data memory macro units ,
A physical cache memory address is determined for each storage location in each data memory macro unit, and each cache data specified by the same index number and the same way number is stored in each data memory macro unit. A cache memory that is stored in the same cache memory address . 2. The cache memory according to claim 1 , wherein the respective cache data designated by the same index number and the same word number are stored at different cache memory addresses in the respective data memory macro units. Each cache data designated by the same index number constituting a part of the cache data stored in each data memory macro unit is designated by a different way number and a different word number. The cache memory according to claim 1. The line buffer of claim 1, further comprising a line buffer connected to a plurality of multiplexers for receiving the N data from the main memory for writing to the plurality of data memory macro units. Cache memory. 2. The cache memory according to claim 1 , wherein the number of ways N is four. Each of the plurality of cache data stored in each of the data memory macro units is set to a group of each of the cache data designated by the same index number, and the group is set to the cache memory address. The index number is set in order of increasing in a corresponding manner, and each of the cache data constituting each of the groups is periodically set in order of increasing word number. Item 4. The cache memory according to Item 1. 7. The cache according to claim 6, wherein an initial way number in the periodic sequence of the word numbers designating each cache data constituting the group of the cache data is different between the data memory macro units. memory. 2. The cache memory according to claim 1, wherein each of the cache data includes a word number from a main memory that is a multiple of the N. 2. The cache memory according to claim 1, wherein the number of the data memory macro units is a multiple of the N. 2. The cache memory according to claim 1, further comprising a multiplexer connected to a data output terminal of each data memory macro unit so as to permit simultaneous reading of N cache data from the plurality of data memory macro units. .

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