JP5963385B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device used for a magnetic energy regeneration circuit that controls a current flowing in an AC circuit.

  A power conversion device that performs power conversion by controlling on / off of a plurality of semiconductor switching elements is a known technique. For example, in a power converter for performing PWM (Pulse Width Modulation) control, a power supply voltage from an AC power supply is controlled by a bridge circuit composed of four reverse conducting semiconductor switches. Each reverse conducting semiconductor switch includes a free wheeling diode (FWD) connected in antiparallel, and is configured to conduct current in the reverse direction. The bridge circuit is a hard switching circuit that supplies power to the load circuit with a specified size.

  In such a power converter, while the reverse conducting semiconductor switch is on, a current flows from the power source to the load circuit via the reverse conducting semiconductor switch. On the other hand, when the reverse conducting semiconductor switch is turned off, if the load circuit is an inductive load circuit such as a coil, an induced electromotive force is generated, and a current flows in the reverse direction from the load circuit to the reverse conducting semiconductor switch. End up. At this time, by providing the FWD in the reverse conducting semiconductor switch, the reverse current that has flowed by the induced electromotive force can flow from the FWD to the inductive load.

  In such an AC circuit, a reactance voltage is generated by a pseudo electric resistance (reactance) generated in the load circuit, an inductance component of the wiring and the AC generator, and the like. When the reactance voltage is generated, the current supplied to the load circuit is reduced, the phase of the current waveform flowing through the load circuit is delayed, and the power factor in the AC circuit is lowered.

  In order to avoid the above-described problems, a low power factor AC circuit is provided with a magnetic energy regeneration circuit. In the magnetic energy regenerative circuit, the magnetic energy stored in the inductance is regenerated to reduce the conduction loss due to the generation of the reactance voltage and improve the conversion efficiency of the power converter (see, for example, Patent Document 1 below). .

  In Patent Document 1, when the current flowing through the load circuit is interrupted, the magnetic energy remaining in the circuit is stored in a storage capacitor provided in the bridge circuit, and the energy stored in the storage capacitor is loaded at the next turn-on. An invention of a current forward / reverse bidirectional snubber energy regenerative switch that is regenerated in an AC circuit by discharging to the circuit is disclosed.

  In such a magnetic energy regenerative circuit, a switching element developed so as to simultaneously realize the characteristics of low on-voltage characteristics, high-speed switching characteristics, and load short-circuit tolerance, each having a trade-off relationship is used. As such a switching element, for example, in an insulated gate bipolar transistor (IGBT), by reducing minority carrier injection from the collector region, low on-voltage characteristics are improved and high-speed switching characteristics are improved. And the technique which improves load short circuit tolerance is proposed (for example, refer to the following nonpatent literature 1 and the following nonpatent literature 2).

  However, since the conventional magnetic energy regeneration circuit using a switching element obtains high-speed switching characteristics at the expense of low on-voltage characteristics, the energy conversion efficiency of the magnetic energy regeneration circuit cannot be sufficiently improved.

  In addition, as a method for improving the low on-voltage characteristics of the switching element, the low on-voltage characteristics of the IGBT and FWD constituting the switching element are improved to reduce the overall on-voltage of the switching element, thereby converting the power. Techniques for improving the conversion efficiency of the apparatus have been proposed (see, for example, Patent Document 2 and Non-Patent Document 3 below).

  However, since the IGBT and the FWD are configured as separate semiconductor devices, an increase in the number of semiconductor devices increases a mounting area, which is an obstacle to miniaturization of the semiconductor device. Furthermore, since the magnetic energy regeneration circuit has a configuration in which switching elements are connected in series, the same magnitude of current flows through all the switching elements, which increases conduction loss in the entire magnetic energy regeneration circuit. There's a problem.

  In order to solve the above-described problem, a reverse conducting IGBT (RC-IGBT) in which an IGBT and an FWD are integrally formed on the same semiconductor substrate has been proposed (for example, Patent Document 3 below, Non-Patent Document 4 below and (See Non-Patent Document 5 below.) In the techniques of Non-Patent Document 4 and Non-Patent Document 5, a PN diode is built in the IGBT by providing an n region in a part of the p collector layer on the back surface of the semiconductor element on which the IGBT structure is formed. Therefore, by using RC-IGBT as a switching element of the magnetic energy regeneration circuit, the number of semiconductor elements necessary for the configuration of the magnetic energy regeneration circuit can be reduced, and the mounting area can be reduced.

By the way, as a method for improving the low on-voltage characteristics of the IGBT having the trench structure, the carrier concentration is reduced by limiting the carrier flow and accumulating it in the semiconductor element by the thinning structure of the emitter contact portion on the trench structure and the p channel. A method of increasing the number has been proposed (see, for example, Non-Patent Document 6 below). As another method, a high concentration n layer is provided between the p channel layer and the n ⁻ layer to generate a weak downward electric field, thereby accumulating holes in the semiconductor element to reduce the carrier concentration. A method of increasing the number has been proposed (see, for example, Non-Patent Document 7 below).

JP 2000-358359 A JP 2008-171294 A JP 2008-4867 A Y. Onozawa, 5 others, Development of the Next Generation 1200V Trench-Gate FS-IGBT Featuring Lower EMI Noise and Lower Switching Loss noise and lower switching loss (Korea), 19th International Symposium on Power Semiconductor Devices 2007 (ISPSD'07: Proceedings of the 19th International Symposium on Power Semiconductor Device) s and ICs 2007), 5 May 27-30, 2007, p. 13-16 H. Ruthing, 4 others, 600V-IGBT3: Trench Field Stop Technology in 70 μm Ultra-Thin Wafer Technology (600V-IGBT3: Trench Field Stop Technology in 70 μm Ultra-ThinTwin UK) 15th International Symposium on Power Semiconductor Devices 2003 (ISPSD'03: Proceedings of the 15th International Symposium on Power Semiconductor Devices and ICs 2003), April 2003, p. 66-69 R. Shimada, 7 others, A New AC Current Switch Cold MERS With Low On-State Voltage IGBTs (1.54V) For Renewable Energy and Power Saving Applications (A New AC Current Switch Called MERSw On-State Voltage IGBTs (1.54V) for Renewable Energy and Power Saving Applications, (USA), 20th International Symposium on Power Semiconductor Devices 2008 (ISPSD'08: Proceedings of the 20th International Phenomenon) wer Semiconductor Devices and ICs 2008), 5 May 18-22, 2008, p. 4-11 H. Ruthing, 4 others, 600V Reverse Conducting (RC-) IGBT For Drivers Applications in Ultra-Sin Wafer Technology (600V Reverse Conducting Applications in Tl.) (Technology), (Korea), 19th International Symposium on Power Semiconductor Devices 2007 (ISPSD'07: Proceedings of the 19th International Symposium on Power Semiconductor Devices and ICs 2007), May 27, 2007. 89-92 M. Rahimo, 5 others, A High Current 3300V Model Employing Reverse Conducting IGBTs Setting A New Benchmark In Output Power Capability (A High Current 3300V Module Developing Output Power Capability (USA), 20th International Symposium on Power Semiconductor Devices 2008 (ISPSD'08: Proceedings of the 20th International Symposium on Power Semiconductor Devices) and ICs 2008), May 18-22, 2008, p. 68-71 M. Kitagawa, 4 others, 4500V Injection Enhanced Insulated Gate Bipolar Transistor (IEGT) Operating In A Mode Mirror To A Thyristor (A 4500V Injected Enhanced Insulated Gated Bipolar Transistor Bipolar Transistor (IEGT) (Similar to a Thyristor), (USA), 1993 International Electronic Device Conference Technical Digest (IEDM '93 Technical Digest: International Electronic Devices Meeting 1993 Technical Digest) 12 May 1993, p. 679-681 H. Takahashi, 3 others, Carrier Stored Trench-Gate Bipolar Transistor-Anovel Power Device For High Voltage Application- (Carrier Stored Trench-Gate Bipolar Transistor-A Novell Powerp (USA), 8th International Symposium on Power Semiconductor Devices 2003 (ISPSD '96: Proceedings of the 15th International Symposium on Power Semiconductor Devices and ICs 1996), May 20-23, 1996, p.349-352

  However, in the technologies of Non-Patent Document 4 and Non-Patent Document 5 described above, the lifetime control process is applied to increase the reverse recovery characteristics of the diode. In the techniques of Non-Patent Document 2 and Non-Patent Document 4 described above, the concentration of the p collector layer is lowered to lower the minority carrier injection efficiency, and the high-speed switching characteristics of the IGBT operation are realized. As described above, the conventional RC-IGBT has sufficient low on-voltage characteristics that are in a trade-off relationship with these characteristics in order to realize high-speed switching characteristics during IGBT operation and high speed reverse recovery characteristics of the built-in PN diode. It has not been improved.

Further, when the technologies of Non-Patent Document 6 and Non-Patent Document 7 described above are applied to the RC-IGBT, the ON voltage of the FWD built in the IGBT becomes high during the FWD operation. In Non-Patent Document 6, the thinning-out structure of the emitter contact portion corresponds to eliminating a part of the anode electrode of the built-in FWD, which deteriorates the current conduction capability and increases the on-voltage. Further, in Non-Patent Document 7, by providing a high-concentration n layer between the p-channel layer and the n ⁻ layer, the hole injection efficiency from the p-channel layer during the FWD operation deteriorates, and the on-voltage increases. End up. In other words, RC- by incorporating FWD in a FS-IGBT (hereinafter referred to as trench FS-IGBT) having a trench structure having a field stop region (hereinafter referred to as FS region) with sufficiently improved low on-voltage characteristics. Even if the IGBT is manufactured, the low on-voltage characteristics obtained by the trench FS-IGBT cannot be obtained. As described above, the conventional technology has a problem in that sufficient power conversion efficiency cannot be obtained because the low on-voltage characteristics are not sufficient.

  An object of the present invention is to provide a semiconductor device capable of improving power conversion efficiency in a magnetic energy regenerative circuit in order to eliminate the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention is connected in series between an AC power supply and an inductive load, and controls a power supplied to the inductive load. The power conversion device includes a bridge circuit configured by a plurality of reverse conducting semiconductor switches, and a magnetic energy regeneration circuit having a capacitor connected between DC terminals of the bridge circuit, At least one of the reverse conducting semiconductor switches constituting the magnetic energy regeneration circuit is an insulated gate bipolar transistor having a diode integrated therein, and the forward direction of the diode and the forward direction of the insulated gate bipolar transistor are reversed. The insulated gate bipolar transistor is connected in the direction A conductive type semiconductor substrate, a second conductive type channel region provided in a surface layer of the front surface of the semiconductor substrate, a trench provided so as to penetrate the channel region and reach the semiconductor substrate, A gate electrode provided inside the trench via a gate insulating film; a first conductivity type emitter region provided in part of a surface layer of the channel region in contact with the trench; and the emitter region An emitter electrode in contact with the semiconductor substrate, a first conductivity type field stop region having a lower resistance than the semiconductor substrate, provided on the back side of the semiconductor substrate, and shallower than the field stop region on the back side of the semiconductor substrate A collector region of a second conductivity type provided at a position, and the diode includes the channel region, the field stop region, and the collector region. Some of the collector region is provided so as to penetrate in the depth direction, anda high-concentration region of high impurity concentration first conductivity type than said field stop region, the high concentration region The surface area of the high-concentration region on the back surface of the semiconductor substrate is formed in a region facing the central portion of the second channel region, and is 2% or more and 40% or less of the area of the active region through which the current flows in the semiconductor substrate. And
The channel region is divided by the trench into a first channel region and a second channel region in contact with the emitter region and the emitter electrode, and the first channel region on the front surface of the semiconductor substrate. Is formed wider than the surface area of the second channel region on the front surface of the semiconductor substrate, and part of the surface of the first channel region includes the first channel region and the emitter. A plurality of emitter contact portions for controlling the area in contact with the electrode are provided.

  According to the above-described invention, in the semiconductor device in which the diode is incorporated in the insulated gate bipolar transistor, the surface area of the first channel region is formed larger than the surface area of the second channel region, and the first contact area is formed by the emitter contact portion. The area where one channel region and the emitter electrode are in contact is controlled. Therefore, carriers can be prevented from flowing from the first channel region to the emitter electrode during the operation of the insulated gate bipolar transistor. Further, the first channel region and the second channel region are separated by the surface layer of the front surface of the semiconductor substrate, so that the first channel is formed inside the semiconductor substrate during the operation of the insulated gate bipolar transistor. It is possible to prevent the region from being connected to the emitter electrode through the second channel region. Further, by controlling the surface area and formation position of the high concentration region on the back surface of the semiconductor substrate, it is possible to prevent minority carriers from being injected from the collector region into the high concentration region during the operation of the insulated gate bipolar transistor. it can. Thereby, the low on-voltage characteristic of the insulated gate bipolar transistor incorporating the diode can be improved over the low on-voltage characteristic of the conventional reverse conducting semiconductor switch. Further, since minority carriers are injected from the first channel region during the operation of the diode, the low on-voltage characteristics of the diode can be improved over the low on-voltage characteristics of the conventional reverse conducting semiconductor switch.

  According to the semiconductor device of the present invention, there is an effect that the power conversion efficiency can be improved in the magnetic energy regeneration circuit provided with the semiconductor element.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the description of each embodiment and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a circuit diagram using the semiconductor device according to the first embodiment. The circuit shown in FIG. 1 includes a magnetic energy regeneration circuit 111 connected in series between an inductive load circuit 112 and an AC power supply 113, and a control circuit 114. The magnetic energy regeneration circuit 111 includes a first reverse conducting semiconductor switch having the IGBT 101 and the diode 102, a second reverse conducting semiconductor switch having the IGBT 103 and the diode 104, and a third reverse conducting semiconductor switch having the IGBT 105 and the diode 106. And a fourth reverse conducting semiconductor switch having the IGBT 107 and the diode 108, and a capacitor 125 connected between the DC terminals of the bridge circuit. Each reverse conducting semiconductor switch is provided with a gate drive circuit for driving each reverse conducting semiconductor switch. At least one of the reverse conducting semiconductor switches, for example, the IGBT 101 and the diode 102 constituting the first reverse conducting semiconductor switch are integrally formed in the same semiconductor device 100.

  The control circuit 114 performs on / off control of the magnetic energy regeneration circuit 111 at a frequency synchronized with the load circuit 112 or the AC power supply 113 by outputting a switching signal for controlling the gate drive circuits 121 to 124. Yes. In the control circuit 114, a pair of the first reverse conducting semiconductor switch and the fourth reverse conducting semiconductor switch, the second reverse conducting semiconductor switch, and the third reverse conducting semiconductor switch located on the diagonal line are connected to the AC power supply 113. Switching signals are supplied to the respective gate drive circuits so that they are alternately turned on at the same period as the voltage waveform.

  When the voltage of the AC power supply 113 is positive, by turning on the IGBT 103 and the IGBT 105, a current flows simultaneously through two paths of the diode 102 and the IGBT 105 and the IGBT 103 and the diode 108. When the IGBT 103 and the IGBT 105 are turned off and the IGBT 101 and the IGBT 107 are turned on immediately before the voltage of the AC power supply 113 is inverted from positive to negative, the magnetic energy stored in the inductance of the load circuit 112 is changed to the diode 102, the capacitor 125, and the diode 108. The capacitor 125 is charged along the path. When charging is completed and the voltage of the AC power supply 113 is inverted from positive to negative, the capacitor 125 is discharged through the path of the IGBT 107, the capacitor 125, and the IGBT 101. At this time, a current flows through two paths of the diode 106 and the IGBT 101 and the IGBT 107 and the diode 104 simultaneously. Next, when the IGBT 103 and the IGBT 105 are turned on and the IGBT 101 and the IGBT 107 are turned off immediately before the voltage of the AC power supply 113 is inverted from negative to positive, the magnetic energy stored in the inductance of the load circuit 112 is converted to the diode 106, the capacitor 125, The capacitor 125 is charged through the path of the diode 104. When charging is completed and the voltage of the AC power supply 113 is inverted from negative to positive, the capacitor 125 is discharged through the path of the IGBT 103, the capacitor 125, and the IGBT 105. At this time, a current flows through two paths of the diode 102 and the IGBT 105 and the IGBT 103 and the diode 108 simultaneously. These are repeated thereafter. In this way, magnetic energy is stored in the capacitor 125, and the magnetic circuit is regenerated by discharging the magnetic energy to the load circuit 112 each time the voltage of the AC power supply 113 is reversed between positive and negative, thereby improving the power factor in the circuit.

FIG. 2 is a sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a plan view showing the semiconductor device according to the first embodiment. As shown in FIG. 2, in the semiconductor device 100, an n ⁻ support substrate 1 is used as an n-type silicon substrate. The semiconductor device 100 includes, for example, n ^- having field stop region provided on the rear surface side of the supporting substrate 1 (FS region) ^- a gate electrode of trench structure provided on the front surface side of the supporting substrate 1, n This is an FS-IGBT having a trench structure (trench FS-IGBT). The semiconductor device 100 is a reverse conducting IGBT (RC-IGBT) having a configuration in which, for example, a PiN diode 102 is built in the IGBT 101. In the circuit shown in FIG. 1, four semiconductor devices 100 as shown in FIG. 2 are required as the first to fourth reverse conducting semiconductor switches.

As shown in FIG. 2, a p-channel region 4 is provided on the surface layer of the front surface of the n ⁻ support substrate 1 on the front surface of the semiconductor device 100. A trench 11 is provided so as to penetrate the p-channel region 4 and reach the n ⁻ support substrate 1. The p channel region 4 separated by the trench 11 has a configuration in which the first channel region 2 and the second channel region 3 are alternately and repeatedly formed. At this time, the width between the side surfaces of the trench in contact with the first channel region 2 (hereinafter referred to as the width of the first channel region 2) is the width between the side surfaces of the trench in contact with the second channel region 3 (hereinafter referred to as the width of the first channel region 2). The width of the second channel region 3).

A part of the surface layer of the second channel region 3 is provided with n ⁺ emitter regions 6 in contact with the trench 11 and spaced apart from each other. A gate electrode 5 is provided in the trench 11 via a gate insulating film 12. On the front surface of the n ⁻ support substrate 1, an emitter electrode 7 in contact with the n ⁺ emitter region 6 and the second channel region 3 is provided.

As shown in FIG. 3, the trench 11, the first channel region 2, the second channel region 3 between the first channel region 2, the gate electrode 5, and the n ⁺ emitter region 6 are connected to the p channel region 4. The surface layer is provided in a stripe shape. The first channel region 2 is surrounded by the trench 11, and the first channel region 2 and the second channel region 3 are separated by the trench 11. A breakdown voltage structure region 14 is provided so as to surround the p-channel region 4. All the trenches 11 may be connected at the ends.

An interlayer insulating film (not shown) is provided on the front surface of the n ⁻ support substrate 1, and a first contact portion 21 for electrically connecting the emitter electrode 7 and the first channel region 2 and A second contact portion 22 is provided. The first contact portion 21 corresponds to an emitter contact portion.

The first contact portion 21 is provided on the surface of the first channel region 2 in, for example, a square shape that is sufficiently smaller than the surface area of the first channel region 2. The second contact portion 22 is provided in a stripe shape on the surface of the emitter electrode 7. For example, when the area of a current flowing region (hereinafter referred to as an active region) of the semiconductor device 100 having a square shape with a side of 9.6 mm is 6 mm ² , for example, the width of the first channel region 2 is set to 16 μm, and the second In the case where the width of the channel region 3 is 4 μm and the width of the trench 11 is 1 μm, the size of the first contact portion 21 is preferably a square shape having a side of 5 μm, for example.

On the other hand, as shown in FIG. 2, the back surface of the semiconductor device 100, n ^- the surface layer of the back surface of the supporting substrate 1, n ^- n-type FS region 8 of low resistance is provided than the support substrate 1. A p collector region 9 is provided on the surface layer of the FS region 8. A part of the surface layer of the p collector region 9 is provided with an n ⁺ high concentration region 10 having a higher concentration than the FS region 8. The n ⁺ high concentration region 10 is formed in a region substantially opposite to the central portion of the second channel region 3. Further, the surface area of the n ⁺ high concentration region 10 on the back surface of the n ⁻ support substrate 1 is provided to be 2% or more and 40% or less of the area of the active region. A collector electrode 13 is provided on the surfaces of the p collector region 9 and the n ⁺ high concentration region 10.

As described above, the PiN diode 102 formed of the second channel region 3, the n ⁻ support substrate 1 and the FS region 8, and the n ⁺ high concentration region 10 is formed integrally with the IGBT 101 in the semiconductor device 100. can do.

Further, the first channel region 2 and the second channel region 3 are separated from each other by the trench 11 on the front surface of the n ⁻ support substrate 1. It is possible to prevent the emitter electrode 7 from being connected via the inside of the n ⁻ support substrate 1.

  Further, the surface area of the first channel region 2 can be made larger than the surface area of the second channel region 3 by providing the width of the first channel region 2 wider than the width of the second channel region 3. it can. In addition, by providing the first contact portion 21 sufficiently smaller than the surface area of the first channel region 2, the area where the first channel region 2 and the emitter electrode 7 are connected can be controlled. As a result, carriers can be prevented from flowing out from the first channel region 2 to the emitter electrode 7 during operation of the IGBT 101, and surface carriers are sufficiently accumulated, so that the low on-voltage characteristics of the IGBT 101 are improved. be able to. In addition, since minority carriers are sufficiently injected from the second channel region 3 during the operation of the PiN diode 102, the low on-voltage characteristics of the PiN diode 102 can be improved. The reason will be described later.

Further, by controlling the formation position and formation area of the n ⁺ high concentration region 10 on the back surface of the n ⁻ support substrate 1, a small number is changed from the p collector region 9 to the n ⁺ high concentration region 10 during the operation of the IGBT region 101. Carriers can be prevented from being injected. The reason will be described later.

4 to 8 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment. First, as shown in FIG. 4, a wafer to be an n ⁻ support substrate 1 of an n-type silicon substrate is prepared, and a trench 11 is formed in a stripe shape and a first channel region 2 on the surface layer of the n ⁻ support substrate 1. It is formed so as to surround the region to be. At this time, the trench 11 has a region having an interval corresponding to the width of the first channel region 2 and a region having an interval corresponding to the second channel region 3 narrower than the width of the first channel region 2. These are formed at intervals such that they are alternately and repeatedly formed. In forming the trench 11, the bottom surface of the trench 11 can be formed with a radius of curvature of about 0.5 μm. Next, a gate insulating film 12 is grown in the trench 11 and filled with an oxide film such as polysilicon to form the gate electrode 5.

Next, a p-channel region 4 shallower than the depth of the trench 11 is formed on the front surface of the n ⁻ support substrate 1 by ion implantation and thermal diffusion. At this time, the p-channel region 4 is separated into the first channel region 2 and the second channel region 3 by the trench 11.

Next, an n ⁺ emitter region 6 is formed in part of the surface layer of the second channel region 3 by ion implantation and thermal diffusion. Next, an interlayer insulating film such as BPSG (Boro-Phospho Silicate Glass) (not shown) is formed on the front surface of the n ⁻ support substrate 1. Next, the first contact portion 21 and the second contact portion 22 are opened in the interlayer insulating film by patterning treatment and heat treatment. The first contact portion 21 is formed at one location on the surface of the first channel region 2, for example, in a square shape. The second contact portion 22 is formed in a stripe shape along the n ⁺ emitter region 6.

  Next, for example, an aluminum (Al) film to be the emitter electrode 7 is deposited on the surface of the interlayer insulating film by sputtering. Next, heat treatment is performed after the aluminum film is processed by photolithography to form a wiring pattern. Next, a surface protection film (not shown) made of, for example, polyimide is formed on the surface of the semiconductor substrate 100, and contact holes for extracting electrodes of the pad portions of the emitter electrode 7 and the gate electrode 5 are opened by patterning and heat treatment, The electrode surface for connection is exposed.

Then, as shown in FIG. 5, n ^- polishing the back surface of the supporting substrate 1 to a desired thickness of about 100 [mu] m. Next, as shown in FIG. 6, after forming the FS region 8 in the surface layer on the back surface of the n ⁻ support substrate 1 by ion implantation, the FS region 8 is activated by annealing treatment. Next, a p collector region 9 is formed in the surface layer of the FS region 8 by ion implantation. Next, a photoresist (not shown) is applied to the surface of the p collector region 9 and a baking process is performed. Thereafter, the photoresist is patterned, and in the region to be each chip, 2% or more and 40% or less of the area of the active region at a position almost opposite to the central portion of the second channel region 3 having the n ⁺ emitter region 6. A hole of the size (hereinafter referred to as a resist hole) is opened.

Next, for example, phosphorus is ion-implanted from the resist hole into the surface layer of the p collector region 9 to form an n ⁺ high concentration region 10 in a part of the surface layer of the p collector region 9 as shown in FIG. Next, as shown in FIG. 8, the surface of the p collector region 9 and the n ⁺ high concentration region 10 is irradiated with, for example, a semiconductor laser 15 to perform laser annealing, and the p collector region 9 and the n ⁺ high concentration region 10 are formed. Activate. Next, the photoresist is removed.

  Next, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film are stacked in this order on the back surface of the semiconductor device 100 as the collector electrode 13 by, for example, a vacuum deposition method. Next, the semiconductor device 100 is completed by cutting the wafer into individual chips along the dicing line.

  The shape of the resist hole is a substantially circular shape having a curved portion without a corner portion, and preferably a circular shape. The reason is that when a polygonal resist hole is opened, the cross-sectional shape of the vertical PiN diode 102 becomes a polygonal shape, and electric field concentration may occur at the corners.

As described above, according to the first embodiment, in the semiconductor device 100 in which the PiN diode 102 is built in the IGBT 101, the surface area of the first channel region 2 is formed wider than the surface area of the second channel region 3. In addition, the area where the first channel region 2 and the emitter electrode 7 are connected is controlled by the first contact portion 21. Therefore, it is possible to prevent carriers from flowing out from the first channel region 2 to the emitter electrode 7 during the operation of the IGBT 101. In addition, since the first channel region 2 and the second channel region 3 are separated by the trench 11, the first channel region 2 is the second channel in the semiconductor substrate 100 during the operation of the IGBT 101. Connection to the emitter electrode 7 through the channel region 3 can be prevented. Further, by controlling the surface area and formation position of the n ⁺ high concentration region 10 on the back surface of the semiconductor substrate 100, minority carriers are injected from the p collector region 9 into the n ⁺ high concentration region 10 during the operation of the IGBT 101. Can be prevented. Thereby, the low on-voltage characteristic of the semiconductor device 100 can be improved over the low on-voltage characteristic of the conventional reverse conducting semiconductor switch. Further, since minority carriers are injected from the first channel region 2 during the operation of the PiN diode 102, the low on-voltage characteristics of the PiN diode 102 are improved more than the low on-voltage characteristics of the conventional reverse conducting semiconductor switch. Can do. Moreover, since the magnetic energy regeneration circuit uses a switching frequency of about 50 to 60 Hz, which is a commercial power supply frequency, high-speed switching characteristics are not required. Therefore, since it is not necessary to reduce the concentration of the p collector region 9 or perform lifetime control as in the conventional case, it is possible to prevent the on-voltage of the IGBT 101 and the on-voltage of the PiN diode 102 from increasing. . Further, by fabricating the semiconductor device 100 by integrating the IGBT 101 and the PiN diode 102, it is possible to reduce the size compared to the conventional reverse conducting semiconductor switch in which the IGBT and the PiN diode are fabricated on separate semiconductor substrates.

(Embodiment 2)
In the first embodiment, a plurality of first contact portions 21 may be provided in the first channel region 2 surrounded by the trench 11. Other configurations of the semiconductor device are the same as those in the first embodiment. The method for manufacturing the semiconductor device according to the second embodiment is substantially the same as that of the first embodiment.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

Example 1
A semiconductor device 100 was manufactured in accordance with Embodiment 1 (hereinafter referred to as Example 1). In Example 1, n ^- as the supporting substrate 1, was prepared n-type silicon substrate having a diameter of 6 inches and a thickness of 500μm and an impurity concentration of 8.0 × 10 ¹³ cm ^-3. N after backside grinding ^- the thickness of the support substrate 1 was 135 .mu.m. A formation region of one semiconductor element was a square shape having a side of 9.6 mm. The area of the active region was 6 mm ² . The width of the first channel region 2 was 16 μm. The width of the second channel region 3 was 4 μm. The width and depth of the trench 11 were 1 μm and 5 μm, respectively. The thickness of the gate oxide film was 100 nm. Polysilicon was used as the gate electrode 7. The depth of the p-channel region 4 was 2.5 μm. In forming the p-channel region 4, boron (B) was used as a dopant, the dose amount was 8.0 × 10 ¹³ cm ⁻² , and the heat treatment temperature and time were 1150 ° C. and 2 hours. The depth of the n ⁺ emitter region 6 was set to 0.4 μm. In forming the n ⁺ emitter region 6, arsenic (As) was used as a dopant, and the dose amount was 5.0 × 10 ¹⁵ cm ⁻² .

BPSG was used as an interlayer insulating film, and its thickness was 1.0 μm. The first contact portion 21 has a square shape with one side of 5 μm. In the first channel region 2 surrounded by the trench 11, the first contact portion 21 is formed at one location. As the emitter electrode 7, aluminum containing 1% of silicon (Si) was used. The heat treatment temperature after patterning of the emitter electrode 7 was set to 400 ° C. The thickness of the surface protective film was 10 μm. The heat treatment temperature after patterning the surface protective film was set to 300 ° C. For the formation of the FS layer 8, phosphorus (P) was used as the dopant, and the dose amount was 5.0 × 10 ¹³ cm ⁻² . The p collector region 9 was formed using boron as a dopant, with a dose of 3.0 × 10 ¹³ cm ⁻² and an acceleration voltage of 40 keV. For the formation of the n ⁺ high concentration region 10, phosphorus was used as a dopant, the dose amount was 5.0 × 10 ¹⁵ cm ⁻² , and the acceleration voltage was 80 keV. The shape of the resist hole was circular, and its area was 1.2 mm ² which is 2% of the area of the active region. The irradiation energy density of laser annealing performed on the p collector region 9 and the n ⁺ high concentration region 10 was ² J / cm ² . As the collector electrode 13, a titanium film, a nickel film, and a gold film were laminated in this order.

  The current-voltage characteristics of the above-described conventional semiconductor device in which the first embodiment (RC-IGBT), the trench FS-IGBT, and the PiN diode were formed on different semiconductor substrates were compared. FIG. 9 is a characteristic diagram showing a current-voltage characteristic during the IGBT operation of the semiconductor device according to the first embodiment. FIG. 10 is a characteristic diagram showing current-voltage characteristics during the FWD operation of the semiconductor device according to the first embodiment. As a result of Example 1 shown in FIG. 9, the on-voltage during operation of the IGBT 101 in Example 1 is measured. As a result of Example 1 shown in FIG. 10, the on-voltage during operation of the PiN diode 102 in Example 1 is measured. The rated voltage and rated current of Example 1 are 1200 V and 75 A, respectively. Note that the conventional trench FS-IGBT was designed to simultaneously realize low on-voltage characteristics and high-speed switching characteristics. The conventional PiN diode is designed to realize low on-voltage characteristics and high-speed switching characteristics at the same time.

From the results shown in FIGS. 9 and 10, it can be seen that the on-state voltages when the IGBT 101 and the PiN diode 102 of Example 1 are operating when a current of 75 A flows are 1.55 V and 1.47 V, respectively. . In contrast, it can be seen that the on-voltages of the conventional trench FS-IGBT and the conventional PiN diode are 1.96V and 1.80V, respectively. Thereby, in Example 1, it turned out that ON voltage can be reduced compared with the conventional trench FS-IGBT and the conventional PiN diode. At this time, the current density of Example 1 is 125 A / cm ² .

  Further, the conventional trench FS-IGBT and PiN diode described above were designed to realize only the low on-voltage characteristics, and the current-voltage characteristics were measured in the same manner as the measurements shown in FIGS. As a result, the on-voltages of the trench FS-IGBT and the PiN diode were 1.52V and 1.41V, respectively. In other words, it was found that Example 1 can obtain substantially the same on-voltage as the trench FS-IGBT and PiN diode designed to realize only the low on-voltage characteristics. As a result, it was found that in Example 1, the low on-voltage characteristics almost the same as those of the conventional switching element specialized only in the low on-voltage characteristics can be realized. Further, in the first embodiment, the IGBT 101 and the PiN diode 102 are manufactured on the same semiconductor substrate, so that the size can be reduced as compared with the conventional switching element manufactured on another semiconductor substrate.

In addition, the current-voltage characteristics of a semiconductor device (hereinafter, referred to as a comparative example of Example 1) in which only the formation position of the n ⁺ high concentration region 10 was changed in Example 1 were measured. In the comparative example of Example 1, in forming the n ⁺ high concentration region 10, the position of the resist hole is changed from the position corresponding to the central portion of the second channel region 3 having the n ⁺ emitter region 6. It is shifted about 2mm to the side. As a result, in the comparative example of Example 1, the on-voltage during the operation of the IGBT 101 was 2.01V. The on-state voltage during the operation of the PiN diode 102 was almost the same as in Example 1. From this result, in Example 1, by providing the n ⁺ high concentration region 10 in the central portion of the formation region of the PiN diode 102, the on-voltage during the operation of the IGBT 101 can be maintained as in the conventional semiconductor switch. all right. The reason is presumed that the electron current supplied from the surface of the semiconductor device is concentrated in the n ⁺ high concentration region 10 during the operation of the IGBT 101 and minority carrier injection from the p collector region 9 easily occurs. .

Furthermore, the current-voltage characteristics were measured by changing the area of the n ⁺ high concentration region 10 in Example 1. FIG. 11 is a characteristic diagram showing current-voltage characteristics with respect to changes in the area of the cathode region of the FWD of the semiconductor device according to the first embodiment. FIG. 11 shows the on-voltage during operation of the IGBT 101 and the on-voltage during operation of the PiN diode 102 due to a change in the ratio of the area of the n ⁺ high concentration region 10 to the area of the active region. From the results shown in FIG. 11, it can be seen that as the area of the n ⁺ high concentration region 10 increases, the on-voltage during the operation of the IGBT 101 increases and the on-voltage during the operation of the PiN diode 102 decreases. Further, in the range A where the ratio of the area of the n ⁺ high concentration region 10 to the area of the active region is 2% or more and 40% or less, the low on-voltage characteristics are maintained during both the IGBT 101 operation and the PiN diode 102 operation of the first embodiment. You can see that

(Example 2)
In Example 1, the current-voltage characteristics of a semiconductor device (hereinafter referred to as Example 2) in which a plurality of first contact portions 21 are formed in each first channel region 2 surrounded by the trench 11 are measured. did. FIG. 12 is a characteristic diagram illustrating current-voltage characteristics of the semiconductor device according to the second embodiment. FIG. 12 shows the on-voltage during the operation of the IGBT 101 and the on-voltage during the operation of the PiN diode 102 due to a change in the number of formed first contact portions 21. From the results shown in FIG. 12, when the first contact portion 21 is not provided, that is, when the first channel region 2 is electrically floating, the ON voltage when the PiN diode 102 is operated may be 2.25V. all right. At this time, the on-voltage during operation of the IGBT 101 maintains the same low on-resistance characteristics as the conventional switching element. Accordingly, it has been found that it is necessary to provide at least one first contact portion 21 and to electrically connect the first channel region 2 and the emitter electrode 7.

  Further, it was found that when the first contact portion 21 is provided at five or more locations, the on-voltage during the operation of the IGBT 101 is 2.32 V or more. The reason is as follows. For example, a semiconductor device when the first channel region 2 and the second channel region 3 are not separated in the second embodiment (hereinafter referred to as a comparative example of the second embodiment) will be described as an example. FIG. 13 is a plan view illustrating an example of a comparative example of the semiconductor device according to the second embodiment. In the comparative example of Example 2, even when the first contact portion 21 is not provided, the on-voltage during the IGBT operation becomes 2.2V. This is because the first channel region 2 is connected to the entire surface of the emitter electrode 7 through the second channel region 3 in the semiconductor device, thereby retaining surface carriers in the first channel region 2. It is because it becomes impossible. Accordingly, it has been found that if the connection area between the first channel region 2 and the emitter electrode 7 is excessively increased, the on-voltage during the IGBT operation increases.

  Although the present invention describes a semiconductor device in which the width of the first channel region 2 and the width of the second channel region 3 are 16 μm and 4 μm, respectively, the width of the first channel region 2 and the second channel region 2 are described. The same effect can be obtained also in a semiconductor device in which the width of the channel region 3 is 20 μm and 4 μm, respectively, or a semiconductor device in which the width is 25 μm and 5 μm, respectively. That is, the same effect can be obtained if the width of the first channel region 2 is wider than the width of the second channel region 3.

  In the above description, the magnetic energy regeneration circuit has been described as an example in the present invention. However, the present invention is not limited to the above-described embodiment, and can be applied to circuits having various configurations.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used in a power conversion device.

1 is a circuit diagram using a semiconductor device according to a first embodiment; 1 is a cross-sectional view showing a semiconductor device according to a first embodiment; 1 is a plan view showing a semiconductor device according to a first embodiment; 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 6 is a characteristic diagram showing current-voltage characteristics during the IGBT operation of the semiconductor device according to the first embodiment; FIG. 7 is a characteristic diagram showing current-voltage characteristics during FWD operation of the semiconductor device according to the first embodiment; FIG. 6 is a characteristic diagram showing current-voltage characteristics with respect to an area change of the cathode region of the FWD of the semiconductor device according to the first embodiment; FIG. 6 is a characteristic diagram showing current-voltage characteristics of a semiconductor device according to a second embodiment; 7 is a plan view illustrating an example of a comparative example of a semiconductor device according to a second embodiment; FIG.

Explanation of symbols

1 n ^- supporting board 2 channel region (first)
3 channel region (second)
4 p channel region 5 gate electrode 6 n ⁺ emitter region 7 emitter electrode 8 field stop region 9 p collector region 10 n ⁺ high concentration region 11 trench 12 gate insulating film 13 collector electrode 100 semiconductor device 101 IGBT
102 PiN diode

Claims (1)

In a semiconductor device that constitutes a power conversion device that is connected in series between an AC power supply and an inductive load and controls the power supplied to the inductive load,
The power conversion device has a magnetic energy regeneration circuit having a bridge circuit composed of a plurality of reverse conducting semiconductor switches, and a capacitor connected between DC terminals of the bridge circuit,
At least one of the reverse conducting semiconductor switches constituting the magnetic energy regeneration circuit is an insulated gate bipolar transistor having a diode integrated therein, and the forward direction of the diode and the forward direction of the insulated gate bipolar transistor are Connected in the opposite direction,
The insulated gate bipolar transistor is:
A first conductivity type semiconductor substrate;
A channel region of a second conductivity type provided in the surface layer of the front surface of the semiconductor substrate;
A trench provided so as to penetrate the channel region and reach the semiconductor substrate;
A gate electrode provided inside the trench via a gate insulating film;
A first conductivity type emitter region provided in contact with the trench in a part of a surface layer of the channel region;
An emitter electrode in contact with the emitter region;
A first conductivity type field stop region having a lower resistance than the semiconductor substrate, provided on the back side of the semiconductor substrate;
A second conductivity type collector region provided at a position shallower than the field stop region on the back surface side of the semiconductor substrate;
The diode is
The channel region;
The field stop region;
A high concentration region of a first conductivity type having a higher impurity concentration than the field stop region provided in a part of the collector region so as to penetrate the collector region in the depth direction;
The high concentration region is formed in a region facing the central portion of the second channel region, and the surface area of the high concentration region on the back surface of the semiconductor substrate is 2 times the area of the active region through which the current of the semiconductor substrate flows. % To 40%,
The channel region is divided by the trench into a first channel region and a second channel region in contact with the emitter region and the emitter electrode,
The surface area of the first channel region on the front surface of the semiconductor substrate is formed wider than the surface area of the second channel region on the front surface of the semiconductor substrate,
A semiconductor device comprising a plurality of emitter contact portions for controlling an area where the first channel region and the emitter electrode are in contact with each other on a part of the surface of the first channel region.

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