JP5960322B2 - Determination of clock mode of memory system - Google Patents

Abstract

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Description

  Flash memories are widely used in a wide variety of nonvolatile memory types as mass storage for consumer electronic devices such as digital cameras and portable digital music players. The integration of currently available flash memory components is composed of two stacked dies, can be up to 32Gbits (4GB), and the size of one flash component is small, so the use of a typical USB flash device Suitable for

  The advent of 8 megapixel (8 million) pixel digital cameras and portable digital entertainment devices with music and video capabilities has prompted a very high capacity requirement to store large amounts of data. It cannot be handled by a flash memory device. Therefore, a large number of flash memory devices are incorporated together in the memory system, effectively increasing the available storage capacity. For example, a 20 GB flash memory storage density may be required for such applications.

  FIG. 1 is a block diagram of a prior art memory system 10 in which a host system 12 is integrated. The flash memory system 10 includes a memory controller 14 that communicates with the host system 12 and a plurality of nonvolatile memory devices 16. The host system 12 includes a processing device such as a microcontroller, a microprocessor, or a computer system. The flash memory device 10 of FIG. 1 is configured to include one channel 18, and the memory device 16 is connected to the channel 18 in parallel. One skilled in the art will appreciate that the memory system 10 has more or less than four memory devices connected to the channel 18.

  Channel 18 includes a set of common buses, which include data and control lines connected to all corresponding memory devices. Each memory device is enabled / disabled by a respective chip select signal CE # 1, CE # 2, CE # 3 and CE # 4 provided by the memory controller 14. “#” Indicates that the signal is an active low logic level signal. Memory controller 14 is responsible for issuing commands and data over channel 18 to selected memory devices based on the operation of host system 12. Data read from the memory device is transferred to the memory controller 14 and the host system 12 via the channel 18. The operation of the flash memory system 10 can be asynchronous or synchronous. FIG. 1 shows an example of a synchronous system that uses a clock CLK, which is provided to each memory device 16 in parallel. Flash memory system 10 is generally referred to as a multi-drop configuration, and memory device 16 is connected in parallel to channel 18.

  In flash memory system 10, non-volatile memory devices 16 can be substantially identical to one another (not necessarily so) and are typically implemented as NAND flash memory devices. Those skilled in the art will appreciate that the flash memory is configured in multiple banks, each bank being configured in multiple blocks to facilitate block erase. Most commercially available NAND flash memory devices are configured to have two memory banks.

  There are specific problems that adversely affect system performance. The configuration of the flash memory system 10 imposes physical performance limitations. With a large number of parallel signals extending across the system, the integrity of the signals they carry will be degraded by crosstalk, signal skew, and simultaneous switching noise (SSN). The power consumption of such a configuration is problematic because each signal track between the flash controller and the flash memory device is frequently charged or discharged for signal transmission. With increasing system clock frequency, power consumption will increase.

  Since the drive capability of one memory device is small compared to the load of a long signal track, there is a practical limit on the number of memory devices that can be connected in parallel to the channel. Furthermore, as the number of memory devices increases, more chip enable signals (CE #) will be required, and the clock signal CK will need to be routed to additional memory devices. The problem of clock performance due to a wide range of clock distributions is well known and needs to be solved. Therefore, to accommodate a memory system with many memory devices, a controller with more channels must be used, or in addition or not, the system must be clocked at a lower frequency. There is. A controller configured with multiple channels and additional chip enable signals increases the cost of the memory system. Otherwise, the memory system is limited to a small number of memory devices.

  It would therefore be desirable to provide a memory system device architecture capable of high speed operation while overcoming the problems associated with conventional memory systems having memory devices connected in parallel with each other.

An embodiment of a clock mode circuit will be described by way of example only with reference to the accompanying drawings.
FIG. 1 is a block diagram of a prior art flash memory system. FIG. 2A is a general block diagram of a serial memory system that receives clock signals in parallel. FIG. 2B is a general block diagram of a serial memory system that receives clock signals in series. FIG. 3A is a block diagram of a serial memory system that receives clock signals in series according to one embodiment. FIG. 3B is a timing diagram illustrating the operation of the memory system of FIG. 3A. FIG. 3C is a block diagram of a serial memory system that receives clock signals in parallel according to another embodiment. FIG. 3D is a timing diagram illustrating the operation of the memory system of FIG. 3C. FIG. 4 is a block diagram of a memory device having a native core and a serial input / output interface suitable for use with the serial memory system of FIGS. 3A and 3B. FIG. 5 is a block diagram illustrating an example configurable input circuit that can be used in the serial memory system of FIGS. 3A and 3C. FIG. 6 is an example of a circuit diagram of the mode setter of FIG. FIG. 7 is a sequence diagram illustrating the operation of the mode setter of FIG. FIG. 8A is an example of the configurable input circuit shown in FIG. FIG. 8B is a timing diagram illustrating the operation of the circuit of FIG. 8A. FIG. 9 is a block diagram of an example of a dynamically configurable serial memory system. FIG. 10 shows another example of the clock switch circuit used in the memory device shown in FIG. FIG. 11 is a flowchart of a method for configuring a clock operation mode of a memory device.

  In a first aspect, a semiconductor device that receives a clock and input data is provided. The semiconductor device includes a configurable input circuit operable in a first mode that receives coincident (coincident) edges of the clock and data inputs, and further includes data to sample the input data. Provide shifted clock edges located within the active window. The configurable input circuit is operable in the second mode and receives a non-coincident edge between the clock and the input data in order to sample the input data. In an example of this aspect, the semiconductor device further includes an input pin that provides a voltage to the configurable input circuit for setting the first mode and the second mode. The input pin includes a reference voltage pin that is set to one of a low power supply level and a high power supply level to set the second mode, and the pin is further configured to set to the first mode Set to the reference voltage level. The reference voltage level can be between a low power supply level and a high power supply level, and the reference voltage level is used by the configurable input circuit to sense the logic level of the input data.

  In a further embodiment of this aspect, the configurable input circuit includes a single-ended input buffer and a differential input buffer. A single-ended input buffer is coupled to a data input pin that receives input data and is enabled (operational) in the second mode and disabled (non-operational) in the first mode. The differential input buffer is coupled to a data input pin that receives input data and is enabled in a first mode to sense the logic level of the input data with respect to voltage. Alternatively, the configurable input circuit provides a shifted clock edge in response to the clock. The clock synthesizer includes one of a delay locked loop and a phase locked loop, and the clock synthesizer can be disabled in the second mode.

  In a second aspect, the present invention provides a configurable memory device. The configurable memory device includes a mode setter (which sets the mode), a clock switch, and a configurable data input / output buffer. The mode setter senses the voltage level of the reference voltage input port and provides a mode selection signal corresponding to the sensed voltage level. The clock switch is coupled to a clock input port that receives at least one of a parallel complementary clock signal and a serial complementary clock signal. The clock switch generates a complementary internal clock signal corresponding to the parallel complementary clock signal in response to the first logic state of the mode selection signal, or is responsive to the second logic state of the mode selection signal. Thus, a complementary internal clock signal corresponding to the serial complementary clock signal is generated. A configurable data input / output buffer is connected to the data input port and the reference voltage input port and in response to the second logic state of the mode selection signal, the data received at the data input port for the voltage level. Sense. In an embodiment of this aspect, the mode setter includes a sensing circuit and a latch. The sensing circuit compares the voltage level with a preset reference voltage and provides a sensing output corresponding to the voltage level relative to the preset reference voltage. The latch latches the sense output and provides a mode selection signal having one of a first logic state and a second logic state.

  In this embodiment, the sensing circuit includes a reference voltage circuit and a comparator. The reference voltage circuit provides a preset reference voltage, and the comparator provides a sense output in response to the voltage level and the preset reference voltage. The reference voltage circuit includes a voltage divider connected between VDD and VSD and a power interrupt device that interrupts current through the voltage divider after a predetermined time period. The mode setter includes a delay circuit that turns off the power shut-off device after a predetermined time period when the reset signal is driven to an inactive logic state. The delay circuit includes an n-bit counter that is enabled when the reset signal is in the inactive logic state and drives the most significant bit to the active logic state. The most significant bit is driven to an active logic state when 2n active edges of the clock signal are counted, n is an integer value greater than 1, and the delay circuit is the logic with the most significant bit active. A disable signal corresponding to the state is generated to turn off the power shut-off device.

  In yet another embodiment of this aspect, the clock switch includes a clock input buffer, a clock generator, and a clock output buffer. The clock input buffer is responsive to a first logic state of the mode selection signal to provide a buffered parallel complementary clock signal and is further configured to be serially complementary in response to the second logic state of the mode selection signal. Providing a sensed clock signal corresponding to a typical clock signal. The clock generator is either a buffered parallel complementary clock signal when the mode selection signal is in the first logic state or a sensed clock signal when the mode selection signal is in the second logic state. In response, a complementary internal clock signal is generated. The clock output buffer drives a complementary internal clock signal through the clock output port when the mode select signal is in the second logic state. The clock input buffer includes a comparator and a pair of buffers. The comparator is enabled in response to the second logic state mode select signal and provides a sensed clock signal in response to the serial complementary clock signal. A pair of buffers is enabled in response to the second logic state mode selection signal and provides a parallel complementary clock signal buffered in response to the parallel complementary clock signal. The clock output buffer includes a pair of drivers enabled in response to the second logic state mode select signal and drives a complementary internal clock signal through the clock output port.

  In a further embodiment, the clock generator includes a clock synthesizer and a switch circuit. The clock synthesizer provides a first clock signal and a second clock signal that is shifted 180 degrees relative to the first clock signal in response to the sensed clock signal. The switch circuit passes the first clock signal and the second clock signal as complementary internal clock signals when the mode selection circuit is in the second logic state. The switch circuit passes the buffered parallel complementary clock signal as a complementary internal clock signal when the mode selection circuit is in the second logic state. The clock synthesizer can be one of a phase locked loop or a delay locked loop. The clock synthesizer provides a third clock signal and a fourth clock signal, the third clock signal is shifted 90 degrees with respect to the first clock signal, and the fourth clock signal is the third clock signal. It is shifted 180 degrees with respect to the signal. The clock generator further includes a phase selection circuit that selectively provides either the complementary internal clock signal or the third and fourth clock signals to the clock output buffer.

  According to another embodiment, the configurable data input / output buffer receives input data corresponding to either sensed data resulting from a comparison between data and voltage levels, or buffered data corresponding to the data. A data input buffer for selectively providing in response to a mode selection signal. The data input buffer includes a comparator and a buffer. The comparator is enabled when the mode selection signal is in the second logic state and provides input data in response to the voltage level and the voltage of the data. The buffer is enabled when the mode select signal is in the first logic state and provides buffered data. The configurable data input / output buffer further includes a data switch that selectively sends one of the input data and the local read data to the data output buffer.

  In a third aspect, the present invention provides a method for configuring a clock operating mode of a memory device that receives a reference voltage for sensing input data. The method sets a reference voltage level; compares the reference voltage with a preset voltage and generates a mode selection signal corresponding to the reference voltage with respect to the preset reference voltage; and, depending on the mode selection signal, Configuring the clock input buffer to receive either a parallel complementary clock signal or a serial complementary clock signal. In an embodiment of the present aspect, the comparing step includes latching the mode selection signal, and the further comparing step is used to compare the reference voltage with the preset reference voltage after a predetermined delay. Disabling the sensing circuit that is enabled. The predetermined delay is determined by counting 2n clock edges after deasserting the reset signal, and the preset reference voltage floats to the voltage supply while the reset signal is asserted. To do.

  In yet another embodiment of the present aspect, the configuring step includes enabling a comparator that receives the serial complementary clock signal in response to the first logic state of the mode selection signal, and the parallel complementary Including disabling a buffer that receives the clock signal. The enabling step enables a clock synthesizer that generates a first clock signal and a second clock signal that is shifted 180 degrees relative to the first clock signal in response to the sensed clock signal from the comparator. Including that. The step of enabling the clock synthesizer is responsive to the mode selection signal to include a buffered parallel complementary clock signal corresponding to a complementary clock signal in parallel with the first clock signal and the second clock signal. Providing one as an internal clock signal. The clock synthesizer generates a third clock signal and a fourth clock signal, the third clock signal is shifted by 90 degrees with respect to the first clock signal, and the fourth clock signal is the third clock signal. It is shifted 180 degrees with respect to the signal. The configuring step includes selectively passing one of the internal clock signal and the third and fourth clock signals in response to the phase selection signal.

  In a fourth aspect, the present invention provides a memory system that can be configured to operate with one of a parallel clock signal and a serial clock signal. The memory system includes a memory controller and at least one memory device connected in series. At least one memory device includes a clock input port, a reference voltage input port, a mode setter, and a clock switch circuit. The clock input port receives one of a parallel clock signal and a serial clock signal. The reference voltage input port receives a reference voltage set to one of a predetermined power level and a power supply level. The mode setter compares the reference voltage with a predetermined voltage level and issues a mode selection signal corresponding to the comparison result. The clock switch circuit is connected to the clock input port and generates a complementary internal clock signal corresponding to one of the complementary clock signals in series with the parallel clock signal in response to the mode selection signal.

  A memory system that solves many of the performance problems of the flash memory system 10 of FIG. 1 is a serially connected memory system in which the memory devices are connected to each other in a ring topology configuration. Connected in series to the memory controller. 2A and 2B are block diagrams illustrating the conceptual nature of the serial memory system. FIG. 2A is a block diagram of a serial memory system that receives a parallel clock signal, while FIG. 2B is a block diagram of the same serial memory system as FIG. 2A that receives a source-synchronized clock signal.

  In FIG. 2A, the serial memory system 20 includes a memory controller 22 having at least one serial channel output port Sout and a serial channel input port Sin, and memory devices 24, 26, 28 and 30 connected in series. Input and output ports correspond to physical pins or connections that interface the memory device to the system, and the memory device is integrated or integrated into the system. In one embodiment, the memory device can be a flash memory device. Alternatively, the memory device can be a DRAM, SRAM, or other type of memory device, and the memory device can execute a command or pass a specific command structure to pass commands and data to the next memory device. Serial input / output interface compatible with The current example of FIG. 2A includes four memory devices, but other examples can include a single memory device, or any number of memory devices. Thus, if memory device 24 is the first device of serial memory system 100 as connected to Sout, memory device 30 is the Nth or last memory device as connected to Sin. , N is an integer greater than 0. Memory devices 26-28 are therefore serially connected memory devices that are interposed between the first and last memory devices. Each memory device assumes an identification (ID) number or device address (DA) that is identifiable after system power-up initialization, so that they are individually addressable. Co-owned US patent application Ser. No. 11 / 622,828, entitled “IDS Generation Device and Method for Mixed Type Interconnected Devices”, US Patent Application No. 11/750 , 649, title of the invention "device and method for establishing a device identifier for devices interconnected in series", US patent application Ser. No. 11 / 692,452, "title of invention" mixed type serial Device and method for generating device identifiers for devices interconnected with each other ", US Patent Application No. 11 / 692,446", Title of Invention "Identifiers regardless of mixed devices in series interconnects" Apparatus and method for generating ", U.S. patent application Ser. No. 11 / 692,326, Title of Invention" Apparatus and method for identifying apparatus type of serially interconnected apparatus ", U.S. Pat. Application No. 11 / 771,023, entitled “Address Assignment and Type Recognition of Mixed-Type Serially Interconnected Memory Devices”, provides device addresses for serially-connected memory devices in a memory system. The methods that occur are described, all of which are hereby incorporated by reference in their entirety.

  Memory devices 24-30 are considered to be memory devices connected in series, where the data input of one memory device is connected to the data output of the previous memory device, so that This is because a series connection configuration is formed except for the last memory device. The channel of the memory controller 22 contains data, addresses, commands, and control information and is provided by individual pins or the same pin. For example, a data channel with an appropriate data width carries command, data, and address information, while a control channel carries control signal data. The embodiment of FIG. 2A includes one channel, which includes a Sout port and a corresponding Sin port. However, the memory controller 22 can include multiple channels to accommodate individual memory device chains. In the example of FIG. 2A, the memory controller 22 provides a clock signal CLK, which is connected in parallel to all the memory devices.

  In general operation, the memory controller 22 issues a command through the Sout port, and the command includes an operation code (opcode), a device address, address information for reading and writing, and data for a program. The command is issued as a serial bit stream packet, and the packet can be divided into segments of a logically predetermined size, for example, 1 byte. A bitstream is a sequence or sequence of bits provided over time. The command is received by the first memory device 24, which compares the device address with the assigned address. If the addresses match, the memory device 24 executes the command. Otherwise, the command is passed through its own output port to the next memory device 26 where the same procedure is repeated. Eventually, the memory device with the matching device address (hereinafter selected memory device) will perform the operation indicated by the command. If the command reads data, the selected memory device outputs the read data via the output port, and this read data is intervened until it reaches the Sin port of the memory controller 22. Pass through the memory device in series. Since commands and data are provided in a serial bit stream, a clock is used by each memory device to synchronize the operation of the internal memory device and to clock in or out the serial bits. This clock is used by all memory devices in the serial memory system 20.

  The performance of the serial memory system 20 is superior to that of the parallel memory system shown in FIG. The parallel distributed clock lines can provide a relatively relaxed clock frequency, and therefore the memory system 20 can use low voltage CMOS unterminated full amplitude signaling and is robust. Data communication. This is also referred to as LVTTL signaling. For example, assuming a 66 MHz clock is used and the serial memory system 20 includes four memory devices, the data for one of the serially connected memory devices using double data rate (DDR) signaling The rate is approximately 133 Mbps.

  The serial memory system 40 of FIG. 2B is similar to the serial memory system of FIG. 2A except that the clock signal CLK is provided in series to each memory device from an alternative memory controller 42 configured to provide the source synchronous clock signal CLK. Similar to the memory system 20. Each memory device 44, 46, 48 and 50 is configured to receive and transfer a source synchronous clock CLK. In a practical implementation of the serial memory system 40, the clock signal CLK is passed from one memory device to another memory device via a short signal line. Therefore, there are no clock performance issues associated with the parallel clock redistribution scheme, and CLK can operate at high frequencies. Accordingly, the serial memory system 40 can operate at a much higher speed than the serial memory system 20 of FIG. 2A. For example, high speed transceiver logic (HSTL) signaling can be used to provide high performance data communications. In the HSTL signal transmission format, each memory device receives a reference voltage that is used to determine the logic state of the incoming data signal. Another similar signal transmission format is the SSTL signal transmission format. Therefore, the data and clock input circuits of the memory devices of the serial memory systems 20 and 40 are configured differently.

  While high-speed serial memory systems are suitable for newer computing devices, there may be existing computing systems that do not require high-speed operation, but can still benefit from the high memory capacity of serial memory systems. For example, the serial memory system can be modular, as disclosed in co-owned US patent application Ser. No. 11 / 843,440, with additional memory devices extending the total memory capacity. It can be added to the memory system for purposes. On the other hand, replacing an existing slower speed serial memory system with a higher speed memory system may not be cost effective. Therefore, both types of memory devices should be available for upgrade or assembly of both types of serial memory systems. However, those skilled in the art can manufacture two different types of memory devices, one type configured to interface to the memory controller 22 and the other type configured to interface to the memory controller 42. You will understand that it is not cost effective.

  Therefore, a clock mode configuration circuit for a configurable memory device is provided to allow a configurable memory device to be used in both a parallel clocked memory system and a serial clocked memory system. . Such memory systems include configurable memory devices connected in series with each other, each configurable memory device receiving a clock signal. The clock signal can be provided in parallel to all configurable memory devices or in series from one memory device to another memory device via the same clock input. The clock mode configuration circuit in each configurable memory device may be set to a parallel mode that receives a parallel clock signal and set to a serial mode that receives a source synchronous clock signal from a previous memory device or memory controller. Depending on the set operating mode, the data input circuit is configured for the corresponding data signal format and the corresponding clock input circuit is enabled or disabled. The parallel mode and the serial mode are set by sensing the reference voltage level provided to each memory device.

  3A and 3C are block diagrams of a serial memory system using the same type of memory device including an example of a clock mode configuration circuit, details of which will be described later. The memory device of the serial memory system of FIG. 3A receives the clock in series, while the memory device of the serial memory system of FIG. 3C receives the clock in parallel. In the example memory system of FIGS. 3A and 3C, four memory devices are shown, which are connected in series in a ring topology configuration with a memory controller, but any number of memory devices can be connected to any serial memory. Can be included in the system. The serial memory system of FIGS. 3A and 3C illustrates that the same type of memory device can be used in both a parallel clocked system and a serial source-synchronized clocked system. It has a mode configuration circuit.

  In FIG. 3A, the serial memory system 100 includes a memory controller 102 and four memory devices 104, 106, 108 and 110. The memory controller 102 provides control signals to the memory device in parallel. These include a chip enable signal CE # and a reset signal RST #. In one use case of CE #, the memory device is enabled when CE # is at a low logic level. Once the memory device initiates a program or erase operation, CE # is either not asserted or driven to a high logic level. In one use case of RST, the memory device is set to reset mode when RST # is at a low logic level. In reset mode, power is stabilized and the device prepares itself for operation by initializing all finite state machines and resetting the configuration and state registers to default states. The memory controller 102 includes clock output ports CKO # and CKO that provide complementary clock signals CK and CK #, and clock input ports CKI # and CKI that receive complementary clock signals from the last memory device in the system. . Each memory device will include a clock synthesizer, such as a DLL or PLL, to generate the phase of the received clock. A phase will be used to collect clock edges within the input data valid window to ensure reliable operation internally. Each memory device has a clock output port CKO # and CKO for passing a complementary clock signal to the clock input port of the next memory device, and a complementary clock signal from either the memory controller 102 or the previous memory device. Clock input ports CKI and CKI #. The last memory device 110 returns the clock signal to the memory controller 102.

  The channel of the memory controller 102 includes a data channel including a data output port Qn and a data input port Dn, a command strobe input CSI, a command strobe output CSO (CSI echo), a data strobe input DSI, and a data strobe output DSO (DSI Control channel consisting of echo). The output port Qn and the input port Dn can be 1 bit wide or n bit wide depending on the desired configuration, where n is a non-zero integer. For example, if n is 1, 1 byte of data is received after the edge of the clock that latches 8 data. The clock edge for latching data can be, for example, a rising clock edge in single data rate (SDR) operation, and can be, for example, both a rising and falling clock edge in double data rate (DDR) operation. it can. If n is 2, 1 byte of data is received after 4 latching clock edges. If n is 4, one byte of data is received after two latching clock edges. The memory device can be statically or dynamically configured for the width of Qn and Dn. Therefore, in configurations where n is greater than 1, the memory controller provides data in parallel bitstreams. CSI is used to latch command and write data appearing at input port Dn, and CSI has a pulse duration corresponding to the length of the received command data. More specifically, the command and write data have a duration measured by the number of clock cycles, and the pulse duration of the CSI signal has a corresponding duration. The DSI is used to enable the output port Qn buffer to output read data, and the DSI has a pulse duration corresponding to the length of the requested read data.

  The example of FIG. 3A is intended for high-speed operation, and a high-speed signal transmission format such as an HSTL signal transmission format would be used. Thus, a reference voltage VREF is provided to each memory device, which is used by each memory device to determine the logic level of signals received at the Dn, CSI and DSI input ports. The reference voltage VREF can be generated, for example, by another circuit on the printed circuit board, and the reference voltage VREF is set to a voltage level that is determined in advance based on the voltage amplitude of the HSTL signal. For example, VREF can be set to an intermediate voltage at the maximum voltage level of the HSTL signal. According to this embodiment, setting VREF to the aforementioned predetermined voltage level is a first mode of operation in which the input circuit is set to receive an HSTL input signal and an appropriate internal clock circuit is generated. Set the clock mode configuration circuit. The first mode of operation may be referred to as a high speed mode of operation.

  In a practical implementation of the embodiment of FIG. 3A, each memory device is positioned on a printed circuit board such that the distance between the input and output ports and the signal track are minimized. Alternatively, the four memory devices can be implemented in a system in package module (SIP) that further minimizes the length of the signal track. The memory device can also be implemented as a number of SIP modules. The memory controller 102 and the memory devices 104-110 are connected in series to form a ring topology, that is, the last memory device 110 provides an output to the memory controller 102. One skilled in the art should understand that the distance between the memory device 110 and the memory controller 102 is easily minimized.

  FIG. 3B is a timing diagram illustrating a schematic timing relationship between input and output signals for each memory device of the serial memory system 100, and several internal signals are shown as well. In a real system, the delay of the internal gate is assumed to be minimal in this figure, although the significant delay is adjusted and has no functional impact. Signal traces for received input clocks CKI and CKI #, input data Dn, output clocks CKO and CKO #, output data Qn are shown in FIG. 3B, and 90 degrees, 180 degrees, 270 degrees of received input clocks and A 360 degree phase is generated internally. Since each memory device operates at a double data rate, the received data is buffered into an internal single data rate even data stream D_E and an internal single data rate odd data stream D_O. In the example of FIG. 3B, data “A”, “B”, “C”, “D”, and “E” are provided in series on the Dn input of the memory device, each of which is the rising edge of CKI or CKI #. A data input valid window corresponding to the falling edge is provided. In other words, the input data and the clock edge coincide with each other. Data “A”, “C” and “E” are latched on each rising edge of the internal 90 degree clock and provided to the D_E data stream. Data “B” and “D” are latched on each rising edge of the internal 270 degree clock and provided to the D_O data stream. Assuming that the input data received at Dn is simply passed to its Qn output, the double data rate output data Qn is an even number of D_E data latched on each rising edge of the 270 degree clock output and a 90 degree clock. Generated from odd O_D data latched on each rising edge of the output. As shown in FIG. 3B, CKO corresponds to a 270 degree clock output, while CKO # corresponds to a 90 degree clock output.

  In the embodiment of FIG. 3C shown here, each memory device has the same serial input / output interface, which receives RST #, CE #, CKI for receiving corresponding signals from the memory controller 102. Includes # and CKI input ports. The serial input / output interface further includes a data input port Dn, a data output port Qn, and CSI, DSI, CSO, and DSO ports. As shown in FIG. 3C, the Dn, CSI and DSI input ports of each memory device are connected to the Qn, CSO and DSO output ports of the previous memory device, respectively. Thus, the memory devices are considered connected in series so that each can pass commands and read data to the next memory device in the chain.

  In FIG. 3C, the serial memory system 200 includes a memory controller 202 and the same memory devices 104, 106, 108 and 110 as in FIG. 3A. The memory controller 202 is configured to provide the same functionality as the memory controller 102 of FIG. 3A, except that the clock signals are provided in parallel, and therefore the clock output ports CKO # and CKO of each memory device. Is not connected. In addition, the signal transmission format for data and strobe signals will be different, for example, the LVTTL signal transmission format without full swing termination. The LVTTL signaling format at the lower clock frequency does not require the use of the reference voltage VREF, so VREF is set to a voltage level other than the predetermined level used in the embodiment of FIG. 3A. Can do. For example, VREF can be set to either VDD or VSS. According to this embodiment, setting VREF to VSS or a voltage other than the above-described predetermined voltage level sets the clock mode configuration circuit to the second operation mode, and in the second operation mode, The input circuit is configured to receive the LVTTL input signal and a suitable internal clock circuit is generated. The second operation mode can be referred to as a low speed operation mode. Thus, the advantage of using the memory device's existing VREF input to set the operating mode of the clock mode configuration circuit is that no additional pins and corresponding logic are required in the memory controller to configure the memory device. It is. Each memory device configures itself based on the voltage level of VREF, thus reducing the design cost of the memory controller. Furthermore, the same clock input ports CKI and CKI # can receive either a parallel clock signal or a serial clock signal, which minimizes the number of pins of the memory device.

  FIG. 3D is a timing diagram illustrating a schematic timing relationship between input signals and output signals of each memory device of the serial memory system 200, and some internal signals are also shown. In an actual system, large delays are adjusted and do not affect functionality, but in this figure it is assumed that internal gate delays are minimal. A signal trace of the received input clocks CKI and CKI #, input data Dn, and output data Qn is shown in FIG. 3D. The memory device does not have an internal clock synthesizer and the output clocks CKO and CKO # are not provided. Each memory device operates at a double data rate, so received data is buffered into a single data rate even data stream D_E and a single data rate odd data stream D_O. In the example of FIG. 3D, data “A”, “B”, “C”, “D”, and “E” are provided in series to the Dn input of the memory device, and the rising and falling edges of CKI and CKI # Are collected at the center of each data entry valid window. In this example, internal read data “Ci” and “Di” are provided to the output circuit of the memory device via RD_E and RD_O in response to a read command received by the memory device. Thus, there are an even output data stream Q_E and an odd output data stream Q_O that provide either internal read data from RD_E and RD_O or external data from D_E and D_O to the Qn output. More specifically, data from RD_E and RD_O is provided to Q_E and Q_O in response to high logic level enable signals EN_E and EN_O.

  Data “A”, “C” and “E” are latched on each rising edge of CKI and provided to the D_E data stream. Data “B” and “D” are latched on each rising edge of CKI # and provided to the D_O data stream. While EN_E and EN_O are at an inactive low logic level, data “A” and “B” are latched on the rising edges of CKI and CKI # and provided to D_E and D_O, respectively. On the rising edge of CKI #, data “A” on D_E is latched and provided to Q_E, while data “B” on D_O is latched on the rising edge of CKI and provided to Q_O. Data "A" and "B" are then provided to the Qn output on the rising edges of CKI # and CKI, respectively. When EN_E is high, RD_E data “Ci” is latched and provided on Q_E on the rising edge of CKI #. Thereafter, while EN_O is high, RD_O data “Di” is latched and provided on Q_O on the rising edge of CKI. Data “Ci” and “Di” are then provided to the Qn output on the rising edges of CKI # and CKI, respectively. When EN_E and EN_O drop to a low logic level, external data “E” is latched on Q_E and passed on Qn. The delay through the output path of the device, the internal connection to the next device, and the input path of the next device shifted the Qn data stream so that the rising edge of the next device's CKI was received. The falling edge of CKI # of the next device falls in Dn data stream bits A, Ci and E and falls in the received Dn data stream bits B and Di. One skilled in the art will be sure that the delay from serial output Qn to serial input Dn is less than half the clock period.

  According to this embodiment, memory devices 104, 106, 108 and 110 can be any type of memory device having a serial input / output interface designed to be serially interconnected with other memory devices. While the memory devices 104, 106, 108 and 110 can be implemented as flash memory devices, the memory devices are DRAM, SRAM, or other suitable type of volatile or non-volatile memory device. There can also be. More specifically, other memory types can be adapted to operate with a serial input / output interface and configured to receive an LVTTL input signal or an HSTL input signal.

  FIG. 4 is a block diagram illustrating a conceptual configuration of a schematic memory device having a native core and a serial input / output interface suitable for use with the serial memory system of FIGS. 3A and 3C. Memory device 300 includes a native memory core, which includes memory array banks 302 and 304 and native control and I / O circuitry 306 that accesses memory array banks 302 and 304. One skilled in the art will appreciate that the memory array can be configured as a single memory bank or more than two memory banks. The native memory core can be based on, for example, DRAM, SRAM, NAND flash, or NOR flash memory. Of course, a suitable new memory and its corresponding control circuit can be used. Thus, depending on the type of native memory core, circuit block 306 includes error correction logic, high voltage generator, refresh logic, and other circuit blocks required to perform memory type specific operations. Can do.

  Typically, a memory device uses a command decoder that initializes the associated circuitry in response to a command received by asserting an internal control signal. The memory device also includes well known I / O circuitry that receives and latches data, commands and addresses. According to this embodiment, the existing I / O circuit is replaced with a serial interface and control logic block 308. In this example, the serial interface and control logic block 308 receives RST #, CE #, CK #, CK, CSI, DSI, and Dn inputs and provides Qn, CSO, DSO, CKO, and CKO # outputs.

  The serial interface and control logic block 308 is responsible for various functions, which are described in US patent application Ser. No. 11 / 324,023. The exemplary functions of the serial interface and control logic block 308 are to set a device identification number, pass data to the next serially connected memory device, and decode received commands to perform native operations Including doing. This circuit is configured to receive commands serially and may be configured to include additional commands specific to the serial operation of the memory device in addition to the specific existing native commands that control the core circuit. When memory devices are connected in series, the command set can be extended to implement features usable by the memory controller. For example, status register information may be requested to evaluate the status of the memory device.

  Therefore, the serial memory devices of FIGS. 3A and 3C can include a mix of multiple memory device types, each providing various advantages for larger systems. Further details of these configurations can be found in commonly owned US patent application Ser. No. 11 / 771,023, entitled “Address Assignment and Type Recognition of Mixed Type Series Interconnected Memory Devices” (ADDRESS). ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE) and jointly owned US Patent Application No. 11 / 771,241; SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE), the contents of which are hereby incorporated by reference. For example, high speed DRAM memory can be used to cache operations, while non-volatile flash memory can be used for low power mass data storage. Regardless of the type of memory device used, each memory device is individually addressable to operate with commands, and the serial interface and control logic block 308 is configured to receive commands according to a predetermined protocol. This is because that. According to one embodiment, the aforementioned clock mode configuration circuit is implemented within the serial interface and control logic block 308.

  FIG. 5 is a block diagram illustrating a clock mode configuration circuit according to one embodiment, which generates signals to be used by a configurable input / output buffer example. Both clock mode configuration circuitry and configurable input buffers can be used in the serial interface and control logic block 308 described above. The clock mode configuration circuit includes a mode setter 400 and a clock switch circuit 402. The mode setter 400 generates a mode signal MODE having either a high logic level or a low logic level in response to the voltage level of the reference voltage VREF. As described above, VREF is used by the memory device to determine the logic level of the high speed input signal, as when using the HSTL signal transmission format. In this embodiment, VREF is set to a predetermined voltage level between a high voltage supply level and a low voltage supply level, such as VDD / 2 for HSTL signal transmission. If a slower input signal can be used, such as when using the LVTTL signaling format, the VREF voltage is not required and the VREF pin will be at either the supply voltage level VDD or VSS. Can be connected. From this point, the HSTL and LVTTL signal transmission formats are used to describe the operation of this embodiment, and VREF is set to VSS when the memory device can receive the LVTTL signal. The clock switch circuit 402 is responsible for enabling the generation of an internal clock signal based on one of the parallel clock source or the source synchronous serial clock signal in response to the mode signal MODE provided by the mode setter 400. Further description of the configuration of the clock switch circuit 402 will be described later.

  The configurable input / output buffer of FIG. 5 is implemented as a configurable data input / output buffer 404 that senses an HSTL or LVTTL input signal and outputs a received input signal or internal data from a memory device. Pass to port Qn. The configurable data input / output buffer 404 uses the internally generated clock signal provided by the clock switch circuit 402 to maintain synchronized operation according to the selected input signal transmission format. Although only one configurable input / output buffer is shown in FIG. 5, those skilled in the art will recognize that there is one configurable input / output buffer for the input signals DSI and CSI as well. You will understand.

  In this exemplary embodiment, the predetermined voltage VREF is typically VDD / 2, corresponding to serial clock mode operation, while the VSS voltage level VREF corresponds to parallel clock mode operation. . That is, during assembly of the memory system, if each memory device receives a clock signal as in FIG. 3A in series, VREF is set to a predetermined voltage level. Therefore, the HSTL signal transmission format will be used. On the other hand, if each memory device receives the clock signal in parallel as in FIG. 3C, VREF is set to VSS. In that case, the LVTTL signaling format would be used instead. Therefore, VREF is sensed by mode setter 400 and causes signal MODE to be set to a first logic state corresponding to serial clock mode operation or to a second logic state corresponding to parallel clock mode operation.

  Turning again to the clock switch circuit 402 with an understanding of the MODE signal, the clock switch circuit 402 includes a clock input buffer 406, a clock generator 408, and a clock output buffer 410. Clock input buffer 406 is connected to clock input ports CK and CK # and is either a single-ended clock signal based on two differential clock inputs CK and CK # or individually buffered in response to the logic state of mode signal MODE. Generated CK and CK # versions. For example, a single-ended clock signal is generated when MODE is in a first logic state. Clock generator 408 receives either a single-ended clock signal or buffered versions of CK and CK # and uses two internal clocks that are used for internal operation and to generate appropriate output timing. Provides phase. Internal clock signals CKI and CKI # are distributed to input / output buffers configurable with the internal circuitry of the memory device. Clock output buffer 410 receives internal clock signals CKI and CKI # and drives them through the CKO and CKO # output ports when MODE is in the first logic state. When the MODE is in the second logic state corresponding to parallel mode operation, the clock output buffer 410 is disabled because it is not necessary to provide a serial clock to the next memory device.

  The configurable data input / output buffer 404 includes a data input buffer 412, a data switch 414, and a data output buffer 416. Data input buffer 412 receives input data Dn and reference voltage VREF, which is used when MODE is at the first logic level. The buffered input signal Din is then provided to the data switch 414, which passes either Din or native data from the memory device to the data output buffer 416. The native data in this example includes even data RD_e and odd data RD_o. This is because data is provided on both the rising and falling edges of the clock signal. Signals EN_o and EN_e are used to select either Din or RD_e and RD_o and pass them to data output buffer 416. Furthermore, it should be noted that the serial data Dn is provided on both the rising and falling edges of the clock signal. The choice of which data to pass depends on the command received by the memory device. In any case, the data is synchronized with the internal clock signals CKI and CKI # and transmitted to the data output buffer as even data Dout_e and odd data Dout_o, respectively. The data output buffer 416 interleaves the bit data of Dout_e and Dout_o in response to the clock and drives it through the Qn data output port.

  An advantage provided by the clock mode configuration circuit of FIG. 5 is that no additional package pins are required because VREF is used for two different purposes. If each memory device is packaged individually, the package size is minimized by reducing the number of pins required. One skilled in the art will appreciate that smaller package sizes with integrated or integrated memory systems minimize the required printed circuit board area. Alternatively, the memory devices of the serial memory system shown in FIGS. 3A and 3C can be packaged together like a system in package (SIP). Again, the reduced number of pins minimizes package size. The mode setter 400 connected to the VREF input port provides such an effect. A further advantage is that a single memory component can operate accurately in a high performance source synchronous clock configuration and in a lower performance parallel clock configuration with reduced power consumption, as described in more detail below. It is.

  FIG. 6 is a circuit diagram of a mode setter 400 according to one embodiment. The mode setter 400 senses the voltage level of VREF and drives the signal MODE to either the first logic level or the second logic level. In this particular example, the first and second logic levels can correspond to VDD and VSS, respectively. Mode setter 400 includes a sensing circuit 500, a latch 502, and a digital delay circuit 504. The sensing circuit 500 includes resistance elements 506 and 508, a power cutoff device 510 connected in series between VDD and VSS, and a comparator 512. In this example, power interrupt device 510 is implemented as an n-channel transistor having a gate terminal that receives enable signal EN. The shared terminal of the resistive elements 506 and 508 is connected to one input of the comparator 512, and the second input of the comparator 512 receives the reference voltage VREF. Resistive elements 506 and 508 form a reference voltage circuit. The ratio of the resistive elements 506 and 508 can be set depending on the value of VREF to be detected. For example, if the stable voltage level of VREF is VDD / 2, the resistive element 506 can be set to 3R, while the resistive element 508 can be set to R. Thus, the shared terminal “x” will be approximately VDD / 4. Comparator 512 can be implemented by any known circuit, and in this example, comparator 512 includes an optional enable input that receives enable signal EN.

  The latch 502 can be implemented by a known circuit, and in this example, the latch 502 optionally receives an enable signal EN. When the latch enable input is high, the signal appearing at the D input is provided to the Q output. When the latch enable input transitions from high to low, the state of the D input is latched and provided to the output Q. Digital delay circuit 504 includes a counter 514, a NOR logic gate 516, and an inverter 518. Counter 514 is an n-bit counter, where n is an integer greater than 1, and counter 514 has only the most significant bit (MSB) output connected to the input of inverter 518. The counter is reset, that is, when RST # is at a low logic level, all bits including the MSB output are set to 0 (VSS). The MSB is also connected to one input of NOR logic gate 516, while the other input receives a clock signal CK. Therefore, when reset, the MSB is at VSS in this example. When RST # is set high and released, the counter is allowed to increment the count on each rising or falling edge of clock CK. When the MSB is switched to 1 (VDD), the power shutoff device 510 is turned off via the inverter 518, the comparator 512 is turned off to save power, the MODE output is latched, and the counter 514 clock The input is disabled through the NOR gate, causing the counter 514 to freeze. After the delay provided by the counter, MODE is stably set to either VDD or VSS.

  The operation of the mode setter 400 will be described with reference to the sequence diagram of FIG. At time t1, RST # is at VDD and counter 514 drives the MSB to VDD. EN is then driven to VSS by inverter 518, which turns off power shutoff device 510 and causes node "x" to float to VDD. The advantage of allowing node “x” to float to VDD while the circuit is disabled is that MODE immediately defaults to VSS when comparator 512 and latch 502 are enabled, regardless of the value of VREF. This is because node “x” is always greater than VREF. This immediately sets the memory device to parallel clock mode operation and normal memory operation can be started without delay. At time t2, RST # is pulsed to VSS, resetting the MSB to VSS. RST # returns high, releases the counter 514, counts a predetermined number of edges of the clock signal CK, calms down the level on the VREF pin and corrects it even if the low-level pulse on RST # is short Give the analog portion of the circuit enough time to make a decision. When MSB drops to VSS, EN is driven to VDD by an inverter, enabling the resistor divider, comparator 512, and latch 502, evaluating the level of the VREF pin, and determining the MODE of operation. Since node “x” is currently floating to VDD, enabled comparator 512 drives a low logic output, which is sent to latch 502 to set MODE to a low logic level.

  In this example, it is assumed that VREF is configured to be approximately VDD / 2, and the ratio of resistance elements 506/508 is configured to be 3R / R. While the circuit is enabled, the voltage at node “x” will therefore settle to a level of approximately VDD / 4. Eventually, the voltage at node “x” will be fixed at a stable VDD / 4 level, as shown at time t3 in FIG. If VREF is set to VSS, the comparator 512 is not changed and MODE is maintained at VSS. On the other hand, if VREF is set to VDD / 2, comparator 512 drives its output to VDD, which causes latch 502 to drive MODE to VDD around time 3. Finally, the counter 514 sets MSB to VDD and drives EN to VSS at time t4. The MSB at VDD causes the NOR logic gate 516 to output a low logic level signal, effectively terminating the counting by the counter 514, thereby “freezing” the counter 514. Once EN falls to VSS, the power interrupt device 510 is turned off and the node “x” eventually floats to VDD. However, EN at VSS now disables comparator 512 and latch 502 is prevented from latching any changing output signal on the D input. Therefore, power is saved by turning off the sensing circuit 500. In operation in source synchronous mode, normal memory operation can only be started after PLL or DLL synchronization. This time is not wasted because the voltage at node “x” settles to the correct value during synchronization.

  Therefore, the time delay corresponding to the time of counter 514 to switch the MSB to VDD is long enough to ensure that node “x” and VREF are stabilized to be sensed by comparator 512. . As an example, a 1 ms time delay can be a sufficient time delay provided by the digital delay circuit 504. Therefore, by turning off the power shut-off device 510 after the MSB has been switched to VDD, the current path from VDD to the VSS via the resistance elements 506 and 508 is cut off, so that during operation of the memory device Save power. This time delay can be selected based on a given clock frequency and the number of bits in the counter 514.

  FIG. 8A is a circuit example of the clock switch circuit 402 and configurable data input / output buffer 404 of FIG. Both circuits can be referred to as configurable input circuits because one receives an input clock and the other receives input data from at least one input data port. The clock switch circuit 402 can be configured to operate in a parallel or serial clock mode in response to the logic state of the mode signal MODE, while the configurable data input / output buffer 404 has a logic level of MODE. In response to the condition, it can be configured to receive input data in either HSTL or LVTTL signaling format. It should be noted that the Dn input can receive both write data and commands from the memory controller. To simplify the circuit diagram of FIG. 8A, the command data path and the input write data path are not shown. The same reference numbers in FIG. 8A are generally described in FIG.

  Details of the clock switch circuit 402 are as follows. The clock input buffer 406 includes a comparator 700 that receives complementary clock signals from the clock input ports CKI and CKI #, a first buffer circuit 702 that receives a clock signal from the clock input port CKI, and a complementary clock from the clock input port CKI #. And a second buffer circuit 704 for receiving the signal. Comparator 700 is enabled by one state of MODE, while both first and second buffers 702, 704 are enabled by the opposite state of MODE. Thus, only one of comparator 700 and buffers 702 and 704 will be activated in any signal logic state of MODE. However, the outputs of comparator 700 and buffers 702 and 704 are coupled in parallel to clock generator 408. In the embodiment described herein, mode setter 400 sets MODE to a first logic state corresponding to serial clock mode operation as well as to a second logic state corresponding to parallel clock mode operation. The MODE in the first logic state enables the comparator 700. Thus, the second logic state MODE enables the first and second buffers 702, 704.

  Clock generator 408 includes a phase locked loop (PLL) 706 that is enabled when MODE is in the first logic state. When enabled, the PLL circuit 706 generates a clock output that is shifted by 90 degrees, 180 degrees, 270 degrees, and 360 degrees with respect to the clock signal received at the REF input, and the REF input is connected to the comparator 700. Connected to output. These shifted clock outputs are provided from terminals labeled 90, 180, 270, 360. In serial clock mode operation, the received input clock transition and the received input data transition occur simultaneously. The PLL circuit 706 is used to place the edge of the internal clock signal within the input data valid window for reliable data acquisition. The feedback input FB receives the clock output shifted 360 degrees to facilitate clock signal locking. Those skilled in the art will be familiar with the operation of the PLL circuit and the clock will be locked after several clock cycles to ensure stable operation. Instead of a PLL, a delay locked loop (DLL) circuit can be used in place of the PLL circuit 706. Both PLL and DLL are examples of clock synthesizers and can be used in the embodiments disclosed herein. The 90 degree and 270 degree clock outputs are provided to the first inputs of 2-1 multiplexers 708 and 710, both of which are controlled by MODE. The second inputs of multiplexers 708 and 710 receive the outputs of buffer 702 and buffer 704, respectively. In parallel clock mode operation, the received input clock transitions are within the input data valid window so that no phase-shifted clock is required. Therefore, multiplexers 708 and 708 collectively form a switch circuit and, in response to MODE, 90 degree and 270 degree clock outputs from PLL circuit 706 and buffered clock signals from buffers 702 and 704. Is selectively passed. In this embodiment, when MODE is at the first logic level, PLL circuit 706 is enabled and multiplexers 708 and 710 pass the 90 degree and 270 degree clock outputs as internal clock signals CK and CK #. To be controlled. On the other hand, when MODE is at the second logic level, PLL circuit 706 is disabled and multiplexers 708 and 710 pass the clock signals from buffers 702 and 704 as internal clock signals CK and CK #. Be controlled. Therefore, turning off an unused PLL reduces power consumption.

  Although not explicitly shown in FIG. 8A, complementary internal clock signals CK and CK # are distributed to other circuits in the memory device. An optional feature of clock generator 408 is a phase selection circuit that includes multiplexers 712 and 714. The first inputs of multiplexers 712 and 714 receive internal clock signals CK # and CK, respectively, while the second input receives 360 degree and 180 degree clock outputs from PLL circuit 706. Both multiplexers 712 and 714 are controlled by signal PHASE, which is provided by the command decoder of the memory device. The purpose of the phase selection circuit is to collect the output clock signals provided to the output ports CKO and CKO # along with the output data provided to the output port Qn. In memory systems connected in series, this feature is enabled in the last memory device of the system. The advantage is that the memory controller design can be simplified because no PLL or DLL is required to reliably receive data from the last memory device in the ring. Further details of the application of this feature of the memory system are described below. Clock output buffer 410 includes a pair of drivers 716 and 718 and drives the clock signal provided by multiplexers 712 and 714 to output ports CKO and CKO #. Both drivers 716 and 718 are enabled by MODE when MODE is at a first logic level representing, for example, a serial clock mode.

  Therefore, in response to MODE, the clock switch circuit 402 is configured to generate an internal clock signal corresponding to a source synchronous clock signal provided in series or a parallel clock signal. Since the memory device operates at high speed in response to a high speed source synchronous clock signal, this mode may be referred to as high speed mode operation. On the other hand, since the parallel clock signal is at a lower frequency than the source synchronous clock, this mode is referred to as low power mode operation, circuits such as comparator 700, PLL 706, and drivers 716 and 718 are turned off, and more Low frequency operation reduces overall power consumption compared to when the memory device operates at a high frequency. In either mode of operation, the internal clock signals CK and CK # are generated by other circuits of the memory device such as a configurable data input / output buffer comprising a data input buffer 412, a data switch 414, and a data output buffer 416. Generated for use.

  The data input buffer 412 includes a comparator 720, a buffer circuit 722, and a data input selector 724, which is implemented as a 2-1 multiplexer. Comparator 720 has one input connected to input port Dn and a second input connected to reference voltage input port VREF. A buffer circuit 722 is also connected to the input port Dn. Comparator 720 generates a logic output corresponding to the voltage level of Dn with respect to VREF, while buffer circuit 722 drives the logic level corresponding to what it receives. All three circuits are controlled by MODE, and in the example described here, the first logic level MODE corresponds to fast mode operation, comparator 720 is enabled, buffer 722 is disabled, The data input selector 724 is controlled to pass the output of the comparator 720. The output of the data input selector 724 is hereinafter referred to as Din.

  Since the memory devices of this embodiment are connected in series with each other, external data arriving at the Dn input port can be selectively transferred or passed to the designated or addressed memory device via the memory device. . However, each memory device can also provide local read data to be transferred to the memory controller via an intervening memory device. The purpose of the data switch 414 is to selectively pass either external Dn data or local read data to the output port Qn. Data switch 414 includes external data input latches 726 and 728, data output selectors 730 and 732, and output latches 734 and 736. In this embodiment, data is latched at both edges of the internal clock CK. Therefore, latches 726 and 728 receive CK and CK #, respectively. The data output selector 730 passes one of the latched external data from the data input latch 726 or the local even read data RD_e in response to the selection signal EN_e. Similarly, data output selector 732 passes one of latched external data from data input latch 728 or local odd read data RD_o in response to select signal EN_o. The select signals EN_e and EN_o are provided by the command decoder of the memory device.

  Data output latches 734 and 736 latch the outputs of output selectors 730 and 732, respectively, in response to the active edges of internal clock signals CK # and CK. The operation of the data switch 414 is well understood by those skilled in the art who are familiar with double data rate operation. Data output buffer 416 includes a data output selector 738 implemented as a 2-1 multiplexer and a driver 740. Data output selector 738 alternately passes the outputs of data output latches 734 and 736 in response to CK, which is then provided by driver 740 to output port Qn. In summary, when MODE is set, the data input buffer 412 is automatically configured to receive the corresponding data signal format and the appropriate internal clock signal is available for use by the data switch 414 and the data output buffer 416. Are automatically generated by the clock switch circuit 402.

  Therefore, the same memory device connected in series in a ring topology with a memory controller is responsive to a reference voltage used to sense the data signal voltage level, as shown in FIGS. 3A and 3C. , Can be configured to receive either a parallel clock or a serial source synchronous clock. Furthermore, the data input circuit is automatically configured to receive a data signal having a signal transmission format corresponding to the parallel clock and the source synchronous clock. Although not shown in the figure, the output buffer drive strength can also be configured based on MODE settings, optimizing performance and power in multidrop bus and point-to-point ring topologies.

  As described above, each memory device can include any phase selection circuit including multiplexers 712 and 714 shown in FIG. 8A. For example, for use with the memory system of FIG. 3A, only the last memory device 110 will have a PHASE set to a logic level that allows the 180 degree and 360 degree clock outputs from the PLL 706 to pass through. For example, all memory devices except the last memory device in the ring output 90 degree and 270 degree clocks, which are the same clocks used to generate output data transitions. . Therefore, the output clock edge and the output data edge occur simultaneously and are fully compatible with the input sampling stage of the next memory device. If the controller does not have a PLL or DLL to shift the input clock edge to the middle of the input data valid window, the PHASE bit provides an output clock transition already located in the middle of the data valid window. So that the controller can directly sample the received data with the received clock signal. In the present example, these would be 180 degree and 360 degree clock outputs. The signal PHASE can be set by loading a single bit register from a command received by the memory device. This will be set during the power up sequence of the memory system, which will start with the memory controller 202 executing the algorithm that assigns addresses to each memory device. Such algorithms include those that generate ID numbers for memory devices in the memory system disclosed in the above-mentioned shared US patent application.

  During ID number assignment, all memory devices have a PHASE bit set to output simultaneous clock and data edges. For example, in this embodiment, this can correspond to the PHASE default state, which is the output of 90 degree and 180 degree clocks. If the memory controller does not have a PLL or DLL, it will not be able to receive data properly until the PHASE of the last memory device is properly programmed. However, until the device address is assigned, the device will not output any data transitions, so the memory controller will recognize the transition on the data input as an indication that the last memory device has been programmed with the device address. . Once the last memory device in the system is recognized by the memory controller, the command is used to set the single bit register described above that changes the PHASE default state to a state that allows the 180 degree and 360 degree clock outputs to pass. publish. After this setting takes effect, full communication of the ring can occur.

  FIG. 8B is a timing diagram illustrating the operation of the circuit of FIG. 8A. In particular, the timing diagram of FIG. 8B shows internally generated clock signals in response to various settings of MODE and PHASE during a continuous sequence of CKI and CKI # clock transitions. At the same time, virtual data on the Qn output port is shown, contrasting the timing difference for the output data valid window in response to the different logic levels of MODE and PHASE. This timing diagram is merely illustrative of the operation of the circuit of FIG. 8A. One skilled in the art will appreciate that data is not provided in close proximity to MODE and PHASE transitions in actual use. The dynamic transition of MODE and PHASE will be performed during the initialization or reset period of the memory system. FIG. 8B includes MODE, PHASE, CKI and CKI #, internally generated 90 degree, 180 degree, 270 degree, 360 degree clock signal from clock synthesizer, CK and CK #, CKO and CKO # traces .

  During the time period between times t1 and t2, the circuit is operating in parallel clock mode when MODE is at a low logic level. Since MODE is at a low logic level, PLL circuit 706 is turned off, resulting in the 90, 180, 270, and 360 degree clock outputs being set to a low logic level. Therefore, the internal clocks CK and CK # are buffered versions of CKI and CKI #, respectively. When using the circuit shown in FIG. 8A, the data transfer operation between input Dn (not shown) and Qn is performed in response to CK and CK # instead of the latch operation responding directly to CKI and CKI #. Except follow the same sequence as shown in FIG. 3D. Due to the low logic level MODE, the clock output buffer 410 is disabled and maintains the low logic level CKO and CKO #.

  During the time period between times t2 and t4, the circuit is operating in serial clock mode when MODE is at a high logic level. Since MODE is at a high logic level, PLL circuit 706 is turned on and generates 90 degree, 180 degree, 270 degree and 360 degree clock outputs. The current timing diagram assumes that mode reset and PLL locking are immediate. In a high logic level MODE, the internal clocks CK and CK # correspond to 90 ° and 270 ° clock outputs and the clock output buffer 410 is enabled to drive CKO and CKO # with the CK and CK # clocks. When using the circuit shown in FIG. 8A, the data transfer operation between input Dn (not shown) and Qn does not cause the latch operation to respond directly to the 90 degree and 270 degree clock outputs. Instead of responding to CK and CK # instead, the same sequence as shown in FIG. 3B is followed.

  At time t3, PHASE goes to a high logic level, but in actual use, PHASE is set to either a high logic level or a low logic level prior to normal operation of the memory operation. The transitions shown in FIG. 8B simply contrast the relationship between the rising and falling edges of CKO and CKO # for Qn output data between different logic levels of PHASE. With PHASE set to a high logic level, multiplexers 712 and 714 pass the 180 ° and 360 ° clock outputs to clock output buffer 410. Therefore, CKO and CKO # correspond to clock outputs of 180 degrees and 360 degrees, thereby collecting clock edges in the data valid window.

  The system embodiments of FIGS. 3A and 3C are static, i.e., once manufactured or assembled for use, they cannot be modified. According to other embodiments, the memory system can be dynamically modified so that the memory device receives either a parallel clock or a serial source synchronous clock. FIG. 9 is an example of a dynamically configurable serial memory device, where the memory controller provides a data signal in a signal transmission format corresponding to both the parallel clock and the source synchronous clock and the clock type. . The memory device includes the same circuitry as represented in FIG. 8A with minor modifications to receive both the parallel clock signal and the source synchronous clock signal.

  In FIG. 9, configurable serial memory system 800 includes a memory controller 802 and four dynamically configurable memory devices 804, 806, 808 and 810. The memory controller 802 provides the same control and data signals as the memory controllers 102 and 202, but here the memory controller 802 includes a parallel complementary clock and a clock via clock output ports CK1 and CK1 #. Complementary source synchronous clocks are provided via output ports CK2 and CK2 #. The memory controller 802 further dynamically provides data and strobe signals in a signal transmission format corresponding to the parallel clock and another signal transmission format corresponding to the source synchronous clock via the Qn, CSO and DSO output ports. Configured. For example, LVTTL signaling can be used with a parallel clock, while HSTL signaling can be used with a source synchronous clock. The memory controller 802 further includes serial clock input ports CKI and CKI # for receiving a source synchronous clock from the last memory device. Each memory device is configured similarly to the memory device shown in FIGS. 3A and 3C, except that each memory device includes parallel input clock ports CK1 and CK1 # and serial input clock ports CKI and CKI #. Depending on the level of VREF, each memory device selectively uses either a parallel clock or a source synchronous clock.

  FIG. 10 is a diagram showing details of the clock switch circuit 402 according to another embodiment. This clock switch circuit shows a modification to the clock switch circuit shown in FIG. 8A, and the same configuration shares the same reference number. The only difference from the embodiment of FIG. 8A is that the clock input buffer 406 includes a comparator 900, a first buffer circuit 902 that replaces the comparator 700, the first buffer circuit 702, and the second buffer circuit 704 of FIG. The second buffer circuit 904 is included. Comparator 900 has inputs connected to clock input ports CKI and CKI # that are directed to receive complementary source synchronous clock signals. The first buffer circuit 902 and the second buffer circuit 904 are connected to clock input ports CK1 # and CK1 that are directed to receive complementary parallel clock signals. Each memory device can be physically connected to both the parallel clock and the source synchronous clock simultaneously. The voltage level of VREF determines which clock input should be used. In the memory system embodiments of FIGS. 9 and 10, VREF can be controlled by a memory controller or can be controlled to drive VREF to a predetermined voltage level or any supply voltage. It can be controlled by a suitable circuit separated from the memory controller. Therefore, the memory systems illustrated in FIGS. 9 and 10 are dynamically switched and operated with a source synchronous clock for high speed operation or a parallel clock where low power consumption operation is desired.

  FIG. 11 is a flow chart summarizing a general algorithm executed by both the memory controller and the memory device of the memory system shown in FIGS. 3A, 3C and 9 for setting the operation mode. The method begins at step 1000 where the memory system is powered up or reset by asserting a reset signal RST #. In step 1002, the memory controller executes a startup algorithm, such as an algorithm for assigning device ID numbers to each memory device in the memory system. Upon power-up or reset, VREF is set to the power supply voltage or a predetermined voltage level. One skilled in the art will appreciate that other startup algorithms can be executed by the memory controller and the memory device itself. Each memory device then senses the level of VREF at step 1004 via each clock input buffer, such as clock input buffer 406 shown in FIG. 8A. Then, at step 1006, the level of VREF is determined, and if it is not a reference voltage, it should be either VDD or VSS voltage supply, and MODE is the first logic in step 1008. Set to level. Otherwise, VREF is a predetermined reference voltage level and MODE is set to the second logic level in step 1010.

  Once MODE has been set, all memory devices are configured with a clock switch circuit and configurable data input / output buffer, such as clock switch circuit 402 and configurable data input / output buffer 404, at step 1012 as described above. Configure automatically. When the memory device is configured to receive a clock and data signal corresponding to MODE, as an optional step, the memory controller may issue a command to switch the PHASE of the last memory device from a default value to an active level. it can. Referring to FIG. 8A, the default value of PHASE at memory device startup or reset can be a low logic level to pass CKI and CKI #, while the active values are 180 degrees and 360 of PLL 706. Can be VDD to send the clock output.

  Some of the embodiments described above are for serial memory devices, but they can be applied to any semiconductor device that operates with clocks provided in parallel or in series.

  In the above description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of embodiments of the invention. However, it will be apparent to one skilled in the art that all the detailed descriptions are not required in order to practice the embodiments of the invention instead of the specific embodiments of the invention. In some instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as software routines, hardware circuits, firmware, or combinations thereof.

  Adaptations and modifications of the described embodiments can be made. Therefore, the above embodiments are considered to be illustrative and not limiting.

Claims (11)

a. A mode selection circuit for providing a mode selection signal;
b. A clock input terminal for receiving a clock input signal;
c. A clock output terminal for providing a clock output signal;
d. A data output terminal for providing a read data output signal;
e. A circuit including an input buffer connected to the clock input terminal and providing a buffered clock input signal;
f. An output latch for latching internal read data at the edge of the buffered clock input signal;
g. A data output buffer circuit connected to the data output terminal, the data output buffer circuit connected to the output latch so that the data output terminal can provide the read data output signal; and
h. Functionally coupled to the buffered clock input signal and enabled to provide a source-synchronized clock output signal while read data is provided to the data output terminal by the mode selection signal in a high speed mode of operation. And a clock output buffer circuit disabled by the mode selection signal in a low speed operation mode.   The memory device according to claim 1, wherein the data output buffer circuit is capable of setting a driving strength.   The memory device according to claim 1, wherein the data output buffer circuit is capable of setting a driving strength by the mode selection signal.   The memory device of claim 1, further comprising a data input terminal for receiving command and address information, wherein the data output buffer circuit can provide the command and address information to the data output terminal.   The memory device of claim 1, wherein the circuit includes a delay locked loop connected to the input buffer and providing a phase shifted buffered clock input signal.   The memory device of claim 1, wherein the read data output signal is a double data rate signal.   The memory device according to claim 1, wherein the read data output signal and the clock output signal are SSTL signals in the high-speed operation mode.   The memory device according to claim 1, wherein the read data output signal and the clock output signal are HSTL signals in the high-speed operation mode.   The memory device of claim 1, wherein the read data output signal is an LVTTL signal in the low speed operation mode.   2. The memory device of claim 1, wherein the read data output signal is a low voltage CMOS signal that is not terminated in the low speed operation mode.   The memory device of claim 1, wherein the clock output buffer circuit provides the buffered clock input signal to the clock output terminal in the high speed operation mode.

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