JP4846144B2 - Synchronous semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous semiconductor memory device, and more particularly to a circuit configuration of an input buffer circuit of a synchronous semiconductor memory device that takes in an external signal in synchronization with a clock signal periodically applied from the outside.
[0002]
[Prior art]
Although dynamic random access memory (hereinafter referred to as DRAM) used as main memory has been speeded up, its operation speed still cannot follow the operation speed of the microprocessor (MPU). For this reason, the access time and cycle time of the DRAM become a bottleneck, and there is a possibility that the performance of the entire system is deteriorated. Therefore, in recent years, a double data rate SDRAM (hereinafter referred to as DDR-SDRAM) that operates in synchronization with a complementary clock signal has been proposed as a main memory for a high-speed MPU.
[0003]
In the DDR-SDRAM, a complementary external clock signal ext. CLK and ext. In general, a specification for high-speed access to continuous bits in synchronization with / CLK is common.
[0004]
FIG. 11 is a timing chart showing a continuous access operation in a general DDR-SDRAM.
[0005]
FIG. 11 shows, as an example, an operation of sequentially writing or reading 4-bit data at each data terminal. The number of bits of data read continuously is called a burst length, and in DDR-SDRAM, the burst length is adjusted by a mode register.
[0006]
In the DDR-SDRAM, an external clock signal ext. A row address strobe signal / RAS, a column address strobe signal / CAS, and an address signal ADD, which are external control signals, are taken in synchronization with the rising edge of CLK.
[0007]
The address signal ADD is given by multiplexing a row address signal and a column address signal in a time division manner.
[0008]
Row address strobe signal / RAS is applied to external clock signal ext. If it is at the “L” level in the activated state at the rising edge of CLK, the address signal ADD at that time is taken in as the row address signal Xa.
[0009]
Next, column address strobe signal / CAS is supplied to external clock signal ext. If the signal is at the “L” level in the activated state at the rising edge of CLK, the address signal ADD at that time is taken in as the column address signal Yb. In accordance with the fetched row address signal Xa and column address signal Yb, a row and column selection operation is performed in the DDR-SDRAM.
[0010]
Reading from the memory cell is performed by external clock signal ext. Executed when column address strobe signal / CAS is at "L" level and write enable / WE is at "H" level at the rising edge of CLK. After a predetermined clock period (3.5 clock cycles in FIG. 11) elapses after the row address strobe signal / RAS falls to "L" level, 4-bit data enables high-speed data transmission. Are output in synchronization with the data strobe signals DQS and / DQS.
[0011]
Writing to the memory cell is performed by external clock signal ext. If the column address strobe signal / CAS and the write enable / WE are at "L" level at the rising edge of CLK, the operation is executed. In the write operation, the row address signal Xc is taken in similarly to the data read.
[0012]
Next, the external clock signal ext. If the column address strobe signal / CAS and the write enable / WE are both at the “L” level at the rising edge of CLK, the column address signal Yd is taken in and the data d0 given at that time is taken. Is taken as the first write data. Further, input data d1 to d3 are sequentially fetched in synchronization with data strobe signals DQS and / DQS, and this input data is sequentially written into the memory cells.
[0013]
In such a synchronous semiconductor memory device that transfers data at high speed, data is output at both the rising edge and falling edge of the external clock signal in order to increase the operation speed. A technique for generating an internal clock pulse synchronized with an external clock signal using a clock pulse generation circuit (hereinafter also simply referred to as a DLL circuit) using a digital DLL (Delay Locked Loop) is known. By generating such an internal clock pulse, high-speed data transfer synchronized with the data strobe signals DQS and / DQS is possible.
[0014]
FIG. 12 is a diagram showing a clock buffer 100 and a DLL circuit 110 that generates internal clock pulses.
[0015]
Clock buffer 100 receives external clock signal ext. The internal clock signal int. CLK is a circuit that generates an external power supply voltage ext. Operates upon supply of VCC. That is, the internal clock signal int. The amplitude of CLK is the external power supply voltage ext. It becomes VCC level.
[0016]
The DLL circuit 110 receives the internal clock signal int. By delaying the phase of CLK, the external clock signal ext. An internal clock pulse CLKP synchronized with CLK is generated.
[0017]
FIG. 13 is a diagram illustrating a part of the internal circuit of the DLL circuit 110.
Referring to FIG. 13, DLL circuit 110 includes 2N (N: natural number) inverters I (0) to I (2N−1) connected in series and constituting a delay stage, and selector 130.
[0018]
Two inverters I (0) to I (2N-1) each constitute N delay stages each having the same delay amount. The first-stage inverter I (0) is connected to the internal clock signal int. Receive CLK.
[0019]
The selector 130 receives the output of each of the N delay stages and selectively outputs the output of any one of the delay stages to the internal clock pulse int. Output as CLKP. That is, the selector 130 controls the amount of delay added at the delay stage. For example, the amount of delay added in the delay stage is set to the external clock signal ext. By controlling to K times the period of CLK (K: natural number), the internal clock pulse int. CLKP is converted to the internal clock signal int. CLK, that is, the external clock signal ext. Can be synchronized with CLK.
[0020]
In the DLL circuit 110, in order to stably form the phase-locked loop as described above, it is necessary to suppress the variation in the delay amount of each delay stage. Therefore, in order to make the operation delay time of each inverter constant, the DLL circuit 110 includes an external power supply voltage ext. In general, the power supply is not supplied with VCC directly but operates with the operation power supply voltage VCC stabilized by a regulator or the like. The operating power supply voltage VCC and the external power supply voltage ext. VCC is assumed to be set to the same level during normal operation.
[0021]
[Problems to be solved by the invention]
Here, the external power supply voltage ext. Consider the case where voltage fluctuations occur in VCC.
[0022]
FIG. 14 is an operation waveform diagram for explaining the influence of fluctuations in the power supply voltage on the operation of first-stage inverter I (0) of DLL circuit 110.
[0023]
14A shows that the operating power supply voltage of the first stage inverter I (0) of the DLL circuit 110 is the external power supply voltage ext. Operation in the case of VCC is shown. In this case, the threshold voltage of the inverter I (0) is ext. VCC / 2. Therefore, external power supply voltage ext. Even if the amplitude of the input signal (int.CLK) of the DLL circuit varies with the variation of VCC, the threshold voltage of the inverter I (0) also varies, so the external power supply voltage ext. The phase fluctuation (jitter) ΔT0 caused by the fluctuation of VCC is relatively small.
[0024]
However, as described above, the operating power supply voltage of the DLL circuit 110 includes the external power supply voltage ext. VCC is not applied directly, but another more stable operating power supply voltage VCC is applied. As shown in FIG. 14B, in this case, the threshold voltage of the inverter I (0) is VCC / 2. That is, external power supply voltage ext. Even if the amplitude of the input signal (int.CLK) of the DLL circuit 110 varies with the variation of VCC, the threshold voltage of the inverter I (0) does not change.
[0025]
As a result, the external power supply voltage ext. The phase fluctuation (jitter) ΔT1 caused by the fluctuation of VCC increases. Thus, when the phase fluctuation increases, the internal clock pulse int. CLKP and external clock signal ext. Since it becomes difficult to accurately synchronize with CLK, the data transfer margin may be reduced.
[0026]
The present invention has been made to solve such problems, and the object of the present invention is to provide an external power supply voltage ext. An object of the present invention is to provide a configuration of a synchronous semiconductor memory device that suppresses the occurrence of phase fluctuations of the internal clock pulse CLKP due to fluctuations in VCC and makes data transfer at high speed.
[0027]
[Means for Solving the Problems]
A synchronous semiconductor memory device according to the present invention operates by receiving a first voltage and receives a first external clock and outputs a first internal clock, and a second voltage is supplied. The second clock buffer that receives the first internal clock and outputs the second internal clock, operates by receiving the supply of the second voltage, and based on the second internal clock, A phase adjustment circuit for generating an internal clock pulse synchronized with the external clock.
[0028]
Preferably, the apparatus further includes a third clock buffer that operates by receiving the supply of the first voltage, receives an external clock, and outputs an inverted internal clock that is an inverted signal of the first internal clock, The clock buffer includes a differential amplifier that outputs a second internal clock in response to a comparison between the first internal clock and the inverted internal clock.
[0029]
Preferably, the second clock buffer includes an inverter that outputs an inverted signal of the first internal clock as the second internal clock.
[0030]
In particular, it further includes an internal circuit and a third clock buffer that operates by receiving the supply of the first voltage, receives the first internal clock, and outputs the third internal clock to the internal circuit.
[0031]
Preferably, a second signal line for transmitting an external clock to the first clock buffer and a second signal line for transmitting the second internal clock to the phase adjustment circuit are further provided. The signal line has a shorter wiring distance than the first signal line.
[0032]
Preferably, a regulator is further provided for receiving the first voltage and stably supplying the second voltage.
[0033]
Preferably, the second voltage is an external power supply voltage different from the first voltage.
A synchronous semiconductor memory device of the present invention operates by receiving a first voltage, receives a first clock from an external clock, and outputs a first internal clock. An internal circuit that operates by receiving an input; a second clock buffer that operates by receiving a second voltage; outputs a second internal clock by receiving an external clock; and a second voltage And a phase adjusting circuit for generating an internal clock pulse synchronized with the external clock based on the second internal clock.
[0034]
Preferably, a regulator is further provided for receiving the first voltage and stably supplying the second voltage.
[0035]
Preferably, the second voltage is an external power supply voltage different from the first voltage.
Preferably, the apparatus further includes a first signal line for transmitting an external clock to the second clock buffer, and a second signal line for transmitting the second internal clock to the phase adjustment circuit. The wiring distance is shorter than that of the first signal line.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.
[0037]
(Embodiment 1)
FIG. 1 is a diagram showing an overall configuration of a synchronous semiconductor memory device DDR-SDRAM 1000 of the present invention.
[0038]
The DDR-SDRAM 1000 has an external power supply voltage ext. A power supply terminal 1 that receives the supply of VCC, a data input / output terminal 2 that exchanges a data signal DQ with the outside, a data strobe terminal 3 that receives inputs of complementary data strobe signals DQS and / DQS, and an address signal ADD Address terminal 4 receiving the input of the external clock signal and a complementary external clock signal ext. CLK and ext. A clock input terminal 5 for receiving / CLK and a control signal terminal 6 for receiving control signals such as a row address strobe signal / RAS, a column address strobe signal / CAS and a write enable / WE.
[0039]
The synchronous semiconductor memory device 1000 further receives a control circuit 12 that controls the operation of the entire synchronous semiconductor memory device and an address signal ADD from the address terminal 4 and outputs an internal address to the control circuit 12. An address buffer 7 and a control buffer 8 that receives an input of a control signal from the control signal terminal 6 and outputs an internal control signal to the control circuit 12 are provided.
[0040]
The synchronous semiconductor memory device 1000 further includes an external power supply voltage ext. A stable internal power supply voltage int. A regulator 20 for generating VCC is provided.
[0041]
The synchronous semiconductor memory device 1000 further includes an external clock signal ext. CLK and ext. / CLK is received and the internal clock signal int. CLK and int. / CLK is generated and output to the address buffer 7, the control buffer 8 and the control circuit 12 which are internal circuit groups for timing adjustment, and the internal clock signal int. CLK and int. / CLK to receive the internal clock pulse int. CLKP and int. DLL circuit 11 for generating / CLKP.
[0042]
Synchronous semiconductor memory device 1000 further includes a memory array 10 having a plurality of memory cells arranged in rows and columns, and a data input / output buffer 9 for inputting / outputting data. The data input / output buffer 9 includes a control signal from the control circuit 12, a data strobe signal DQS and an internal clock pulse int. CLKP and int. In response to the input of / CLKP, the input / output of the data signal DQ is controlled. That is, at the time of data input, the data input / output buffer 9 captures the data signal DQ input to the data input / output terminal 2 as 1-bit write data in response to the data strobe signals DQS and / DQS. The fetched write data is written to the memory array. On the other hand, at the time of data reading, a plurality of bits of read data read from the memory array 10 are transferred to the internal clock pulse int. CLKP and int. In response to / CLKP, the data signal DQ is output from the data input / output terminal 2 bit by bit. The data input / output buffer 9 has an internal clock pulse int. CLKP and int. Data strobe signals DQS and / DQS based on / CLKP are output from data strobe terminal 3.
[0043]
2 shows the internal clock signal int. Included in the clock input buffer 13 of FIG. CLK and int. / CLK generating clock buffer 200 and internal clock pulse int. CLKP and int. It is a figure which shows a structure with the DLL circuit 11 which produces | generates / CLKP.
[0044]
Clock buffer 200 includes differential amplifiers 10a, 10b, 10 # a and 10 # b.
[0045]
FIG. 3 is a diagram illustrating a circuit configuration of the differential amplifier 10a.
Differential amplifier 10a includes P channel MOS transistors PT1 and PT2, N channel MOS transistors NT1 and NT2, and an inverter IV0.
[0046]
P-channel MOS transistor PT1 and N-channel MOS transistor NT1 are connected in series between power supply node N0 and node N2 via node N1. Node N2 is connected to ground voltage GND. P-channel MOS transistor PT2 and N-channel MOS transistor NT2 are connected in series between power supply node N0 and node N2 via node N3.
[0047]
The gates of P channel MOS transistors PT1 and PT2 are connected to node N1. N channel MOS transistors NT1 and NT2 are connected to input nodes N4 and N5, respectively. Inverter IV0 is arranged at the final stage of differential amplifier 10a and inverts the voltage level of node N3 to invert internal clock signal int. CLK # is output. Differential amplifier 10a receives external power supply voltage ext. Operates upon supply of VCC. Further, the external clock signal ext. / CLK and ext. Each input of CLK is received.
[0048]
Differential amplifier 10a receives external clock signal ext. Input to input node N5. CLK and the external clock signal ext. Operates according to the comparison with / CLK. Specifically, the differential amplifier 10a receives the external clock signal ext. The external clock signal ext. / CLK during a period in which the voltage level is high, internal clock signal int. CLK # is set to "L" level. On the other hand, the external clock signal ext. The external clock signal ext. / CLK when the voltage level is low, internal clock signal int. CLK # is set to the “H” level.
[0049]
FIG. 4 is a diagram illustrating a circuit configuration of the DLL circuit 11.
The DLL circuit 11 includes inverters I (0) to I (2N−1), a selector 130, and a phase comparator 140.
[0050]
Two inverters I (0) to I (2N-1) each constitute N delay stages each having the same delay amount. The first-stage inverter I (0) receives the internal clock signal int. Receive CLK. The selector 130 receives the output of each of the N delay stages and selectively outputs the output of any one of the delay stages to the internal clock pulse int. Output as CLKP.
[0051]
The phase comparator 140 receives the internal clock pulse int. CLKP and the internal clock signal int. A selection signal SL is generated based on the phase comparison result with CLK. For example, the internal clock pulse int. CLKP is the internal clock signal int. If it is earlier than the phase of CLK, the phase is adjusted by increasing the number of delay stages that pass through in accordance with the selection signal SL. On the other hand, the internal clock pulse int. CLKP is the internal clock signal int. When the phase is slower than the phase of CLK, the phase is adjusted by reducing the number of delay stages that pass through according to the selection signal SL.
[0052]
Inverters I (0) to I (2N-1) operate by receiving power supply from power supply node NV. The power supply node NV has an internal power supply voltage int. VCC is supplied.
[0053]
Although not shown, the internal clock signal int. In response to the internal clock pulse int. Similar to the above-described configuration for generating CLKP, the internal clock signal int. / CLK in response to internal clock pulse int. The DLL circuit 11 includes a DLL loop that generates / CLKP.
[0054]
Conventionally, the internal clock signal int. CLK is input to the DLL circuit 11 as it is. Therefore, external power supply voltage ext. A phase fluctuation occurred in the DLL circuit 11 with the fluctuation of VCC.
[0055]
Therefore, in the first embodiment of the present invention, the external power supply voltage ext. Even when VCC voltage fluctuation occurs, the internal clock signal int. It is an object to make the configuration in which CLK is not affected.
[0056]
Referring to FIG. 2 again, the circuit configuration of clock buffer 200 according to the first embodiment of the present invention will be described.
[0057]
Differential amplifiers 10a and 10b in clock buffer 200 are connected to external power supply voltage ext. Operates in response to the supply of VCC, and the internal clock signal int. CLK # and internal clock signal int. / CLK # is generated. Differential amplifiers 10 # a and 10 # b receive internal power supply voltage int. Operates in response to the supply of VCC, and the internal clock signal int. CLK and int. / CLK is generated and output to the DLL circuit 11.
[0058]
As compared with the configuration of differential amplifier 10a shown in FIG. 3, differential amplifier 10b receives external clock signal ext. At input nodes N4 and N5. CLK and ext. / CLK is received and internal clock signal int. The difference is that / CLK # is generated.
[0059]
As compared with the configuration of differential amplifier 10a shown in FIG. 3, differential amplifier 10 # a has internal power supply voltage int. VCC is supplied to the input nodes N4 and N5 and the external clock signal int. CLK # and int. The difference is that / CLK # is input. Internal clock signal int. The amplitude of CLK is the internal power supply voltage int. It becomes VCC level.
[0060]
As compared with the configuration of differential amplifier 10a shown in FIG. 3, differential amplifier 10 # b has internal power supply voltage int. VCC is supplied to the input nodes N4 and N5 and the external clock signal int. / CLK # and int. The difference is that CLK # is input. Internal clock signal int. / CLK is the amplitude of internal power supply voltage int. It becomes VCC level.
[0061]
Differential amplifiers 10 # a and 10 # b each have a common external power supply voltage ext. As described with reference to FIG. 14 (a), the external power supply voltage ext. The internal clock int. CLK and int. Due to the amplitude fluctuation of / CLK, it is possible to suppress the occurrence of phase fluctuations generated in the DLL circuit 11.
[0062]
In particular, the internal power supply voltage int. Since the stability of VCC is high, the internal clock signal int. VCC and int. Amplitude fluctuation of / CLK is suppressed. Also from this point, the occurrence of phase fluctuations generated inside the DLL circuit 11 is strongly prevented.
[0063]
Further, the internal clock signal int. CLK and int. It is possible to employ a configuration that does not adversely affect the generation of / CLK.
[0064]
FIG. 5 shows the external power supply voltage ext. FIG. 11 is an operation waveform diagram for explaining the operation of the differential amplifier 10 # a when a voltage variation occurs in VCC.
[0065]
Referring to FIG. 5, external power supply voltage ext. When the VCC voltage is stable, the internal clock signal int. CLK # and int. / CLK # is indicated by a solid line. At normal time, differential amplifiers 10 # a and 10 # b are connected to internal clock signal int. CLK # and int. / CLK # is detected to detect the internal clock signal int. CLK and int. / CLK is generated.
[0066]
From this state, the external power supply voltage ext. The internal clock signal int. CLK # and int. The amplitude of / CLK # changes as indicated by the dotted line. However, even in such a case, the internal clock signals int. CLK # and int. The change in timing at which / CLK # intersects is small. Therefore, by using differential amplifiers 10 # a and 10 # b, external power supply voltage ext. Even if VCC fluctuates, the internal clock signal int. CLK and int. / CLK and the internal clock pulse int. The phase fluctuation of CLKP can be suppressed.
[0067]
The internal clock signal int. / CLK also for the internal clock signal int. Same as CLK.
[0068]
With the configuration of the first embodiment of the present invention, the external power supply voltage ext. Internal clock pulse int. CLKP and int. The occurrence of / CLKP phase fluctuation can be suppressed, and data transfer can be performed at high speed.
[0069]
(Embodiment 2)
In the first embodiment of the present invention, by adding the differential amplifiers 10 # a and 10 # b, the internal clock signal int. CLK and int. A configuration for controlling the amplitude of / CLK is shown.
[0070]
In the second embodiment of the present invention, the internal clock signal int. Output to the DLL circuit 11 under a simpler circuit configuration. Suppresses the occurrence of phase fluctuation in CLK.
[0071]
In the following embodiments, the internal clock pulse int. / CLKP, the internal clock pulse int. It is assumed that the same configuration as CLKP is arranged.
[0072]
FIG. 6 shows a circuit configuration of clock buffer 210 according to the second embodiment of the present invention.
[0073]
As already described, in the DLL circuit 11, the internal clock pulse int. Accurate phase adjustment is required to generate CLKP. Therefore, the internal power supply voltage int. VCC is input to the power supply node NV of the DLL circuit 11, and the internal clock signal int. CLK is input.
[0074]
In the second embodiment of the present invention, in the clock buffer 210, the internal clock signal int. CLK and the internal clock signal int. The purpose is to generate CLK #.
[0075]
Here, the internal circuit 30 includes the DLL circuit 11 and the internal clock pulse int. Except for circuits operating at CLKP.
[0076]
Clock buffer 210 includes a differential amplifier 10a and an inverter IV1. Inverter IV1 has an input node connected to node N3 of differential amplifier 10a. Inverter IV1 receives an input signal from node N3 and generates internal power supply voltage int. The internal clock signal int. Operates by receiving the supply of VCC and outputs to the DLL circuit 11. Generate CLK.
[0077]
The final stage inverter IV0 is connected to the external power supply voltage ext. The internal circuit 30 operates by receiving the supply of the VCC. CLK # is output.
[0078]
That is, the internal clock signal int. Inverter IV1 for generating CLK and internal clock pulse int. The voltages supplied to the DLL circuit 11 that generates CLKP are the same power supply voltage.
[0079]
With this configuration, the external power supply voltage ext. Even when VCC voltage fluctuation occurs, the int. Since the amplitude of CLK is common to the operating voltage of the DLL circuit 11, the occurrence of phase fluctuations in the DLL circuit 11 can be prevented.
[0080]
Also in the configuration of the second embodiment of the present invention, the external power supply voltage ext. Internal clock pulse int. CLKP and int. The occurrence of / CLKP phase fluctuation can be suppressed, and data transfer can be performed at high speed.
[0081]
Further, the internal clock signal int. Output to the DLL circuit 11 can be more easily than the configuration of the clock buffer 200 shown in the first embodiment of the present invention. A circuit for generating CLK can be configured.
[0082]
In addition, the clock buffer 210 receives an internal clock signal int. The clock buffer that generates CLK # can be shared, and the number of components can be reduced.
[0083]
(Modification of Embodiment 2)
FIG. 7 shows a configuration of clock buffer 220 according to the modification of the second embodiment of the present invention.
[0084]
In the configuration according to the modification of the second embodiment of the present invention, the internal clock signal int. CLK and the internal clock signal int. CLK # is generated independently.
[0085]
Referring to FIG. 7, clock buffer 220 includes differential amplifiers 10 # c and 10a.
[0086]
Differential amplifier 10 # c is connected to internal power supply voltage int. At power supply node N0 as compared to differential amplifier 10a of FIG. VCC is supplied to the input nodes N4 and N5 and the external clock signal ext. / CLK and ext. CLK is received and internal clock signal int. The difference is that CLK is generated.
[0087]
Differential amplifier 10 # c has internal power supply voltage int. Operates in response to the supply of VCC, and the internal clock signal int. CLK is output to the DLL circuit 11. Differential amplifier 10a has external power supply voltage ext. Operates in response to the supply of VCC, and the internal clock signal int. CLK # is output to internal circuit 30.
[0088]
Also in this configuration, the same effect as in the second embodiment can be obtained.
(Embodiment 3)
FIG. 8 shows a circuit configuration of clock buffer 230 according to the third embodiment of the present invention.
[0089]
Referring to FIG. 8, clock buffer 230 includes a differential amplifier 10a and an inverter IV1. Inverter IV1 has an input node connected to node N3 of differential amplifier 10a, and external power supply voltage ext. The internal clock signal int. Generate CLK.
[0090]
Here, the external power supply voltage ext. DVCC is external power supply voltage ext. The voltage level is different from VCC.
[0091]
For example, the terminal DP is connected to the external power supply voltage ext. It is also possible to use a dedicated terminal for supplying DVCC.
[0092]
In the third embodiment of the present invention, the power supply voltage supplied to the inverter IV1 and the DLL circuit 11 is different from that of the second embodiment in that the internal power supply voltage int. VCC to external power supply voltage ext. The difference is that DVCC is replaced.
[0093]
Also in the configuration of the third embodiment of the present invention, the external power supply voltage ext. Internal clock pulse int. CLKP and int. The occurrence of / CLKP phase fluctuation can be suppressed, and data transfer can be performed at high speed.
[0094]
Further, with such a configuration, it is not necessary to provide the regulator 20 in the DDR-SDRAM 1000, and the number of parts can be reduced.
[0095]
(Modification of Embodiment 3)
FIG. 9 shows a circuit configuration of clock buffer 240 according to the modification of the third embodiment of the present invention.
[0096]
A modification of the third embodiment of the present invention is that the internal clock signal int. CLK and the internal clock signal int. The purpose is to generate CLK # independently.
[0097]
Clock buffer 240 includes differential amplifier 10 # d and differential amplifier 10a.
[0098]
Differential amplifier 10 # d receives external power supply voltage ext. The external clock signal ext. / CLK and ext. The internal clock signal int. Generate CLK. Differential amplifier 10a has external power supply voltage ext. Operates with the supply of VCC, and the external clock signal ext. / CLK and ext. The internal clock signal int. CLK # is generated.
[0099]
Differential amplifier 10 # d is connected to external power supply voltage ext. At power supply node N0 as compared to differential amplifier 10a shown in FIG. The point of receiving DVCC, and ext. / CLK and ext. CLK is received and internal clock signal int. The difference is that CLK is generated.
[0100]
Also in this configuration, the same effect as in the third embodiment can be obtained.
(Embodiment 4)
In the first to third embodiments, the internal clock signal int. Although the configuration of the clock buffer for generating CLK has been described, the internal clock signal int. CLK is greatly affected by noise not only by voltage fluctuation but also by wiring distance. This is because if the wiring distance is long, the resistance value and parasitic capacitance of the wiring increase, and the rise and fall of the signal waveform become dull.
[0101]
In the fourth embodiment of the present invention, the internal clock signal int. The object is to reduce the influence of noise on CLK.
[0102]
FIG. 10 shows an arrangement of differential amplifiers 10a and 10 # d described in the modification of the third embodiment.
[0103]
Differential amplifier 10a receives external clock ext. From pad PAD0. CLK and ext. / CLK is received and the internal circuit 30 receives the internal clock signal int. CLK # is output. Differential amplifier 10 # d receives external clock ext. From pad PAD1. CLK and ext. / CLK is input, the internal clock signal int. Output CLK.
[0104]
In general, the longer the wiring distance, the greater the influence of the wiring resistance and parasitic capacitance. Therefore, the wiring distance of the signal line of the internal clock signal transmitted to the DLL circuit 11 and the internal circuit 30 is the differential amplifier 10 # d. Is set to be shorter than the differential amplifier 10a.
[0105]
For example, if the wiring distance from the pad PAD1 to the differential amplifier 10 # d is L0 and the wiring distance from the differential amplifier 10 # d to the DLL circuit 11 is L1, L0> L1 is designed. As a result, the internal clock signal int. CLK noise can be reduced.
[0106]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0107]
【The invention's effect】
8. The synchronous semiconductor memory device according to claim 1, wherein the second clock buffer that outputs the second internal clock and the phase adjustment circuit that adjusts the phase of the internal clock pulse have the same second voltage. In the case where voltage fluctuation occurs in the first voltage, the phase adjustment circuit can prevent the occurrence of phase fluctuations.
[0108]
According to the synchronous semiconductor memory device of the third aspect, the second clock buffer can be easily configured by configuring the second clock buffer for generating the second internal clock with the inverter.
[0109]
According to the synchronous semiconductor memory device of the fourth aspect, the number of parts used for the clock buffer for the internal circuit is generated by generating the third internal clock to be output to the internal circuit by using the first clock buffer in common. Can be reduced.
[0110]
According to the synchronous semiconductor memory device of the fifth and ninth aspects, by making the second signal line shorter than the first signal line, noise of the second internal clock transmitted by the second signal line can be reduced. It can be reduced.
[0111]
According to the synchronous semiconductor memory device of claim 6, the first clock buffer for the internal circuit and the second clock buffer for the phase adjustment circuit are provided separately, and the second clock buffer is provided with the second voltage. In the case where voltage fluctuation occurs in the first voltage, the phase adjustment circuit can prevent the occurrence of phase fluctuations.
[0112]
According to the synchronous semiconductor memory device of the eighth aspect, by setting the second voltage to an external power supply voltage different from the first voltage, it is not necessary to provide a regulator, and the number of circuit components can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a synchronous semiconductor memory device DDR-SDRAM 1000 of the present invention.
FIG. 2 is a diagram showing a configuration of a DLL circuit 11 and a clock buffer 200. FIG.
FIG. 3 is a diagram illustrating a circuit configuration of a differential amplifier 10a.
4 is a diagram showing a circuit configuration of a DLL circuit 11. FIG.
FIG. 5 shows external power supply voltage ext. FIG. 11 is an operation waveform diagram for explaining the operation of the differential amplifier 10 # a when a voltage variation occurs in VCC.
FIG. 6 shows a circuit configuration of clock buffer 210 according to the second embodiment of the present invention.
7 shows a configuration of a clock buffer 220 according to a modification of the second embodiment of the present invention. FIG.
FIG. 8 shows a circuit configuration of clock buffer 230 according to the third embodiment of the present invention.
FIG. 9 is a diagram showing a circuit configuration of a clock buffer 240 according to a modification of the third embodiment of the present invention.
10 is a diagram showing the arrangement of differential amplifiers 10a and 10 # d described in the modification of the third embodiment. FIG.
FIG. 11 is a timing chart showing a continuous access operation in a general DDR-SDRAM.
12 is a diagram showing a clock buffer 100 that internally generates a clock signal and a DLL circuit 110. FIG.
13 is a diagram showing a part of an internal circuit of a DLL circuit 110. FIG.
FIG. 14 is a diagram showing an operation waveform due to voltage fluctuation of the inverter I (0).
[Explanation of symbols]
1000 DDR-SDRAM, 10a, 10b, 10 # a, 10 # b, 10 # c, 10 # d Differential amplifier, 11 DLL circuit, 20 regulator, 30 internal circuit.

Claims (7)

A first clock buffer which operates by receiving a first voltage and receives an external clock and outputs a first internal clock;
A second clock buffer which operates by receiving a second voltage and receives the first internal clock and outputs a second internal clock;
A synchronous semiconductor memory device comprising: a phase adjustment circuit that operates by receiving the supply of the second voltage and generates an internal clock pulse synchronized with the external clock based on the second internal clock. A third clock buffer that operates by receiving the supply of the first voltage, and that receives an input of the external clock and outputs an inverted internal clock that is an inverted signal of the first internal clock;
The synchronous semiconductor memory device according to claim 1, wherein the second clock buffer includes a differential amplifier that outputs the second internal clock in accordance with a comparison between the first internal clock and the inverted internal clock.   The synchronous semiconductor memory device according to claim 1, wherein the second clock buffer includes an inverter that outputs an inverted signal of a first internal clock as the second internal clock. Internal circuitry,
The third clock buffer according to claim 3, further comprising a third clock buffer that operates by receiving the supply of the first voltage, and that receives the first internal clock and outputs the third internal clock to the internal circuit. Synchronous semiconductor memory device. A first signal line for transmitting the external clock to the first clock buffer;
A second signal line for transmitting the second internal clock to the phase adjustment circuit;
The synchronous semiconductor memory device according to claim 1, wherein the second signal line has a wiring distance shorter than that of the first signal line. The synchronous semiconductor memory device according to claim 1, further comprising a regulator that receives the first voltage and stably supplies the second voltage . The synchronous semiconductor memory device according to claim 1, wherein the second voltage is a power supply voltage different from the first voltage .

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