JP2003085973A - Synchronous semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the fluctuation in phases of internal clock pulses int. CLKPs which is caused by the fluctuation of the external power source voltage ext.VCC. SOLUTION: In this memory, since the amplitude of the internal clock signal is not changed even in the case where the fluctuation of the external power source voltage ext.VCC is caused by making a power source voltage with which operational amplifiers generating internal clock signals to output to a DLL (delay locked loop) circuit are operated same as a power source voltage with which the DLL circuit is operated, the fluctuation in phases of the internal clock pulses can be suppressed in the DLL circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device, and more specifically, to an input of a synchronous semiconductor memory device which takes in an external signal in synchronization with a clock signal which is periodically given from the outside. The present invention relates to a circuit configuration of a buffer circuit.

[0002]

2. Description of the Related Art Although a dynamic random access memory (hereinafter referred to as DRAM) used as a main memory has been speeded up, its operating speed still follows the operating speed of a microprocessor (MPU). I can't. Therefore, the access time and cycle time of the DRAM become a bottleneck, and the performance of the entire system may deteriorate. Therefore, in recent years, as a main memory for a high-speed MPU, a double data rate SDRAM (hereinafter, referred to as D
A DR-SDRAM) has been proposed.

In the DDR-SDRAM, complementary external clock signals ext. C
LK and ext. A general specification is to access continuous bits at high speed in synchronization with / CLK.

FIG. 11 is a timing chart showing a continuous access operation in a general DDR-SDRAM.

As an example, FIG. 11 shows an operation of continuously writing or reading 4-bit data at each data terminal. The number of bits of data that is continuously read is called the burst length, and in the DDR-SDRAM, the burst length is adjusted by the mode register.

In the DDR-SDRAM, an external clock signal ext. Externally supplied row address strobe signal / RAS and column address strobe signal / CAS and address signal ADD are taken in synchronization with the rising edge of CLK.

The address signal ADD is provided by time-divisionally multiplexing a row address signal and a column address signal.

The row address strobe signal / RAS is
External clock signal ext. If it is at the "L" level which is in the activated state at the rising edge of CLK, the address signal ADD at that time is taken in as the row address signal Xa.

Next, the column address strobe signal /
The CAS outputs the external clock signal ext. If it is at the "L" level which is in the activated state at the rising edge of CLK, the address signal ADD at that time is the column address signal Y.
Incorporated as b. This fetched row address signal X
a and the column address signal Yb, DDR-SDRA
Row and column selection operations are performed in M.

When reading from the memory cell, the external clock signal ext. This is executed when column address strobe signal / CAS is at "L" level and write enable / WE is at "H" level at the rising edge of CLK. The row address strobe signal / RAS is
After a predetermined clock period (3.5 clock cycles in FIG. 11) has passed after falling to the "L" level, data strobe signals DQS and / DQS for enabling 4-bit data to be transmitted at high speed. Is output in synchronization with.

Writing to the memory cell is performed by using the external clock signal ext. Column address strobe signal / CAS and write enable / W at the rising edge of CLK
If E is "L" level, it is executed. In the write operation, the row address signal Xc is taken in as in the data read.

Next, the external clock signal ext. At the rising edge of CLK, if column address strobe signal / CAS and write enable / WE are both at the active "L" level, column address signal Yd
Is taken in, and the data d0 given at that time is taken in as the first write data. further,
Input data d1 to d3 are sequentially taken in in synchronization with the data strobe signals DQS and / DQS, and the input data are sequentially written to the memory cells.

In such a synchronous semiconductor memory device which transfers data at a high speed, data is output at both the rising edge and the falling edge of the external clock signal in order to speed up the operation. There is known a technique of generating an internal clock pulse synchronized with an external clock signal by using a clock pulse generation circuit (hereinafter also simply referred to as a DLL circuit) to which a digital DLL (Delay Locked Loop) is applied inside the device. By generating such an internal clock pulse, high-speed data transfer in synchronization with the data strobe signals DQS and / DQS becomes possible.

FIG. 12 is a diagram showing a clock buffer 100 and a DLL circuit 110 for generating an internal clock pulse.

Clock buffer 100 receives external clock signal ext. Internal clock signal i in response to CLK input
nt. CLK is a circuit that generates external power supply voltage ex
t. It operates by receiving the supply of VCC. That is, internal clock signal int. The amplitude of CLK is the external power supply voltage ext.
It becomes the VCC level.

The DLL circuit 110 includes the clock buffer 1
00 from the internal clock signal int. By delaying the phase of the external clock signal ext.CLK. CLK
And an internal clock pulse CLKP synchronized with.

FIG. 13 is a diagram showing a part of the internal circuit of DLL circuit 110. Referring to FIG. 13, DLL circuit 1
Reference numeral 10 denotes 2N (N: natural number) inverters I (0) to I (2N-1) connected in series that form a delay stage.
And a selector 130.

2 of the inverters I (0) to I (2N-1)
Each of them constitutes N delay stages, each having the same amount of delay. The first-stage inverter I (0) receives internal clock signal int. Receive CLK.

Selector 130 receives the output of each of the N delay stages and selectively outputs the output of any one of the delay stages to internal clock pulse int. Output as CLKP. That is, the selector 130 controls the delay amount added in the delay stage. For example, the amount of delay added in the delay stage can be calculated using the external clock signal ext. By controlling K times the CLK cycle (K: natural number), the selector 13
0 output from the internal clock pulse int. CLKP
Internal clock signal int. CLK, that is, the external clock signal ext. It can be synchronized with CLK.

In order to stably form the above-described phase locked loop in the DLL circuit 110, it is necessary to suppress the variation in the delay amount of each delay stage. For this reason,
In order to keep the operation delay time of each inverter constant, DL
L circuit 110 receives external power supply voltage ext. It is generally configured to operate by receiving an operating power supply voltage VCC stabilized by a regulator or the like, rather than being directly supplied with VCC to operate. The operating power supply voltage VCC
And the external power supply voltage ext. The VCC is set to the same level in normal times.

[0021]

The external power supply voltage ext. Consider a case where voltage fluctuation occurs in VCC.

FIG. 14 shows that the fluctuation of the power supply voltage is caused by the DLL circuit 1.
FIG. 11 is an operation waveform diagram for explaining the influence on the operation of the first stage inverter I (0) of No. 10.

In FIG. 14A, the operating power supply voltage of the first-stage inverter I (0) of the DLL circuit 110 is the same as that of the clock buffer 100. The operation is shown when it is VCC. In this case, the inverter I
The threshold voltage of (0) is ext. It is VCC / 2. Therefore, external power supply voltage ext. D due to fluctuation of VCC
Even if the amplitude of the input signal (int.CLK) of the LL circuit fluctuates, the threshold voltage of the inverter I (0) also fluctuates, and therefore the external power supply voltage ext.CLK. The phase fluctuation (jitter) ΔT0 caused by the fluctuation of VCC is relatively small.

However, as described above, the operating power supply voltage of DLL circuit 110 is set to the external power supply voltage ext. V
CC is not directly applied, but another more stable operating power supply voltage VCC is applied. As shown in FIG. 14 (b),
In this case, the threshold voltage of the inverter I (0) is VC
It is C / 2. That is, external power supply voltage ext. VCC
Of the input signal of the DLL circuit 110 (in
t. Even if the amplitude of (CLK) changes, the inverter I (0)
The threshold voltage of does not change.

As a result, the external power supply voltage ext. The phase fluctuation (jitter) ΔT1 caused by the fluctuation of VCC is
growing. Thus, when the phase fluctuation becomes large,
Internal clock pulse int. CLKP and the external clock signal ext. Since it becomes difficult to accurately synchronize with CLK, the data transfer margin may be reduced.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an external power supply voltage ext. An object of the present invention is to provide a structure of a synchronous semiconductor memory device which suppresses the occurrence of phase fluctuations of the internal clock pulse CLKP due to the fluctuation of VCC and speeds up data transfer.

[0027]

A synchronous semiconductor memory device of the present invention operates by receiving a first voltage and outputs a first internal clock by receiving an external clock input.
And a second clock buffer that operates by receiving the supply of the second voltage, receives the first internal clock and outputs the second internal clock, and operates by receiving the supply of the second voltage. And a phase adjustment circuit for generating an internal clock pulse synchronized with the external clock based on the second internal clock.

Preferably, the system further comprises a third clock buffer which operates by receiving the supply of the first voltage and which receives an input of the external clock and outputs an inverted internal clock which is an inverted signal of the first internal clock. The second clock buffer includes a differential amplifier that outputs the second internal clock in response to the comparison of the first internal clock and the inverted internal clock.

Preferably, the second clock buffer is
It includes an inverter that outputs an inverted signal of the first internal clock as the second internal clock.

In particular, it further comprises an internal circuit and a third clock buffer which operates by receiving the supply of the first voltage and which receives the first internal clock and outputs the third internal clock to the internal circuit.

Preferably, a first signal line for transmitting the external clock to the first clock buffer and a second signal line for transmitting the second internal clock to the phase adjusting circuit are further provided. The wiring distance of the second signal line is shorter than that of the first signal line.

Preferably, it further comprises a regulator for receiving the first voltage and stably supplying the second voltage.

Preferably, the second voltage is an external power supply voltage different from the first voltage. The synchronous semiconductor memory device of the present invention operates by receiving the supply of the first voltage, receives the input of the external clock, and outputs the first internal clock, and the first internal clock. An internal circuit that operates by receiving an input, a second clock buffer that operates by receiving a supply of a second voltage, and that receives an input of an external clock, and outputs a second internal clock, and a supply of a second voltage And a phase adjustment circuit for generating an internal clock pulse synchronized with the external clock based on the second internal clock.

Preferably, it further comprises a regulator for receiving the first voltage and stably supplying the second voltage.

Preferably, the second voltage is an external power supply voltage different from the first voltage. Preferably, a first signal line for transmitting an external clock to the second clock buffer,
A second signal line for transmitting the second internal clock to the phase adjustment circuit is further provided, and the second signal line has a shorter wiring distance than the first signal line.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference symbols and description thereof will not be repeated.

(First Embodiment) FIG. 1 is a diagram showing an overall structure of a synchronous semiconductor memory device DDR-SDRAM 1000 of the present invention.

DDR-SDRAM 1000 has external power supply voltage ext. A power supply terminal 1 receiving a supply of VCC and a data input / output terminal 2 transmitting / receiving a data signal DQ to / from the outside.
And complementary data strobe signals DQS and / DQS
Data strobe terminal 3, an address signal ADD input address terminal 4, and a complementary external clock signal ext. CLK and ext. A clock input terminal 5 receiving an input of / CLK, and a control signal terminal 6 receiving a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable / WE which are control signals.

Synchronous semiconductor memory device 1000 further includes control circuit 12 for controlling the operation of the entire synchronous semiconductor memory device, and address signal A from address terminal 4.
An address buffer 7 which receives an input of DD and outputs an internal address to a control circuit 12 and a control circuit 1 which receives a control signal from a control signal terminal 6
2 and a control buffer 8 for outputting an internal control signal.

Synchronous semiconductor memory device 1000 further includes external power supply voltage ext. A stable internal power supply voltage int. V
A regulator 20 for generating CC is provided.

Synchronous semiconductor memory device 1000 further includes external clock signal ext.
CLK and ext. / CLK in response to input of internal clock signal int. CLK and int. / CLK and the clock input buffer 13 for outputting to the address buffer 7, the control buffer 8 and the control circuit 12 which are internal circuit groups for timing adjustment, and the internal clock signal int. CLK and int. / CLK
Of the internal clock pulse int. CLKP and int.
DLL circuit 11 for generating / CLKP.

Synchronous semiconductor memory device 1000 further includes a memory array 10 having a plurality of memory cells arranged in rows and columns, and a data input / output buffer 9 for inputting / outputting data. The data input / output buffer 9 is
The control signal from the control circuit 12, the data strobe signal DQS and the internal clock pulse int. CLK
P and int. It receives the input of / CLKP and controls the input / output of data signal DQ. That is, at the time of data input, the data input / output buffer 9 converts the data signal DQ input to the data input / output terminal 2 into the data strobe signal DQ.
In response to S and / DQS, it is fetched as write data bit by bit. The fetched write data is written to the memory array. On the other hand, at the time of data reading, the read / write data of a plurality of bits read from memory array 10 is applied to internal clock pulse int. CLKP and int. In response to / CLKP, the data signal DQ is output bit by bit from the data input / output terminal 2. In addition, the data input / output buffer 9
Internal clock pulse int. CLKP and in
t. Data strobe signals DQS and / DQS based on / CLKP are output from data strobe terminal 3.

FIG. 2 shows the clock input buffer 13 of FIG.
Internal clock signal int. CLK and in
t. / CLK and the internal clock pulse int. CLKP and int. / CL
It is a figure which shows the structure with the DLL circuit 11 which produces | generates KP.

The clock buffer 200 is the differential amplifier 1
0a, 10b, 10 # a and 10 # b.

FIG. 3 is a diagram showing a circuit configuration of the differential amplifier 10a. Differential amplifier 10a has P channel MOS transistors PT1 and PT2, N channel MOS transistors NT1 and NT2, and an inverter IV0.

P-channel MOS transistor PT1 and N-channel MOS transistor NT1 are connected to node N1.
Is connected in series between the power supply node N0 and the node N2. Node N2 is connected to ground voltage GND. P-channel MOS transistor PT2 and N-channel MOS transistor NT2 are connected in series between power supply node N0 and node N2 via node N3.

The gates of P channel MOS transistors PT1 and PT2 are connected to node N1. N-channel MOS transistors NT1 and NT2
Are connected to input nodes N4 and N5, respectively. Inverter IV0 is arranged at the final stage of differential amplifier 10a and inverts the voltage level of node N3 to invert internal clock signal int. Output CLK #. Differential amplifier 10
a is the external power supply voltage ext. VC
It operates by receiving the supply of C. Further, external clock signal ext. / CLK and ext. Receives CLK input respectively.

Differential amplifier 10a receives external clock signal ext. CLK and the external clock signal ext.CLK input to the input node N4. / CLK
Works according to the comparison with. Specifically, the differential amplifier 1
0a is the external clock signal ext. External clock signal ext.CLK rather than CLK. In the period when the voltage level of / CLK is high, internal clock signal int. CLK # is "L"
Set to level. On the other hand, the external clock signal ext. C
The external clock signal ext. / C
While the voltage level of LK is low, internal clock signal int. CLK # is set to "H" level.

FIG. 4 is a diagram showing a circuit configuration of the DLL circuit 11. The DLL circuit 11 includes inverters I (0) to I (0) -I.
(2N-1), selector 130, and phase comparator 140
Including and

2 of the inverters I (0) to I (2N-1)
Each of them constitutes N delay stages, each having the same amount of delay. The first-stage inverter I (0) receives internal clock signal int. Receive CLK. The selector 130 receives the output of each of the N delay stages and selectively outputs the output of any one of the delay stages.
Internal clock pulse int. Output as CLKP.

The phase comparator 140 outputs the internal clock pulse int.CLK output from the selector 130. CLKP and the internal clock signal int.CLK input to the input node NIN.
The selection signal SL is generated based on the result of phase comparison with CLK. For example, the internal clock pulse int. CLKP is the internal clock signal int. If it is earlier than the phase of CLK,
The phase is adjusted by increasing the number of passing delay stages according to the selection signal SL. On the other hand, the internal clock pulse int. CLKP is the internal clock signal int. C
If it is later than the phase of LK, the phase is adjusted by decreasing the number of delay stages passing through according to the selection signal SL.

Further, the inverters I (0) to I (2N-
1) operates by receiving power supply from the power supply node NV. The power supply node NV has an internal power supply voltage int. VCC is supplied.

Although not shown, the internal clock signal i
nt. CLK to receive the internal clock pulse int. CL
The internal clock signal int. / CLK to receive the internal clock pulse int.
The DLL circuit 11 includes a DLL loop that generates / CLKP.

Conventionally, the internal clock signal int.CLK generated by the differential amplifier 10a. CLK to DLL circuit 11
I was just typing in. Therefore, the external power supply voltage ex
t. The DLL circuit 11 has a phase fluctuation associated with the fluctuation of VCC.
Had occurred within.

Therefore, in the first embodiment of the present invention, external power supply voltage ext. Even when the voltage fluctuation of VCC occurs, the internal clock signal i input to the DLL circuit 11
nt. It is intended to have a configuration in which CLK is not affected.

Referring again to FIG. 2, the circuit configuration of clock buffer 200 according to the first embodiment of the present invention will be described.

Differential amplifiers 10a and 10b in clock buffer 200 receive external power supply voltage ext. VCC
Of the internal clock signal int. CL
K # and internal clock signal int. / CLK # is generated respectively. The differential amplifiers 10 # a and 10 # b are
Internal power supply voltage int. It operates by receiving the supply of VCC, and the internal clock signal int. CLK and int. / CLK
Are generated and output to the DLL circuit 11.

Differential amplifier 10b has the same structure as differential amplifier 10a shown in FIG.
5 to the external clock signal ext. CLK and ext. /
CLK respectively to receive the internal clock signal int. / C
The difference is that LK # is generated.

Differential amplifier 10 # a has the same structure as differential amplifier 10a shown in FIG. 3 except that internal power supply voltage int. VCC and the external clock signal int.NV at input nodes N4 and N5. CLK
# And int. The difference is that / CLK # is input respectively. Internal clock signal int. The amplitude of CLK is
Internal power supply voltage int. It becomes the VCC level.

Differential amplifier 10 # b has the same structure as differential amplifier 10a shown in FIG. VCC and the external clock signal int.NV at input nodes N4 and N5. / CL
K # and int. The difference is that CLK # is input respectively. Internal clock signal int. / CLK has an internal power supply voltage int. It becomes the VCC level.

Differential amplifiers 10 # a and 10 # b each have a common external power supply voltage ext. With the configuration in which the operation is performed by receiving the supply of the VCC, as described in FIG. 14A, the external power supply voltage ext. Internal clock int. CLK and int. /
It is possible to suppress the occurrence of phase fluctuation occurring inside the DLL circuit 11 due to the amplitude fluctuation of CLK.

Particularly, the internal power supply voltage int.CLK generated by the regulator 20 and supplied to the DLL circuit 11 is generated. V
Since the stability of CC is high, the internal clock signal int. V
CC and int. Amplitude fluctuation of / CLK is suppressed.
From this point as well, the occurrence of the phase fluctuation generated inside the DLL circuit 11 is strongly prevented.

Further, internal clock signal int. CLK
And int. It is possible to adopt a configuration in which the generation of / CLK is not adversely affected.

FIG. 5 shows the external power supply voltage ext. FIG. 7 is an operation waveform diagram for explaining an operation of differential amplifier 10 # a when a voltage fluctuation occurs in VCC.

Referring to FIG. 5, external power supply voltage ext. V
Internal clock signal int. CLK # and int. / CLK # is shown by a solid line. In normal time, differential amplifiers 10 # a and 10 # b receive internal clock signal int. CLK # and int. / CLK # is detected, the internal clock signal int. CLK and int. /
Generate CLK.

From this state, the external power supply voltage ext. VC
Due to the fluctuation of C, the internal clock signal int. CLK #
And int. The amplitude of / CLK # changes as indicated by the dotted line. However, even in such a case, the internal clock signals int. CLK # and int.
The change in the timing at which / CLK # crosses is small. Therefore, by using differential amplifiers 10 # a and 10 # b, external power supply voltage ext. Even if the VCC changes, the internal clock signal int. CLK and int. /
CLK and the internal clock pulse int.CLK. It is possible to suppress the phase fluctuation of CLKP.

Internal clock signal int. / CLK
Regarding the internal clock signal int. It is similar to CLK.

According to the configuration of the first embodiment of the present invention, external power supply voltage ext. Internal clock pulse int. CLKP and int. It is possible to suppress the occurrence of the phase fluctuation of / CLKP and speed up the data transfer.

(Second Embodiment) In the first embodiment of the present invention, by adding differential amplifiers 10 # a and 10 # b, the internal clock signal i output to the DLL circuit 11 is output.
nt. CLK and int. A configuration for controlling the amplitude of / CLK has been shown.

In the second embodiment of the present invention, the internal clock signal int.CLK output to DLL circuit 11 is output under a simpler circuit configuration. It suppresses the occurrence of phase fluctuation in CLK.

In the following embodiments, although not shown, the internal clock pulse int. / CLKP, the internal clock pulse int. It is assumed that the same configuration as CLKP is arranged.

FIG. 6 shows a circuit structure of clock buffer 210 according to the second embodiment of the present invention.

As described above, in DLL circuit 11, internal clock pulse int. Precise phase adjustment is required to generate CLKP. Therefore, the internal power supply voltage in
t. VCC is input to the power supply node NV of DLL circuit 11, and internal clock signal int. CLK is input.

In the second embodiment of the present invention, in clock buffer 210, internal clock signal int.CLK output to DLL circuit 11 is output. CLK and the internal clock signal int.CLK output to the internal circuit 30. It is intended to generate CLK # and.

Here, the internal circuit 30 is the DLL circuit 11
And internal clock pulse int. Circuits that operate on CLKP are excluded.

The clock buffer 210 is the differential amplifier 1
0a and inverter IV1. Inverter IV1
Has an input node connected to the node N3 of the differential amplifier 10a. Inverter IV1 receives the input signal from node N3 and receives internal power supply voltage int. It operates by receiving the supply of VCC, and D
Internal clock signal int. CL
Generate K.

Further, the final stage inverter IV0 has external power supply voltage ext. The internal circuit 30 operates by receiving the supply of the VCC, and the internal clock signal int. Output CLK #.

That is, internal clock signal int. CL
Inverter IV1 and internal clock pulse int. The voltages supplied to the DLL circuit 11 that generates CLKP are the same power supply voltage.

With this configuration, the external power supply voltage ext.
Even when the voltage fluctuation of VCC occurs, the int. CLK amplitude is DLL
Since it is common to the operating voltage of the circuit 11, it is possible to prevent the occurrence of phase fluctuation in the DLL circuit 11.

Also in the configuration of the second embodiment of the present invention,
External power supply voltage ext. Internal clock pulse int. CLKP and int. / CLKP
It is possible to speed up data transfer by suppressing the occurrence of phase fluctuations in the.

DLL circuit 1 is simpler than the configuration of clock buffer 200 shown in the first embodiment of the present invention.
Internal clock signal int. A circuit that generates CLK can be configured.

Clock buffer 210 outputs internal clock signal int.CLK to internal circuit 30. It can be shared with the clock buffer that generates CLK #, and the number of components can be reduced.

(Modification of Second Embodiment) FIG. 7 shows a clock buffer 220 according to a modification of the second embodiment of the present invention.
It is a figure which shows the structure of.

In the structure according to the modification of the second embodiment of the present invention, internal clock signal int. CLK and the internal clock signal int.CLK output to the internal circuit 30. Generate CLK # independently.

Referring to FIG. 7, clock buffer 220
Includes differential amplifiers 10 # c and 10a.

Differential amplifier 10 # c has internal power supply voltage int. VCC and the external clock signal ext. / CLK and ex
t. CLK respectively to receive the internal clock signal int.
The difference is that CLK is generated.

The differential amplifier 10 # c has an internal power supply voltage in
t. It operates by receiving the supply of VCC, and the internal clock signal i
nt. CLK is output to the DLL circuit 11. The differential amplifier 10a includes an external power supply voltage ext. It operates by receiving the supply of VCC, and the internal clock signal int. CLK # is output to internal circuit 30.

Also in this structure, the same effect as in the second embodiment can be obtained. (Third Embodiment) FIG. 8 shows a circuit configuration of a clock buffer 230 according to the third embodiment of the present invention.

Referring to FIG. 8, clock buffer 230
Includes a differential amplifier 10a and an inverter IV1. Inverter IV1 has an input node connected to node N3 of differential amplifier 10a, and receives external power supply voltage ext. It operates by receiving the supply of DVCC, and the internal clock signal int. Generate CLK.

Here, the external power supply voltage ext. DVCC
Is the external power supply voltage ext. This is a voltage level different from VCC.

For example, the terminal DP is connected to the external power supply voltage ext. It is also possible to use a dedicated terminal for supplying DVCC.

The third embodiment of the present invention is different from the second embodiment in that the power supply voltage supplied to inverter IV1 and DLL circuit 11 is equal to internal power supply voltage int. From the external power supply voltage ext. The difference is that it is replaced with DVCC.

Also in the configuration of the third embodiment of the present invention,
External power supply voltage ext. Internal clock pulse int. CLKP and int. / CLKP
It is possible to speed up data transfer by suppressing the occurrence of phase fluctuations in the.

With such a configuration, DDR-SDR
It is not necessary to provide the regulator 20 in the AM 1000, and the number of parts can be reduced.

(Modification of Third Embodiment) FIG. 9 shows a clock buffer 240 according to a modification of the third embodiment of the present invention.
3 is a diagram showing a circuit configuration of FIG.

A modification of the third embodiment of the present invention is a DLL.
The internal clock signal int. CLK
And the internal clock signal int.
The purpose is to independently generate CLK #.

The clock buffer 240 is the differential amplifier 1
0 # d and differential amplifier 10a are included.

The differential amplifier 10 # d has the external power supply voltage ex.
t. The external clock signal ext. / CLK and ext. CLK according to the comparison of the internal clock signal int.CLK. Generate CLK. The differential amplifier 10a includes an external power supply voltage ext. The external clock signal ext. / CLK and e
xt. CLK according to the comparison of the internal clock signal int.CLK.
CLK # is generated.

Differential amplifier 10 # d is different from differential amplifier 10a shown in FIG. 3 in that power supply node N0 has external power supply voltage ext. At the point receiving DVCC and at the input nodes N4 and N5. / CLK and ext. CLK respectively to receive the internal clock signal int. The difference is that CLK is generated.

Also in this structure, the same effect as that of the third embodiment can be obtained. (Fourth Embodiment) In the first to third embodiments, D
Internal clock signal int. CL
Although the configuration of the clock buffer for generating K has been described, the internal clock signal int. CLK is greatly affected by noise not only by voltage fluctuation but also by wiring distance. This is because if the wiring distance is long, the resistance value and the parasitic capacitance of the wiring become large, so that the rising and falling of the signal waveform becomes dull.

In the fourth embodiment of the present invention, the DLL circuit 1
Internal clock signal int. The purpose is to reduce the influence of noise on CLK.

FIG. 10 shows an arrangement of differential amplifiers 10a and 10 # d described in the modification of the third embodiment.

The differential amplifier 10a operates from the pad PAD0 to the external clock ext. CLK and ext. / CLK, the internal circuit 30 receives the internal clock signal int.
Output CLK #. The differential amplifier 10 # d has a pad P
AD1 to external clock ext. CLK and ext.
/ CLK, the DLL circuit 11 receives the internal clock signal int. Output CLK.

Generally, the longer the wiring distance is, the greater the influence of the wiring resistance and the parasitic capacitance is. Therefore, the DLL circuit 11
The wiring distance of the signal line of the internal clock signal transmitted to the internal circuit 30 is set so that the differential amplifier 10 # d is shorter than the differential amplifier 10a.

For example, from the pad PAD1 to the differential amplifier 1
When the wiring distance of 0 # d is L0 and the wiring distance of the differential amplifier 10 # d to the DLL circuit 11 is L1, L0> L1
And design. As a result, the internal clock signal int. CLK noise can be reduced.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0107]

According to the synchronous semiconductor memory device of the present invention, the second clock buffer for outputting the second internal clock and the phase adjusting circuit for adjusting the phase of the internal clock pulse are the same. By driving with the second voltage of, it is possible to prevent the generation of the phase fluctuation in the phase adjustment circuit even when the voltage changes in the first voltage.

According to the synchronous semiconductor memory device of the third aspect, the second clock buffer can be easily constructed by forming the second clock buffer for generating the second internal clock by an inverter. .

According to another aspect of the synchronous semiconductor memory device of the present invention, the first clock buffer is commonly used to generate the third internal clock, which is used for the internal circuit clock buffer. The number of parts can be reduced.

According to the synchronous semiconductor memory device of the present invention, by making the second signal line shorter than the first signal line, the second internal clock transmitted by the second signal line is transmitted. The noise of can be reduced.

According to the sixth aspect of the synchronous semiconductor memory device, the first clock buffer for the internal circuit and the second clock buffer for the phase adjusting circuit are separately provided, and the second clock buffer is provided.
By driving the clock buffer of No. 2 with the second voltage, it is possible to prevent the phase fluctuation from occurring in the phase adjustment circuit even when the voltage changes at the first voltage.

According to the synchronous semiconductor memory device of the present invention, by setting the second voltage to an external power supply voltage different from the first voltage, it is not necessary to provide a regulator and the number of circuit components can be reduced. it can.

[Brief description of drawings]

FIG. 1 shows a synchronous semiconductor memory device DDR-SD according to the present invention.
It is a figure which shows the whole structure of RAM1000.

FIG. 2 shows a DLL circuit 11 and a clock buffer 20.
It is a figure which shows the structure of 0.

FIG. 3 is a diagram showing a circuit configuration of a differential amplifier 10a.

FIG. 4 is a diagram showing a circuit configuration of a DLL circuit 11.

FIG. 5 shows an external power supply voltage ext. FIG. 7 is an operation waveform diagram for explaining an operation of differential amplifier 10 # a when a voltage fluctuation occurs in VCC.

FIG. 6 is a diagram showing a circuit configuration of a clock buffer 210 according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a structure of a clock buffer 220 according to a modification of the second embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a clock buffer 230 according to the third embodiment of the invention.

FIG. 9 is a diagram showing a circuit configuration of a clock buffer 240 according to a modification of the third embodiment of the invention.

FIG. 10 is a diagram showing an arrangement of differential amplifiers 10a and 10 # d described in the modification of the third embodiment.

FIG. 11 is a timing diagram showing a continuous access operation in a general DDR-SDRAM.

FIG. 12 is a diagram showing a clock buffer 100 which internally generates a clock signal, and a DLL circuit 110.

FIG. 13 is a diagram showing a part of an internal circuit of DLL circuit 110.

FIG. 14 is a diagram showing an operation waveform due to a voltage change of the inverter I (0).

[Explanation of symbols]

1000 DDR-SDRAM, 10a, 10b, 10
#A, 10 # b, 10 # c, 10 # d differential amplifier, 1
1 DLL circuit, 20 regulator, 30 internal circuit.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03L 7/081 H03L 7/08 J // H03K 5/00 G06F 1/04 330A H03K 5/00 V F term (reference) 5B079 CC02 CC04 CC14 DD06 DD13 DD20 5J055 AX39 BX17 CX24 DX22 EX07 EY21 EZ07 EZ08 EZ10 EZ12 EZ29 EZ50 EZ51 FX18 GX01 GX02 GX05 5J106 AA04 CC21 CC59 DD09JJ02 BB34 DD34DD02 BB34 DD34DD02BB33 A41 DD34BB33 PP03 PP07 PP10

Claims (9)

[Claims] 1. A first clock buffer which operates by being supplied with a first voltage and which receives an external clock and outputs a first internal clock, and which operates by being supplied with a second voltage. A second clock buffer that receives the first internal clock and outputs a second internal clock; and a second clock buffer that operates by receiving the supply of the second voltage and that operates based on the second internal clock. A synchronous semiconductor memory device comprising: a phase adjustment circuit for generating an internal clock pulse synchronized with a clock. 2. It operates by receiving the supply of the first voltage,
It further comprises a third clock buffer which receives an input of the external clock and outputs an inverted internal clock which is an inverted signal of the first internal clock, wherein the second clock buffer includes the first internal clock and the inverted clock. The second according to the comparison of the internal clock
1. A differential amplifier for outputting the internal clock of claim 1,
The synchronous semiconductor memory device described. 3. The synchronous semiconductor memory device according to claim 1, wherein said second clock buffer includes an inverter which outputs an inverted signal of a first internal clock as said second internal clock. 4. An internal circuit, and a third clock buffer that operates by receiving the supply of the first voltage and receives the first internal clock and outputs the third internal clock to the internal circuit. 4. The synchronous semiconductor memory device according to claim 3, further comprising: 5. A first signal line for transmitting the external clock to the first clock buffer, and a second signal line for transmitting the second internal clock to the phase adjusting circuit. The synchronous semiconductor memory device according to claim 1, further comprising: the second signal line having a shorter wiring distance than the first signal line. 6. A first clock buffer which operates by being supplied with a first voltage and which receives an input of an external clock and outputs a first internal clock, and which receives an input of the first internal clock. An internal circuit that operates, a second clock buffer that operates by receiving a supply of a second voltage, receives the input of the external clock, and outputs a second internal clock, and receives a supply of the second voltage. And a phase adjusting circuit for generating an internal clock pulse synchronized with the external clock based on the second internal clock. 7. The synchronous semiconductor memory device according to claim 1, further comprising a regulator for receiving the first voltage and stably supplying the second voltage. 8. The synchronous semiconductor memory device according to claim 1, wherein the second voltage is a power supply voltage different from the first voltage. 9. A signal line for transmitting the external clock to the second clock buffer, and a second signal line for transmitting the second internal clock to the phase adjustment circuit. 7. The synchronous semiconductor memory device according to claim 6, wherein the second signal line has a wiring distance shorter than that of the first signal line.