JP2001006368A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To take in the prescribed input signal with take-in timing of high accuracy by constituting a device so that external power source voltage is supplied to an input buffer circuit and an input signal latch timing signal generating circuit as power source voltage. SOLUTION: An external power source voltage VCC is supplied to an input buffer circuit 8 for a data strobe signal, a DQLAT generating circuit 9 generating an input data latch signal, an input buffer circuit 10 for input data, and an input buffer circuit 14 for a clock signal from power source pads 1-3. A dropped voltage Vii is supplied to a latch circuit 11 for input data and a latch circuit 16 for an address signal or a command signal, and the external power source voltage VCC and the dropped voltage Vii are supplied to an input buffer circuit 13 for a clock signal and an input buffer circuit 15 for an address signal or a command signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDRAM (sync)
hronous dynamic random access memory) and high-speed DRA
The present invention relates to a semiconductor device such as M (a double data rate [DDR] -SDRAM) which requires high-speed input / output.

[0002]

2. Description of the Related Art For example, in a conventional SDRAM, although the operation speed is high, there is no problem in the operation of an input circuit in a cycle of about 10 ns, and the circuit design has a sufficient margin. In order to cope with an increase in the speed of the SDRAM, it is necessary to increase the accuracy of the input circuit.

[0003]

Here, in an SDRAM using an external power supply voltage VCC for all circuits,
The current consumption greatly differs depending on the combination of the address and the command. As a result, there is a problem that the internal potential greatly varies depending on the combination of the address and the command.

For example, in a type such as DDR-SDRAM, an input buffer circuit for an address signal and a command signal operates at one input / 1 clock, but an input buffer for input data is used. The circuit is supposed to operate at 2 inputs / 1 clock. In particular, relatively strict specifications are required for an input buffer circuit for input data.

In such a case, if an external power supply voltage is used for all circuits, the timing accuracy of input data can be ensured. For example, DDR-SDR
In AM, the arrangement of pads is power-DQ (data)
-Power supply -CLK, / CLK-Command-Address-Power supply, noise generated by a combination of address and command is transmitted to the clock input buffer via the VCC power supply line, and the complementary clock signals CLK,
/ CLK cannot be taken in with high timing accuracy.

In order to solve such problems and reduce power consumption, an SDRAM using a step-down voltage obtained by stepping down an external power supply voltage by an internal step-down circuit has been proposed. Is not always constant, and its level fluctuates depending on the operation state of the internal circuit. To improve the accuracy of the input circuit, use step-down voltages for all input circuits. Is not a good idea.

Therefore, it is conceivable that the external power supply voltage is used for the current mirror amplifying circuit constituting the first stage circuit of the input buffer circuit, and the step-down voltage is used for parts other than the current mirror amplifying circuit. In such a case, although the timing accuracy of taking in the address signal and the command signal can be secured, there is a problem that the input data cannot be taken in at a high timing accuracy.

In view of the foregoing, the present invention has been made in consideration of the above-described problems, and even when a step-down circuit is mounted to reduce power consumption, a semiconductor device capable of receiving a predetermined input signal with high timing accuracy. The purpose is to provide.

[0009]

According to the present invention, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a step-down circuit for lowering an external power supply voltage supplied from the outside. An input buffer circuit for buffering an input signal of the input buffer, an input signal latch circuit for latching a predetermined input signal output from the input buffer circuit, and an input signal to the input signal latch circuit based on a timing signal supplied from the outside. An input signal latch timing signal generating circuit for supplying a signal latch timing signal, wherein the input buffer circuit and the input signal latch timing signal generating circuit are configured to supply an external power supply voltage as a power supply voltage. Things.

According to the semiconductor device of the first invention, a step-down circuit is mounted to reduce power consumption, but a predetermined input signal supplied from the outside is supplied to the input signal latch circuit. A stable external power supply voltage is supplied as a power supply voltage to the input signal latch timing signal generation circuit which supplies the input signal latch timing signal to the input signal latch circuit based on the input buffer circuit and the timing signal supplied from outside. In addition, a predetermined input signal supplied from the outside can be captured with high capture timing accuracy.

In the present invention, a semiconductor device according to a second aspect of the present invention is a semiconductor device having a step-down circuit for stepping down an externally supplied external power supply voltage. The semiconductor device buffers an externally supplied timing signal. An input buffer circuit that generates an internal timing signal, a data output timing signal generation circuit that generates a data output timing signal based on the internal timing signal, and a data output circuit that outputs data in accordance with the data output timing signal. The input buffer circuit is configured to supply an external power supply voltage as a power supply voltage.

According to the semiconductor device of the second aspect of the present invention, a step-down circuit is mounted to reduce power consumption. However, an internal timing signal is generated by buffering a timing signal supplied from the outside. Since the external power supply voltage is supplied to the input buffer circuit, a stable internal timing signal can be supplied to the data output timing signal generation circuit. Therefore, data can be output to the outside with high timing accuracy.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 3, an embodiment of the present invention will be described with a DDR-SDRA.
An example in which the invention is applied to M will be described.

FIG. 1 is a schematic configuration diagram of an input circuit portion provided in an embodiment of the present invention. In FIG. 1, reference numerals 1 to 3 denote power supply pads to which an external power supply voltage VCC is applied, VCC power supply line for supplying voltage VCC to a predetermined internal circuit; 6 is a Vii power supply line for supplying a step-down voltage Vii output from an internal step-down circuit (not shown) for stepping down external power supply voltage VCC to a predetermined internal circuit; is there.

Reference numeral 7 denotes a data input circuit unit, 8 denotes an input buffer circuit for a data strobe signal DS for buffering an externally supplied data strobe signal DS, and 9 denotes an input buffer circuit for the data strobe signal DS. 8 which generates an input data latch signal DQLAT based on a data strobe signal DS output from
LAT generation circuit.

Reference numeral 10 denotes an input buffer circuit for input data DQ that buffers the input data DQ and outputs complementary data DQ and / DQ. Reference numeral 11 denotes complementary data output from the input buffer circuit 10 for input data DQ. DQ,
/ DQ is a latch circuit for input data DQ which latches input data DQ in synchronization with input data latch signal DQLAT.

Reference numeral 12 denotes an address / command input circuit, and reference numeral 13 denotes a clock signal input buffer circuit for buffering externally supplied complementary clock signals CLK and / CLK to generate an internal clock signal CLK1. is there.

A buffer 14 buffers externally supplied complementary clock signals CLK and / CLK to control data output timing in a data output circuit.
This is an input buffer circuit that generates an internal clock signal CLK2 for an LL (delay locked loop) circuit.

That is, in one embodiment of the present invention, although not shown, the data output circuit is configured to output data to the outside in synchronization with a data output timing signal output from the DLL circuit. I have.

Reference numeral 15 denotes an input buffer circuit for buffering an externally supplied address signal or command signal, and reference numeral 16 denotes an address output from the input buffer circuit 15 for an address signal or command signal. A latch circuit for an address signal or a command signal that latches a signal or a command signal.

In one embodiment of the present invention, the input buffer circuit 8 for the data strobe signal DS includes a DQLAT
Generating circuit 9, input buffer circuit 10 for input data DQ
The external power supply voltage VCC is supplied as a power supply voltage to the input buffer circuits 14 for the clock signals CLK and / CLK.

The latch circuit 11 for input data DQ
And a latch circuit 16 for an address signal or a command signal
Is supplied with a step-down voltage Vii as a power supply voltage, and the input buffer circuit 13 for the clock signals CLK and / CLK and the input buffer circuit 15 for the address signal or command signal are supplied to the external power supply voltage VCC and the step-down voltage Vii is supplied.

FIG. 2 is a circuit diagram showing a part of the data input circuit section 7. In FIG. 2, reference numeral 18 denotes a pad to which a data strobe signal DS is externally applied, and 19 denotes a pad to which input data DQ is externally applied. It is.

The latch circuit 11 for input data DQ
, 21 is a latch unit, and 22 to 28 are NMOs.
S transistors, 29 to 32 are PMOS transistors,
33 and 34 are inverters.

Reference numeral 35 denotes an output circuit unit.
7 is a PMOS transistor, 38 and 39 are NMOS transistors, 40 is a latch circuit for latching output data DO, and 41 and 42 are inverters.

FIG. 3 shows the address / command input circuit 12
3 is a circuit diagram showing a part of FIG. 3, in which 44 is a pad to which a positive-phase clock signal CLK is externally applied, 45 is a pad to which a negative-phase clock signal / CLK is externally applied,
Reference numeral 46 denotes a pad to which an address signal ADD is externally applied.

EN is the input buffer circuit 13, 1
Activating signals for activating signals 4 and 15;
When N = H level, the input buffer circuits 13, 1
When 4, 15 = active state and the activation signal EN = L level, the input buffer circuits 13, 14, 15 = inactive state.

In the input buffer circuit 15 for the address signal ADD, reference numeral 47 denotes an amplifying section comprising a current mirror amplifying circuit to which an external power supply voltage VCC is supplied as a power supply voltage.
2 to 56 are NMOS transistors, 57 to 59 are inverters, and Vref is a reference potential.

An inverter 60 buffers the address signal ADD output from the amplifier 47. The inverter 60 has a step-down voltage V
ii is provided.

The input buffer circuit 13 has the same circuit configuration as the input buffer circuit 15. The positive-phase clock signal CLK is applied to the gate of the NMOS transistor corresponding to the NMOS transistor 52, and corresponds to the NMOS transistor 53. The inverted-phase clock signal / CLK is applied to the gate of the NMOS transistor.

As described above, according to the embodiment of the present invention, the step-down circuit is mounted to reduce the power consumption. However, the input buffer circuit 8 for the data strobe signal DS and the DQLAT generation circuit 9 and the input buffer circuit 10 for input data DQ are supplied with a stable external power supply voltage VCC as a power supply voltage.
Q can be captured into the latch circuit 11 with high capture timing accuracy.

The inverter 6 forming the drive of the input buffer circuit 15 for address signals or command signals
0 is supplied with the step-down voltage Vii, but the amplifier 47 is supplied with a stable external power supply voltage VCC as the power supply voltage. 1
6 can be captured.

Since a stable external power supply voltage VCC is supplied as a power supply voltage to the input buffer circuits 14 for the clock signals CLK and / CLK, a stable internal clock signal CLK2 can be supplied to the DLL circuit. In addition, data can be output to the outside with high timing accuracy.

In the embodiment of the present invention, the case where the present invention is applied to the DDR-SDRAM has been described. In the present invention, the first invention reduces the external power supply voltage supplied from the outside. The present invention can be widely applied to a semiconductor device having a step-down circuit. The second invention has a step-down circuit for stepping down an external power supply voltage supplied from outside, and externally outputs data according to a data output timing signal. The present invention can be widely applied to a semiconductor device having a data output circuit for outputting data to a semiconductor device.

Here, when the semiconductor device of the present invention is arranged, the semiconductor device of the present invention includes the following semiconductor devices.

(1) A semiconductor device equipped with a step-down circuit for stepping down an external power supply voltage supplied from the outside, comprising: a first input buffer circuit for buffering a first input signal; and a first input buffer. A first input signal latch circuit for latching a first input signal output from the circuit, and a first input signal latch circuit based on a first timing signal supplied from the outside;
A first input signal latch timing signal generating circuit for supplying a first input signal latch timing signal to the input signal latch circuit of the first embodiment, wherein the first input buffer circuit and the first input signal latch timing signal generating circuit include: And a semiconductor device configured to supply an external power supply voltage as a power supply voltage.

(2) The semiconductor device according to (1), wherein the first input signal latch circuit is configured to supply a step-down voltage as a power supply voltage.

(3) In the semiconductor device according to the above (1) or (2), a second input buffer circuit for buffering a second input signal which suffices with a relatively low timing accuracy for acquisition, A second input signal latch circuit that latches a second input signal output from the input buffer circuit, and a second input signal latch circuit that supplies a second input signal to the second input signal latch circuit based on a second timing signal supplied from the outside A second input signal latch timing signal generation circuit for supplying a latch timing signal, wherein the second input signal latch timing signal generation circuit includes an amplification unit and a drive unit to which an output of the amplification unit is input. An external power supply voltage is supplied as a power supply voltage to the amplifier of the second input buffer circuit and the second input signal latch timing signal generation circuit. A semiconductor device, wherein a step-down voltage is supplied as a power supply voltage to a drive unit of a force signal latch timing signal generation circuit.

(4) The semiconductor device according to (3), wherein the second input signal latch circuit is configured to supply a step-down voltage as a power supply voltage.

(5) In the semiconductor device according to (3) or (4), a third input buffer circuit for buffering the second timing signal to generate an internal timing signal, and based on the internal timing signal A data output timing signal generating circuit for generating a data output timing signal; and a data output circuit for outputting data to the outside in accordance with the data output timing signal, wherein an external power supply voltage is supplied to the first input buffer circuit as a power supply voltage A semiconductor device characterized in that it is configured to:

(6) A semiconductor device equipped with a step-down circuit for stepping down an external power supply voltage supplied from outside, comprising: an input buffer circuit for buffering a timing signal supplied from outside to generate an internal timing signal; A data output timing signal generation circuit that generates a data output timing signal based on an internal timing signal, and a data output circuit that outputs data to the outside according to the data output timing signal, wherein the input buffer circuit includes:
A semiconductor device configured to supply an external power supply voltage as a power supply voltage.

(7) The semiconductor device according to (2), wherein the semiconductor device is a semiconductor memory device, the first input signal is input data, and the first timing signal is a data strobe signal. apparatus.

(8) In the semiconductor device according to (4), the semiconductor device is a semiconductor memory device, a first input signal is input data, a first timing signal is a data strobe signal, and a second input signal is an address. The signal, the command signal, and the second timing signal are complementary clock signals.

(9) In the semiconductor device according to (5), the semiconductor device is a semiconductor memory device, a first input signal is input data, a first timing signal is a data strobe signal, and a second input signal is an address. The signal, the command signal, and the second timing signal are complementary clock signals.

(10) In the semiconductor device according to (9), the data output timing signal generating circuit is a DLL.
A semiconductor device, which is a circuit.

(11) The semiconductor device according to (6), wherein the semiconductor device is a semiconductor memory device, and the timing signal supplied from the outside is a complementary clock signal.

(12) In the semiconductor device according to (11), the data output timing signal generating circuit is
A semiconductor device, which is an L circuit.

[0048]

According to the semiconductor device of the first aspect of the present invention, a step-down circuit is mounted to reduce power consumption, but a predetermined input signal supplied from the outside is input. An input buffer circuit that supplies a signal latch circuit and an input signal latch timing signal generation circuit that supplies an input signal latch timing signal to the input signal latch circuit based on a timing signal supplied from the outside have a stable external power supply as a power supply voltage. Since the voltage is supplied, a predetermined input signal supplied from the outside can be captured at a high capture timing.

According to the semiconductor device of the second invention,
Although a step-down circuit is mounted to reduce power consumption, an input buffer circuit that buffers an externally supplied timing signal and generates an internal timing signal has a stable external power supply as a power supply voltage. Since the voltage is supplied, a stable internal timing signal can be supplied to the data output timing signal generation circuit,
Data can be output to the outside with high timing accuracy.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an input circuit unit included in an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a data input circuit unit included in an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a part of an address / command input circuit unit included in an embodiment of the present invention.

[Explanation of symbols]

 VCC External power supply voltage Vii Internal step-down voltage

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shino Saki ▼ Naoji 4-1-1 1-1 Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (Reference) 5B024 AA03 BA27 BA27 BA29 CA07 5F038 BB04 BE09 CD02 DF05 EZ20 5J056 AA01 AA39 BB17 BB18 CC00 CC02 CC03 CC14 DD13 DD28 FF01 HH03 HH04

Claims (2)

[Claims] 1. A semiconductor device having a step-down circuit for stepping down an external power supply voltage supplied from the outside, comprising: an input buffer circuit for buffering a predetermined input signal supplied from the outside; An input signal latch circuit for latching a predetermined input signal to be output; and an input signal latch timing signal generation circuit for supplying an input signal latch timing signal to the input signal latch circuit based on a timing signal supplied from the outside. A semiconductor device, wherein the input buffer circuit and the input signal latch timing signal generation circuit are configured to supply the external power supply voltage as a power supply voltage. 2. A semiconductor device having a step-down circuit for stepping down an external power supply voltage supplied from outside, comprising: an input buffer circuit for buffering a timing signal supplied from outside to generate an internal timing signal;
A data output timing signal generation circuit that generates a data output timing signal based on the internal timing signal; and a data output circuit that outputs data in accordance with the data output timing signal. The input buffer circuit includes a power supply voltage. A semiconductor device configured to supply an external power supply voltage.