JPH1186552A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device provided with an access- path circuit reducing an invalid data area existing between output data and securing a valid data width (enlarging window width). SOLUTION: In this semiconductor storage device, an internal constant voltage VBOOT is applied to the access-path circuit as a constant voltage source by converting a source voltage VCC applied from the outside through a voltage conversion circuit 5 when the data in a memory cell array 1 are outputted for preventing an effect of voltage dependence in the access-path circuit (first stage circuit 2, one shot pulse generation circuit 3, D-latch circuit 4) continuously inputting/outputting the data synchronized with a clock signal CLK based on a reference voltage Vref inputted from the outside, and the data is outputted from the memory cell array 1 according to this internal constant voltage VBOOT. Thus, the invalid data area existing between the output data in a D-latch circuit 4 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an access path circuit for continuously inputting / outputting data mainly in synchronization with a clock signal input from the outside. And a semiconductor memory device having the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device having such an access path circuit, for example, a semiconductor memory device as shown in FIG. The access path circuit here comprises a first stage circuit 2, a one-shot pulse generation circuit 3, and a D-latch circuit 4, and receives, as an external input, a synchronous dynamic circuit based on a predetermined reference voltage _Vref. A circuit relating to an access involving a time transition from inputting a clock signal CLK of a random access memory (hereinafter referred to as SDRAM) to inputting / outputting data in synchronization with the clock signal CLK;
_cc is applied.

[0003] The semiconductor memory device includes a memory cell array 1 which stores data in addition to the access path circuit, converts the power supply voltage V _cc applied externally to the internal constant voltage V _BOOT, the internal constant voltage V _BOOT And a voltage conversion circuit 5 which outputs data according to the following. That is, here, the configuration is such that the D-latch circuit 4 is provided between the power supply conversion circuit 5 and the memory cell array 1.

FIG. 3 is a timing chart shown for explaining an input / output processing operation of an access path circuit in the semiconductor memory device. Here, when the burst length of the SDRAM is set in the D-latch circuit 4 and data is output from a specific address of the memory cell array 1, a clock signal CLK input from the outside and a
3 shows a comparison with an output data signal DQ output from a DQ pin of an output transistor (not shown) at the subsequent stage of the voltage conversion circuit 5.

That is, at times T1, T2, T3, and T4 after the time T0 when the clock signal CLK is initially input, the time from the rising edge of the clock signal CLK to when the output data signal DQ is output from the DQ pin. (T
AC) and the time (tOH) during which the output data signal DQ is held from the rising edge of the clock signal CLK at times T2, T3, T4, and T5, the clock signal CLK is input to the access path circuit, and the rising edge , The data output from the memory cell array 1 is secured by controlling the output to the outside using the D-latch circuit 4. The time (tHZ) at time T5 in the figure is the same time corresponding to the time (tAC), and Hi-Z indicates that the output is completed.

More specifically, when outputting data from the memory cell array 1 in this semiconductor memory device, the amplitude of the clock signal CLK is changed by a full swing (0
To 3.3 V) and output as an amplified clock signal, and a one-shot pulse generation circuit 3 generates a one-shot pulse based on the amplified clock signal, and a D-latch circuit 4 triggers a rising edge of the one-shot pulse. To take in the data of the memory cell array 1. D
- the data captured by the latch circuit 4 is inputted a voltage level of the power supply voltage V _cc voltage conversion circuit 5 to the gate of the boosted output transistor to 4.5V at high level, the DQ pin of the output transistor An output data signal DQ of 0 to 3.3 V is output.

[0007]

In the case of the semiconductor memory device having the above-described access path circuit, data is output at the rising edge of one shot pulse by the D-latch circuit and held until the next rising edge. But,
For example, referring to FIG. 3, from output data Q1, Q2, Q3 as output data signal DQ, the next output data Q2,
Time (tAC) when data is switched to Q3 and Q4
And time (tOH), and tAC> tO
Since the relationship H is established, there is a problem that an invalid data area exists between output data.

Thus, the time (tAC) and the time (tO)
Why H) and the variation occurs, the first stage circuit constituting the access path circuit, a power supply voltage V _cc of the voltage applied to the one-shot pulse generating circuit, and D- latch circuit from the outside, the power supply voltage _Vcc is specifically 3.3V ±
This is because the recommended condition of 10% produces a potential difference of 0.6 V at the maximum.

The present invention has been made to solve such a problem, and a technical problem thereof is to reduce an invalid data area existing between output data and secure an effective data width (window width). It is an object of the present invention to provide a semiconductor memory device provided with an access path circuit which can enlarge the above.

[0010]

According to the present invention, there is provided a semiconductor memory having an access path circuit for continuously inputting / outputting data in synchronization with a clock signal based on a predetermined reference voltage externally input. A semiconductor memory device is provided, wherein the power supply to the access path circuit is a constant voltage source generated inside the device based on a power supply voltage applied from the outside.

According to the present invention, in the above-mentioned semiconductor memory device, a memory cell array storing data and a power supply voltage are converted into an internal constant voltage as a constant voltage source.
A semiconductor memory device including a voltage conversion circuit that outputs data according to the internal constant voltage is obtained.

Further, according to the present invention, in the semiconductor memory device described above, the access path circuit includes a first-stage circuit for applying an internal constant voltage to amplify the amplitude of the clock signal and outputting an amplified clock signal; A one-shot pulse generating circuit to which a voltage is applied to generate a one-shot pulse based on an amplified clock signal, and a latch to which an internal constant voltage is applied and data converted to the internal constant voltage is latched based on the one-shot pulse And a semiconductor memory device including the circuit.

In addition, according to the present invention, in the semiconductor memory device described above, the voltage conversion circuit boosts data to a predetermined voltage value as an internal constant voltage when the voltage level of the power supply voltage is high. Is obtained.

Further, according to the present invention, in any of the above semiconductor memory devices, the latch circuit sets a zero voltage value when the voltage level is low and a high voltage when the voltage level is low, triggered by a rising edge of a one-shot pulse. And a semiconductor memory device that outputs data as a predetermined voltage value.

Further, according to the present invention, in the above-mentioned semiconductor memory device, the semiconductor memory device includes a gate for inputting data having a zero voltage value or a predetermined voltage value. A semiconductor memory device having an output transistor that outputs the data from the DQ pin as a constant voltage value lower than the predetermined voltage value when the level is attained is obtained.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a circuit block diagram showing a basic configuration of a semiconductor memory device having an access path circuit according to one embodiment of the present invention. In the case of this semiconductor storage device,
As a basic configuration, as in the conventional device shown in FIG. 2, an access path circuit including an initial stage circuit 2, a one-shot pulse generation circuit 3, and a D-latch circuit 4;
Memory cell array 1 storing data other than pass circuit
And a voltage conversion circuit 5 for converting an external power supply voltage _Vcc into an internal constant voltage _VBOOT .

However, here, the access path circuit is prevented from being affected by voltage dependence in the circuit, and a clock signal CLK of the SDRAM based on a predetermined reference voltage _Vref is input as an external input. to the continuously output constituting the synchronization data CLK, the voltage conversion circuit 5, an internal constant voltage V converted from _the power supply voltage V _cc
BOOT is applied to the access path circuit as a constant voltage source, and data from the memory cell array 1 is immediately output according to the internal constant voltage V _BOOT . For this reason, the semiconductor memory device has a configuration in which the power supply conversion circuit 5 is provided between the memory cell array 1 and the D-latch circuit 4.

That is, in this semiconductor memory device, when outputting data from the memory cell array 1, the voltage conversion circuit 5 accesses the internal constant voltage V _BOOT as a constant voltage source obtained by converting the power supply voltage V _CC applied from the outside. Since the data is applied to the pass circuit and the data is output from the memory cell array 1 in accordance with the internal constant voltage V _BOOT, the invalid data area existing between the output data in the D-latch circuit 4 is reduced. , A burst mode is established.

More specifically, when outputting the data of the memory cell array 1 in this semiconductor memory device, the amplitude of the clock signal CLK is changed to the first-stage circuit 2 to which the internal constant voltage V _BOOT having a predetermined voltage value of 4.5 V is applied. With full swing (0
To 3.3 V), output as an amplified clock signal, and apply 4.5 V to the one-shot pulse generation circuit 3.
Generates a one-shot pulse based on the amplified clock signal.

Therefore, the data in the memory cell array 1 is
When the voltage level of the power supply voltage V _CC is high, the voltage is increased to 4.5 V by the voltage conversion circuit 5. In the D-latch circuit 4 to which 4.5 V is applied, data is output as 0 V when the voltage level is low and 4.5 V when the voltage level is high, triggered by the rising edge of one shot pulse. The data output from the D-latch circuit 4 is input to the gate of the output transistor. The output transistor has a constant voltage value of 0 V when the voltage level is low and lower than 4.5 V when the voltage level is high. .3V to output data (output data signal DQ) from the DQ pin.

Referring to FIG. 3, when the burst length of the SDRAM is set in the D-latch circuit 4 and data is output from a specific address of the memory cell array 1, it is synchronized with the rising edge of the clock signal (CLK). Then, output data Q1, Q2, Q3, Q4 are continuously output.

In this semiconductor memory device, output data Q1
Is output from the DQ pin at least at time (tAC) after the rising edge of the clock signal (CLK) at time T1. The output data Q1 is held at the time T2 at least for the time (tOH) from the rising edge of the clock signal (CLK), and after the time (tAC), the output data Q2 is output from the DQ pin.

At this time, the voltage applied to the AC pass circuit is set to internal constant voltage V _BOOT, and the data output from memory cell array 1 is converted to internal constant voltage V _BOOT by internal conversion circuit 5.
_{Since the} output is performed according to the _BOOT, the influence of voltage dependence in the access path circuit is prevented, and the time (tOH) can be extended to reduce an invalid data area generated between output data. As a result, when data is continuously read out by increasing the address inside the device, an invalid data area generated during a period from when the data output holding state is cut off to when the next data is output is deleted. Thus, switching of output data can be controlled at high speed.

[0025]

As described above, according to the semiconductor memory device of the present invention, the voltage applied to the tAC circuit is controlled by the voltage conversion circuit inside the device in order to prevent the influence of voltage dependence in the access path circuit. The internal constant voltage obtained by converting the power supply voltage input from the outside is replaced with the internal constant voltage, and the data output from the memory cell array is immediately converted to the internal constant voltage by the voltage conversion circuit and output. When the data is read continuously with the address increased, invalid data areas that occur between the time when the data output holding state is cut off and the time when the next data is output are deleted. Data switching can be controlled at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of a semiconductor memory device having an access path circuit according to one embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a basic configuration of a semiconductor memory device having a conventional access path circuit.

FIG. 3 is a timing chart shown for explaining an input / output processing operation of an access path circuit in the semiconductor memory device shown in FIG. 1 or 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 First stage circuit 3 1 shot pulse generation circuit 4 D-latch circuit 5 Voltage conversion circuit

Claims (6)

[Claims] 1. A semiconductor memory device comprising an access path circuit for continuously inputting / outputting data in synchronization with a clock signal based on a predetermined reference voltage input from the outside, wherein said access path circuit A semiconductor memory device, wherein the power supply to the semiconductor memory device is a constant voltage source generated inside the device based on a power supply voltage applied from the outside. 2. The semiconductor memory device according to claim 1, wherein said memory cell array storing said data and said power supply voltage are converted into an internal constant voltage as said constant voltage source, and said data is stored in accordance with said internal constant voltage. A semiconductor memory device, comprising: a voltage conversion circuit for outputting. 3. The semiconductor memory device according to claim 2, wherein said access path circuit includes a first stage circuit to which said internal constant voltage is applied to amplify an amplitude of said clock signal and output an amplified clock signal; A one-shot pulse generating circuit to which an internal constant voltage is applied to generate a one-shot pulse based on the amplified clock signal; and the one-shot pulse which applies the internal constant voltage and converts the data converted to the internal constant voltage to the one-shot pulse. And a latch circuit for latching based on the following. 4. The semiconductor memory device according to claim 2, wherein said voltage conversion circuit boosts said data to a predetermined voltage value as said internal constant voltage when a voltage level of said power supply voltage is a high level. A semiconductor memory device characterized by the following. 5. The semiconductor memory device according to claim 3, wherein the latch circuit sets a zero voltage value when the voltage level is low and a high voltage when the voltage level is low, triggered by a rising edge of the one-shot pulse. The semiconductor memory device outputs the data as the predetermined voltage value. 6. The semiconductor memory device according to claim 5, further comprising: a gate for inputting said data having said zero voltage value or said predetermined voltage value, wherein said voltage is a zero voltage value when said voltage level is a low level; A semiconductor memory device comprising: an output transistor that outputs the data from a DQ pin as a constant voltage value lower than the predetermined voltage value when the signal is at a high level.