JP3317243B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device having an internal pipeline structure.

[0002]

2. Description of the Related Art In recent years, with the speeding up of CPUs, there has been an increasing demand for speeding up of semiconductor memory devices. But,
This demand cannot always be fulfilled due to the physical limit of process miniaturization and the increase in chip size due to the increase in capacity. Therefore, as one means for overcoming this problem, a synchronous semiconductor memory device having an internal pipeline structure has been proposed (Japanese Patent Application Laid-Open No. 61-146892).
Japanese Patent Application No. 4-67795, "Semiconductor Memory Device", Japanese Patent Application No. 6-232732, "Semiconductor Memory Device", etc.).

FIG. 5 is a block diagram showing an example of such a conventional semiconductor memory device. Referring to FIG. 5, the semiconductor memory device includes a plurality of input circuits 1 for inputting a plurality of address terminals ADD, an input circuit 2 for inputting input terminal DQM, and an internal synchronization signal φ1 for inputting external clock CLK.
And an internal address signal IA in synchronization with an internal synchronization signal φ1.
A burst counter 4 for outputting DD, a column decoder 5 for receiving an internal address signal IADD and outputting a plurality of column selection lines YSW, a plurality of memory cells 6, and a column selection line YSW for inputting data of the memory cells 6 A plurality of sense amplifiers 7 for amplifying and outputting, and a synchronizing signal generating circuit 8 for receiving an internal synchronizing signal φ1 and outputting an internal synchronizing signal φ2
A synchronization signal generating circuit 9 for receiving an internal synchronization signal φ1 and outputting an internal synchronization signal φ3, a plurality of latch circuits 10 receiving an output of the sense amplifier 7 and outputting in synchronization with the internal synchronization signal φ2, A plurality of data amplifiers 24 which receive and amplify the output of the D.10 and output the data D1; a plurality of DF / F circuits 25 which receive the data D1 and output the data D2 in synchronization with the internal synchronization signal φ3; The output of the input circuit 2 is input and the mask signal MS is synchronized with the internal synchronization signal φ1.
A latch circuit 12 for outputting K1B, and a DF for receiving the output of the latch circuit 12 and outputting the same in synchronization with the internal synchronization signal φ1
/ F circuit 27, a delay element DL that receives an output of the DF / F circuit 27 and outputs a mask signal MSK2B, and a plurality of outputs that receives data D2 and a mask signal MSK2B and outputs conduction control signals D3T and D3N. Control circuit 26
And the continuity control signals D3T and D3N and output terminal DQ
And a plurality of output circuits 17 that output data to the output circuit 17.

An output control circuit 26 receives data D2 and a mask signal MSK2B and outputs a conduction control signal D3T. An AND gate AN3 receives the inverted signal of data D2 and a mask signal MSK2B and receives a conduction control signal D3N.
And an AND gate AN4 for outputting the same.
Here, the input mask signal MSK2B is an output control signal for controlling whether to drive the output terminal DQ of the output circuit 17 or set it to high impedance. The output control circuit 26 outputs the mask signal MSK2B and the data D2
, One of the conduction control signals D3T and D3N is activated, or the conduction control signals D3T and D3N are deactivated and output.

[0005] The output circuit 17 is connected to the gate by a conduction control signal D.
3T, an N-channel output transistor Tr1 connected between the power supply and the output terminal DQ, and an N-channel output transistor D1N connected between the output terminal DQ and ground, and a conduction control signal D3N.
And a channel type output transistor Tr2. Here, the output circuit 17 drives the output terminal DQ to output a high level when only the conduction control signal D3T is activated, and drives the output terminal DQ when only the conduction control signal D3N is activated. Output low level. Also,
When the conduction control signals D3T and D3N are inactivated, the output terminal DQ is set to a high impedance state.

Next, the operation of the conventional semiconductor memory device shown in FIG. 5 will be described.

FIG. 6 is a waveform diagram showing an operation example of the conventional semiconductor memory device shown in FIG. 5, wherein "CAS latency =
"3" indicates a state during a read burst.

“CAS latency” indicates how many clock cycles are required after a read command (read command) is input from the outside until data is output to an output terminal. In the case of "CAS latency = 3", three cycles are required. The "burst" means reading several bits of data continuously by one read command input, and the burst counter 4 generates an internal address corresponding to the "burst length".

When the external clock CLK transitions from a low level to a high level, a high-level pulse is generated in the internal synchronizing signal φ1, and when a pulse is generated in the internal synchronizing signal φ1, high-level pulses are generated in the internal synchronizing signals φ2 and φ3. I do.

When a mask command is input in cycle C2, mask signal MSK1B goes low in synchronization with internal synchronization signal φ1 in that cycle, and when internal synchronization signal φ3 transitions from low to high, delay element DL
After a predetermined delay, the mask signal MSK2B goes low. On the other hand, data R2 corresponding to cycle C2 is transmitted from data amplifier 24 in synchronization with internal synchronization signal φ2.
1 and then output as data D2 from the DF / F circuit 25 in synchronization with the internal synchronization signal φ3.
The data of R2 corresponding to the data D2 is also transmitted to the conduction control signal D3T / D3N of the output of the output control circuit. However, when the mask signal MSK2B becomes low, the conduction control signal D3T / D3N becomes low.
3T / D3N are both low. Therefore, the N-channel output transistors Tr1, Tr in the output circuit 17
2 are both turned off, and the output terminal DQ enters a high impedance (Hi-Z) state.

Next, if a mask command is not input in cycle C3, the mask signal MSK1B goes high in synchronization with the internal synchronization signal φ1 in that cycle, and when the internal synchronization signal φ3 transitions from high to low, a delay After a predetermined delay of the element DL, the mask signal MSK2B goes high. Therefore, the data of R3 corresponding to the data D2 is transmitted to the conduction control signal D3T / D3N of the output of the output control circuit, and the N-channel output transistors Tr1, Tr
2 turns on, and data R3 is output to the output terminal DQ.

The external clock CLK in cycle C3
From the high level of the output terminal DQ is high impedance (H
The time required to enter the (i-Z) state is defined by a specification value called tHZ, and the output terminal DQ must be brought into the high impedance (Hi-Z) state earlier than the specification value tHZ. Further, the external clock CL in cycle C3
After the high level of K, the data R1 being output to the output terminal DQ
Must be held for the time specified by the specification value tOH.

[0013]

In this conventional semiconductor memory device, the timing at which the output terminal DQ is brought into the high impedance (Hi-Z) state after the input of the mask command is determined by the delay for outputting the mask signal MSK2B as the output control signal. The delay time is determined by the delay time of the element DL, and when this delay time is too short, the output terminal DQ becomes high impedance (H
(i-Z) state is early, and the specification value tOH is deteriorated. Conversely, when this delay time is too long, the output terminal DQ is late in the high impedance (Hi-Z) state,
To deteriorate the specification value tHZ, the delay element DL
It is important to optimize the delay time, which will result in an increase in design man-hours and delay in commercialization, or otherwise, the specification value tO
There is a problem that the specifications of H and tHZ must be relaxed.

Japanese Patent Application Laid-Open No. 4-85792, entitled "Semiconductor Storage Device" and Japanese Patent Application Laid-Open No. 4-358392, entitled "Random Access Memory Device and Pipeline / Page Mode Control Method", employ a synchronous system in which a latch circuit is provided and pipeline operation is performed. Although a semiconductor memory device is described, there is no description on control of output enable (data output) and disable (high impedance) during a burst, and even when output control is performed by the circuits in these examples, The above problems are exposed as well.

It is therefore an object of the present invention to easily optimize the data output of the output terminal and the timing of high impedance in a synchronous semiconductor memory device having an internal pipeline structure.

[0016]

According to the present invention, a data amplifier for supplying complementary read data read from a memory cell, and a first latch circuit for latching a mask signal in response to a timing signal are provided. Receiving the mask signal latched by the first latch circuit and the complementary read data supplied from the data amplifier, and based on the complementary read data when the mask signal is at one logical level. To generate the first and second conduction control signals complementary to each other, and when the mask signal is at the other logical level, the first and second conduction control signals are at the same level regardless of the complementary read data. An output control circuit for generating a conduction control signal; and a second control circuit for latching the first and second conduction control signals in response to the timing signal, respectively. And a third latch circuit connected between a first power supply terminal and an output terminal, and a conduction state controlled based on the first conduction control signal latched by the second latch circuit. An output transistor, a second output transistor connected between a second power supply terminal and the output terminal, and a conduction state controlled based on the second conduction control signal latched by the third latch circuit; And a semiconductor memory device including the same.

According to the present invention, a data input terminal, a data output terminal and a clock input terminal are respectively provided, and data on each data input terminal is responsive to a timing signal supplied to each clock input terminal. First and second latch circuits for latching and outputting the data from respective data output terminals, and a gate connected between a first power supply terminal and an output terminal and having a gate connected to the data output terminal of the first latch circuit. A second output transistor connected between a second power supply terminal and the output terminal and having a gate connected to the data output terminal of the second latch circuit; In response to the mask signal being inactive, one of the logic levels of one of the logic levels is applied to the data input terminal of the first latch circuit based on the read data read from the memory cell. Means for supplying data at the other logic level to the data input terminal of the second latch circuit, and responsive to a mask signal being active, irrespective of the read data. Means for supplying the data of the one or the other logic level to the data input terminals of the first and second latch circuits.

[0018]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the semiconductor memory device of the present invention. Referring to FIG. 1, the semiconductor memory device according to the present embodiment includes a plurality of address terminals ADD.
, An input circuit 2 for inputting an input terminal DQM, an input circuit 3 for inputting an external clock CLK and outputting an internal synchronization signal φ1, and an input circuit for receiving an output of the input circuit 1 for internal synchronization. A burst counter 4 for outputting a plurality of internal address signals IADD in synchronization with the signal φ1, and a plurality of column selection lines Y for receiving the internal address signal IADD.
A column decoder 5 that outputs SW, a plurality of memory cells 6, a plurality of sense amplifiers 7 that receive a column selection line YSW to amplify and output data of the memory cells 6, and an internal synchronization signal φ1 that receives an internal synchronization signal φ1 a synchronizing signal generating circuit 8 for outputting φ2, a synchronizing signal generating circuit 9 for receiving an internal synchronizing signal φ1 and outputting an internal synchronizing signal φ3, and a sense amplifier 7
, And a plurality of data amplifiers 11 that receive and amplify the output of the latch circuit 10 and output the data D1T / N, and an input circuit 2. Of the internal synchronization signal φ1
Circuit 1 that outputs mask signal MSK1B in synchronization with
2 and the output of the latch circuit 12 and the internal synchronization signal φ3
A D-latch circuit 13 that outputs a mask signal MSK2B in synchronization with a logic obtained by inverting the data D1T / N and a mask signal MSK2B to input conduction control signals D2T and D2N
And a plurality of output control circuits 14 for outputting the conduction control signal D
A plurality of DF / F circuits 15 for inputting 2T and outputting a conduction control signal D3T in synchronization with the internal synchronization signal φ3, and inputting a conduction control signal D2N and synchronizing the conduction control signal D3N with the internal synchronization signal φ3 Outputting a plurality of DF / F circuits 16
And the continuity control signals D3T and D3N and output terminal DQ
And a plurality of output circuits 17 that output data to the output circuit 17.

The output control circuit 14 outputs the data D1T
And the mask signal MSK2B and the conduction control signal D2T
, And an AND gate AN2 that inputs data D1N and a mask signal MSK2B and outputs a conduction control signal D2N. Here, the input mask signal MSK2B is output from the output circuit 17
Is an output control signal for controlling whether to drive the output terminal DQ or set it to high impedance. Output control circuit 1
6 indicates the mask signal MSK2B and the data D1T,
One of the conduction control signals D2T and D2N is activated corresponding to D1N, or the respective conduction control signals D2T and D2N are deactivated and output.

The output circuit 17 connects the gate to the conduction control signal D.
3T, an N-channel output transistor Tr1 connected between the power supply and the output terminal DQ, and an N-channel output transistor D1N connected between the output terminal DQ and ground, and a conduction control signal D3N.
And a channel type output transistor Tr2. Here, the output circuit 17 drives the output terminal DQ to output a high level when only the conduction control signal D3T is activated, and drives the output terminal DQ when only the conduction control signal D3N is activated. Output low level. Also,
When the conduction control signals D3T and D3N are inactivated, the output terminal DQ is set to a high impedance state.

Next, the operation of the semiconductor memory device of this embodiment will be described.

FIG. 2 is a waveform diagram showing an operation example of the semiconductor memory device shown in FIG. 1, and shows a state during read burst at "CAS latency = 3".

When a mask command is input in cycle C2, the mask signal MSK1B goes low in synchronization with the internal synchronization signal φ1 in that cycle, and when the internal synchronization signal φ3 transitions from high to low, the mask signal MSK
2B goes low. On the other hand, data R2 corresponding to cycle C2 is output from data amplifier 11 as data D1T / N in synchronization with internal synchronization signal φ2, and subsequently output from output control circuit 14 as conduction control signals D2T and D2N. However, since the mask signal MSK2B becomes low when the internal synchronization signal φ3 is at a low level, which is earlier than when the internal synchronization signal φ3 transitions from a low level to a high level and is latched by the latch circuits 15 and 16, conduction occurs. The control signals D2T and D2N are both low. Therefore, the conduction control signals D3T and D3N are both output at a low level in synchronization with the internal synchronization signal φ3, the N-channel type output transistors Tr1 and Tr2 are both turned off, and the output terminal DQ
Is in a high impedance (Hi-Z) state.

Next, unless a mask command is input in cycle C3, the mask signal MSK1B goes high in synchronization with the internal synchronization signal φ1 in that cycle, and when the internal synchronization signal φ3 transitions from high to low, the mask Signal MSK2B goes high. On the other hand, data R3 corresponding to cycle C3 is output as data D1T / N from data amplifier 11 in synchronization with internal synchronization signal φ2. At this point, since mask signal MSK2B is still at a low level, output control is performed. The circuit 14 has a conduction control signal D2
Both T and D2N output a low level. However, since the mask signal MSK2B goes to a high level when the internal synchronization signal φ3 is at a low level earlier than when the internal synchronization signal transitions from a low level to a high level and is latched by the latch circuits 15 and 16, the conduction control is performed. The conduction control signal D3 corresponding to the data D1T / N is output to the signals D2T and D2N. Therefore, the conduction control signals D3T and D3N are also provided with the internal synchronization signal φ.
3, the data R3 is output, one of the N-channel output transistors Tr1 and Tr2 is turned on, and the data R3 is output to the output terminal DQ.

FIG. 3 is a block diagram showing another embodiment of the semiconductor memory device of the present invention. Referring to FIG. 3, the semiconductor memory device of the present embodiment has a plurality of address terminals AD.
D, a plurality of input circuits 1 and an input terminal RASB
, An input circuit 19 for inputting an input terminal CASB, an input circuit 20 for inputting an input terminal WEB, an input circuit 21 for inputting an input terminal CSB, and an internal synchronization signal for inputting an external clock CLK. an input circuit 3 for outputting φ1, a burst counter 4 for receiving an output of the input circuit 1 and outputting a plurality of internal address signals IADD in synchronization with the internal synchronization signal φ1, and an internal address signal IADD
, A plurality of memory cells 6, a plurality of memory cells 6, and a plurality of column selection lines YS.
A plurality of sense amplifiers 7 that input W and amplify and output data of the memory cell 6, a synchronizing signal generating circuit 8 that inputs an internal synchronizing signal φ1 and outputs an internal synchronizing signal φ2, A synchronizing signal generating circuit 9 for outputting a synchronizing signal φ3, a plurality of latch circuits 10 receiving the output of the sense amplifier 7 and outputting in synchronization with the internal synchronizing signal φ2;
The output of the latch circuit 10 is input and amplified, and the data D1T /
A plurality of data amplifiers 11 for outputting N and an input circuit 1
A command decoder 22 for inputting, outputting, and outputting respective outputs of 8, 19, 20, and 21; and a latch circuit 23 for receiving an output of the command decoder 22 and outputting a read signal READB in synchronization with the internal synchronization signal φ1. And a D-latch circuit 13 for inputting a read signal READB and outputting an output enable signal OEB in synchronization with a logic obtained by inverting the internal synchronization signal φ3, and inputting data D1T / N and an output enable signal OEB to control conduction. A plurality of output control circuits 14 for outputting signals D2T and D2N;
A plurality of DF / F circuits 15 that receive conduction control signal D2T and output conduction control signal D3T in synchronization with internal synchronization signal φ3, and input conduction control signal D2N and receive internal synchronization signal φ3
DF that output a conduction control signal D3N in synchronization with
/ F circuit 16 and a plurality of output circuits 17 which receive conduction control signals D3T and D3N and output data to output terminal DQ.

The output control circuit 14 outputs the data D1T
An AND gate AN1 which receives the output enable signal OEB and outputs the conduction control signal D2T, and an AND gate AN2 which receives the data D1N and the mask signal MSK2B and outputs the conduction control signal D2N. Here, the input output enable signal OEB is an output control signal for controlling whether to drive the output terminal DQ of the output circuit 17 or to set it to high impedance. The output control circuit 16 activates one of the conduction control signals D2T and D2N or inactivates and outputs the conduction control signals D2T and D2N in response to the output enable signal OEB and the data D1T and D1N. The output circuit 17 includes an N-channel output transistor Tr1 connected between the power supply and the output terminal DQ, and a gate connected to the conduction control signal D3T.
N and an N-channel output transistor Tr2 connected between the output terminal DQ and the ground. Here, the output circuit 17 drives the output terminal DQ to output a high level when only the conduction control signal D3T is activated, and drives the output terminal DQ when only the conduction control signal D3N is activated. Output low level. When each of the conduction control signals D3T and D3N is inactivated, the output terminal DQ is set to a high impedance state.

Next, the operation of the semiconductor memory device of this embodiment will be described.

FIG. 4 is a waveform diagram showing an operation example of the semiconductor memory device shown in FIG. 3, wherein "CAS latency = 3",
An example of “burst length = 2” is shown.

First, in cycle C1, the input terminals RASB,
When CASB, WEB, and CSB are input so as to form a combination of read commands, the read signal READB goes low in synchronization with the internal synchronization signal φ1 in the next cycle C2, and the internal synchronization signal φ3 transitions from high to low. Then, the output enable signal OEB becomes low. On the other hand, the data R1 corresponding to the cycle C1 is synchronized with the internal synchronization signal φ2,
Are output as data D1T / N, and are subsequently output from the output control circuit 14 as conduction control signals D2T and D2N. Then, the output enable signal OEB becomes low level when the internal synchronization signal φ3 is low, which is earlier than when the internal synchronization signal φ3 transitions from low level to high level and is latched by the latch circuits 15 and 16. The conduction control signal D3 corresponding to the data D1T / N is output to the conduction control signals D2T and D2N. Therefore, data R3 is also output to conduction control signals D3T and D3N in synchronization with internal synchronization signal φ3, and N-channel output transistor Tr
1 and Tr2 are turned on, and the data R3 is output to the output terminal DQ.
Is output.

Since the burst length is 2, the read signal READ is synchronized with the internal synchronization signal φ1 in the cycle C4.
When the internal synchronization signal φ3 transitions from the high level to the low level, the output enable signal O
EB goes high. The internal synchronization signal in cycle C4 transitions from low level to high level, and latch circuits 15, 16
Since the output enable signal OEB is at a high level when the internal synchronization signal φ3 is at a low level earlier than the timing at which the data of the cycle C4 is output from, both the conduction control signals D2T and D2N are at a low level, The signals D3T and D3N are both output at a low level in synchronization with the internal synchronization signal φ3, the N-channel output transistors Tr1 and Tr2 are both turned off, and the output terminal DQ enters a high impedance (Hi-Z) state.

[0032]

As described above, the semiconductor memory device according to the present invention includes each latch circuit for separately latching and outputting each conduction control signal in synchronization with an internal synchronization signal for controlling an internal pipeline. Each output transistor of the output circuit is separately controlled in accordance with the output of each of these latch circuits. Therefore, the delay variation from the internal synchronization signal input to each latch circuit to each output transistor is minimized, and the output terminals can be driven to a high level or a low level or set to a high impedance state at the same timing. This makes it easy to optimize the related timing specification values (tHZ, tOH).

Further, since the above-described delay variation is minimized, variations with respect to manufacturing variations and power supply voltage variations are reduced, and there is an effect that the characteristics of related timing specification values can be improved.

[0034]

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a waveform chart showing an operation example of the semiconductor memory device shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the semiconductor memory device of the present invention.

4 is a waveform chart showing an operation example of the semiconductor memory device shown in FIG.

FIG. 5 is a block diagram illustrating an example of a conventional semiconductor memory device.

6 is a waveform chart showing an operation example of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 1, 2, 3, 18, 19, 20, 21 Input circuit 4 Burst counter 5 Column decoder 6 Memory cell 7 Sense amplifier 8, 9 Synchronous signal generation circuit 10, 12, 23 Latch circuit 11, 24 Data amplifier 13 D-latch Circuit 14 Output control circuit 15, 16, 25 DF / F circuit 17, 26 Output circuit 22 Command decoder AN1 to AN4 AND gate Tr1, Tr2 N-channel type output transistor DL Delay element

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/41

Claims (3)

(57) [Claims] 1. A data amplifier that supplies complementary read data read from a memory cell, a first latch circuit that latches a mask signal in response to a timing signal, and a first latch circuit that is latched by the first latch circuit. Receiving the complementary read data supplied from the data amplifier and the mask signal, and when the mask signal is at one logical level, the first and second complementary signals are based on the complementary read data. Generating a conduction control signal of
An output control circuit that generates first and second conduction control signals that are at the same level with each other regardless of the complementary read data when the mask signal is at the other logical level; The first and second
Second and third latch circuits respectively latching the first conduction control signal and the first conduction control signal which is connected between the first power supply terminal and the output terminal and latched by the second latch circuit. A first output transistor whose conduction state is controlled based on the second conduction control signal based on the second conduction control signal which is connected between a second power supply terminal and the output terminal and latched by the third latch circuit; And a second output transistor controlled by the first latch circuit.
The mask signal is activated in response to one edge of the imaging signal.
And the second and third latch circuits are
The first signal in response to the other edge of the timing signal;
And a second conduction control signal, respectively.
A semiconductor memory device characterized by the following. 2. The output control circuit receives one of the complementary read data and the mask signal latched by the first latch circuit, and outputs the first read data based on the mask signal.
A first gate circuit for generating a conduction control signal of the second type, and receiving the other of the complementary read data and the mask signal latched by the first latch circuit, and generating the second conduction control signal based on these. 2. The semiconductor memory device according to claim 1, further comprising: a second gate circuit for generating. 3. A data input terminal, a data output terminal, and a clock input terminal, respectively, and latch data on each data input terminal in response to a timing signal supplied to each clock input terminal. First and second latch circuits that output from the data output terminals of the first and second power supply terminals;
A first output transistor connected to the data output terminal of the first latch circuit, a gate connected between a second power supply terminal and the output terminal, and a gate connected to the data output terminal of the second latch circuit; The second input transistor and the data input terminal of the first latch circuit based on read data read from the memory cell in response to the mask signal being inactive. Means for supplying data and supplying data of the other logic level to the data input terminal of the second latch circuit, responsive to the mask signal being active, irrespective of the read data, Means for supplying the one or other logic level data to the data input terminals of the first and second latch circuits.