KR20010002119A - Circuit for control a data input buffer in SDRAM - Google Patents

Abstract

PURPOSE: A circuit for controlling a data input buffer of SDRAM(Synchronous Dynamic Random Access Memory) is provided to reduce current consumption in the data input buffer by maintaining a turn-on state of the data input buffer only when the SDRAM performs a writing operation. CONSTITUTION: A circuit for controlling a data input buffer includes a control signal generator(50) and an input buffer(52). The circuit inputs data to be written to memory cells in a SDRAM(Synchronous Dynamic Random Access Memory) operating as a DDR(Double Dta Rate) mode or SDR(Single Dta Rate) mode. The control signal generator generates a control signal by logically combining a row activation indication signal enabled when a row is activated, a power down indication signal disabled when the SDRAM is power down mode, an output buffer enable signal for enabling an output buffer outputting read data to outside, a write operation indication signal enabled when the SDRAM performs a write operation and a mode indication signal indicating whether the SDRAM is the DDR mode or the SDR mode. The input buffer inputs the data to be written in response to the control signal.

Description

Circuit for control a data input buffer in SDRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a data input buffer control circuit in an SDRAM operable in a double data rate (DDR) mode.

The data input buffer of the conventional DDR SDRAM used the data input buffer used at the single data rate (SDR) as it is. In the SDR SDRAM, data to be written with a write command is applied. Thus, the data input buffer that accepts the data to write in the SDR SDRAM must already be turned on before the write command is applied. Thus, in SDR SDRAM, the data input buffer is always present except when data is output through the DQ pins, which are the data input / output pins, unless the row is activated and in the power down mode. It is turned on.

1 is a circuit diagram showing a data input buffer control circuit in a DDR SDRAM according to the prior art, which is also a circuit diagram showing a data input buffer in an SDR SDRAM. In the conventional DDR SDRAM, the data input buffer includes a control signal generator 100 including first and second NAND gates 10 and 16 and first to third inverters 12, 14, and 18; And an input buffer 110.

The first NAND gate 10 shown in FIG. 1 is turned low when the power is in the low active display signal PRAL enabled at the high level when the low is activated, and is maintained at the high level when the power is not in the power down mode. Inverted AND of the power down display signal PDWN. The first inverter 12 inverts the inverse AND signal from the first NAND gate 10, and the second inverter 14 outputs the read data to the outside when the DDR SRAM reads the stored data. Invert the output buffer enable signal PTRST to enable the data output buffer. The second NAND gate 16 inverts AND the signals generated by the first and second inverters 12 and 14, respectively, and the third inverter 18 inverts AND the signal generated by the second NAND gate 16. Inverted and outputted as a control signal PDINC for controlling the turning on / off of the input buffer 110. At this time, the input buffer is turned on when the control signal PDINC is at a high level, and the input buffer is turned off when the control signal PDINC is at a low level.

When the input buffer 110 is turned on in response to the high level control signal PDINC generated by the control signal generator 100, the input buffer 110 receives and buffers the write data DATA1 and stores the buffered signal in the memory array cell of the SDRAM. Outputs the data to be written to the output terminal OUT.

As a result, the data input buffer shown in FIG. 1 is enabled when the data output buffer is enabled and the read data is output (that is, when the output buffer enable signal is enabled at a high level), and when the row is inactive ( That is, the control signal PDINC becomes low level only when the low active display signal is disabled) or in the power down mode (that is, when the power down display signal is low level), thereby turning off the input buffer 110. Let's do it. Therefore, when the data output buffer is turned off and not in the power down mode, the control signal PDINC is at a high level, and the data input buffer is always turned on even when the data is not in the data write state.

Meanwhile, a differential amplifier is generally used as the input buffer 110 shown in FIG. 1. When the differential amplifier is turned on, a DC current flows from the power supply voltage (Vcc) to the ground power supply (Vss). In general, the DC current increases to increase the speed of the differential amplifier. Therefore, the longer the time the differential amplifier is turned on, the more the current consumption increases. In order to reduce the current consumption by the differential amplifier, it is preferable to turn on the data input buffer only when the SDRAM writes data, and to turn off the data input buffer in other operation states.

However, conventionally, since the data input buffer maintains the turn-on state even in many sections other than the actual data write operation state, a problem arises in that the current consumption due to the data input buffer becomes large.

An object of the present invention is to control the data input buffer in the SDRAM to minimize the current consumption caused by the data input buffer by maintaining the data input buffer turned on only when the SDRAM operable in DDR mode write operation To provide a circuit.

1 is a circuit diagram showing a data input buffer control circuit in a conventional DDR SDRAM.

2 is a circuit diagram showing an embodiment of a data input buffer control circuit of a DDR SDRAM according to the present invention.

3 (a) to 3 (f) are waveform diagrams for comparing the generation of the control signal PDINC in the present invention and the conventional data input buffer control circuit according to the operation state of the DDR SDRAM.

4 is a circuit diagram of another embodiment of a data input buffer control circuit in an SDRAM according to the present invention.

In order to achieve the above object, a data input buffer control circuit according to the present invention which receives data to be written to a memory cell in an SDRAM selectively operable with DDR or SDR has a row active display signal, SDRAM enabled when the row is activated. Power-down display signal disabled in the power-down mode, output buffer enable signal for enabling the output buffer for outputting read data to the outside while the SDRAM is in read operation, and enabled when the SDRAM is in write operation. A control signal generating means for generating a control signal and a input buffer for receiving data to be written in response to the control signal by logical combination of a write operation display signal to be enabled and a mode display signal indicating whether the SDRAM is in the DDR mode or the SDR mode. Characterized in having a.

Unlike conventional SDR SDRAM, DDR SDRAM uses a differential clock signal and is a memory in which two data are input and output in one clock cycle. Thus, twice the data rate is realized compared to the existing SDR SDRAM. To this end, several pins are added and changed for the SDR SDRAM, and the write and read methods are changed.

First, a DQS pin is added to accept the clock signal. In the case of SDR SDRAM, data is written and read out in synchronization with the system clock signal for operating the system. However, when the DDR SDRAM receives data to be written from the outside, the DDR clock receives the write clock signal for writing the data to the DQS pin. . That is, the DDR SDRAM is normally accepted when the data applied to the DQ pin satisfies the setup / hold time (tDS / tDH) based on the transition of the write clock signal applied to the DQS pin.

In addition, in the SDR SDRAM, data to be written with a write command is applied. Thus, the data input buffer that accepts data must already be turned on before a write command is issued. As a result, in SDR SDRAM, the data input buffer is always turned on except when outputting data through the DQ pin, when it is not row active and when it is in power down mode. Do it.

DDR SDRAM, on the other hand, has a delay time of one clock for the write command and the data to be written. That is, since the write data is applied after the write command is applied and one clock has passed, the DDR SDRAM does not need to turn on the data input buffer before the write command is applied like the SDR SDRAM. Therefore, the present invention allows the DDR SDRAM to turn on only during the write operation of the turn-on period of the data input buffer by using the characteristic that there is a one clock delay time between the write command and the data to be written.

2 is a circuit diagram illustrating an embodiment of a data input buffer of a DDR SDRAM according to the present invention. The DDR SDRAM according to the present invention includes an input buffer including first and second inverters 20 and 22, third and fourth inverters 24 and 26, and first to fifth MOS transistors M1 to M5. 28) including. Here, the first to fifth MOS transistors M1 to M5 constitute a differential amplifier.

The first and second inverters 20 and 22 shown in FIG. 2 buffer the write operation indication signal PWR, which is enabled at a high level when the DDR SDRAM is in a write operation, to turn on / turn off the input buffer 28. Is generated as a control signal PDINC for controlling. The third inverter 24 of the input buffer 28 inverts the control signal PDINC to generate an inverted control signal. When the control signal PDINC is enabled at the high level (that is, during a write operation), the control signal inverted to the low level by the third inverter 24 is input to the gate of the first MOS transistor M1, and the first One MOS transistor M1 is turned on.

When the first MOS transistor M1 is turned on, a current path is formed in the second to fifth MOS transistors M2 to M5, and the input buffer 28 is turned on. When the input buffer 28 is turned on, the levels of the reference voltage VREF and the write data DATA1 input to the gates of the fourth MOS transistor M4 and the fifth MOS transistor M5 are compared with each other. It is generated as the drain of the third MOS transistor M3, and the level generated at this time is the level at which the write data DATA1 is inverted. The signal generated at the drain of the third MOS transistor M3 is inverted by the fourth inverter 26 and eventually inverted back to the level of the write data DATA1, and then output through the output terminal OUT to thereby output the memory cell array of the SDRAM. Is delivered to. However, the level on the bus such as LVTTL or SSTL is changed to the CMOS level while passing through the input buffer 28.

On the other hand, when the DDR SDRAM is not in the write operation, the first and second inverters 20 and 22 buffer the write operation display signal PWR, which is disabled to the low level, to control the input buffer 28 to be turned off. Generates a control signal PDINC. When the control signal PDINC is disabled at a low level (ie, not in a write operation), a control signal inverted to a high level by the third inverter 24 is input to the gate of the first MOS transistor M1. The first MOS transistor M1 is turned off.

When the first MOS transistor M1 is turned off, a current path is not formed by the second to fifth MOS transistors M2 to M5, so that the input buffer 29 is turned off to receive external data. As a result, since the data input buffer in the DDR SDRAM shown in FIG. 2 uses the write operation display signal PWR which is enabled only when the DDR SDRAM performs the write operation, the input buffer 28 causes the DDR SDRAM to perform the write operation. It is turned on only when it is in operation, and turned off when other operations are performed.

3A to 3F are waveform diagrams for comparing control signal PDINC generation in the data input buffer control circuit according to the present invention according to an operation state of a DDR SDRAM, and FIG. 3 (b) shows input / output data, and FIG. 3 (c) shows an output buffer enable signal for enabling the data output buffer to a high level in order for the DDR SDRAM to read the data. (PTRST), FIG. 3 (d) shows the write operation display signal PWR, and FIG. 3 (e) is a waveform diagram showing generation of the control signal PDINC in the conventional data input buffer. f) is a waveform diagram showing generation of the control signal PDINC in the data input buffer control circuit according to the present invention.

In FIG. 3, the first command CMD1 is a command to activate a row, the second command CMD2 is a write command, the third command CMD3 is a read command, and the fourth command CMD4 is a low precharge command. to be. Here, the row is deactivated when the low precharge command CMD4 is generated.

3 (a) and 3 (b), it can be seen that in the case of DDR SDRAM, the write command CMD2 is generated and the write data is input one clock later. Referring to FIG. 3C, the read command CMD3 is applied to the DDR SDRAM, and the read data is a signal for enabling the data output buffer to output the read data DATA1 to the outside through the data output buffer. It is enabled only in the section where is generated. Referring to FIG. 3D, while the write command CMD2 is applied to the DDR SDRAM, the write data DATA1 is applied, and the write display signal PWR is at a high level while the write data DATA1 is written to the memory cell. Is enabled.

3 (e) is a waveform diagram showing a control signal PDINC generated in a conventional data input buffer control circuit, and the control signal PDINC is enabled at a high level while the row is activated by the row activation command CMD1. And then remain enabled at a high level. Then, when the output buffer enable signal PTRST is enabled at the high level by the read command CMD3, the control signal PDINC goes low during this period, and then goes back to the high level, and the low precharge command CMD4. It can be seen that the control signal PDINC is disabled to the low level when the low value is inactivated by.

On the other hand, Fig. 3 (f) is a waveform diagram showing the control signal PDINC generated in the data input buffer control circuit according to the present invention, and the write operation display signal PWR is brought to the high level by the write command CMD2. It can be seen that the control signal PDINC is enabled to a high level only while being enabled.

As a result, the period in which the data input buffer control circuit according to the present invention is enabled at a high level in order to receive the write data DATA1 is greatly reduced as compared with the prior art, thereby greatly reducing the current consumption by the data input buffer. In addition, since the data input buffer according to the present invention uses the write operation display signal PWR as the control signal PDINC, a logic circuit for generating the control signal PDINC is not required as in the conventional DDR SDRAM. Can be simplified.

4 is a circuit diagram of another embodiment of a data input buffer control circuit in an SDRAM according to the present invention. The data input buffer according to the present invention includes a control signal generator 50 including a NAND gate 30, inverters 32, 34, 36, and 46, AND gates 40 and 42, and a NOA gate 44. And an input buffer 50.

The data input buffer control circuit shown in FIG. 4 is for an SDRAM capable of selectively operating in a DDR mode or an SDR mode. The control signal generator 50 shown in FIG. 4 has a row active display signal PRAL enabled when the row is activated, a power down display signal PDWN disabled when the SDRAM is in a power down mode, and the SDRAM is docked. Output buffer enable signal (PTRST) for enabling the data output buffer during run-out, write operation indication signal (PWR) enabled if the SDRAM is in write operation, and whether the SDRAM is in DDR mode or SDR mode. The mode display signal PDDR is logically combined to generate the control signal PDINC. Here, the mode display signal PDDR is a signal that is enabled at a high level when the SDRAM is in the DDR mode. The input buffer 52 buffers the write data DATA1 in response to the control signal PDINC.

In more detail, the NAND gate 30 of the control signal generator 50 inverts the low active display signal PRAL and the power down display signal PDWN, and the inverted AND product of the NAND gate 30 is performed. Inverted by the inverter 32. The inverter 34 inverts the output buffer enable signal PTRST, and the inverter 36 inverts the mode display signal PDDR. The AND gate 40 logically multiplies the signals generated by the inverter 32, the inverter 34, and the inverter 36, respectively. The AND gate 42 then multiplies the mode display signal PDDR by the write operation display signal PWR.

The NOR gate 44 inverts and ORs the signals multiplied by the AND gate 40 and the AND gate 42, respectively, and the inverter 46 inverts the ORs that are inverted AND in the NOA gate 44 to input buffers. Generated as a control signal PDINC for controlling the turn-on / turn-off of 52.

Since the input buffer 52 shown in FIG. 4 has the same circuit configuration as the input buffer 28 shown in FIG. 2 and performs the same operation, the description thereof is omitted here.

As a result, in the data input buffer control circuit shown in FIG. 4, when the mode display signal PDDR is enabled at a high level, the SDRAM operates in the DDR mode to generate the control signal PDINC according to the write operation display signal PWR. When the mode display signal PDDR is disabled at a low level, the SDRAM operates in the SDR mode so that the low active display signal PRAL and the power down display signal PWDN are independent of the write operation display signal PWR. And a control signal PDINC according to the output buffer enable signal PTRST.

Referring to FIG. 3, the waveform diagram of FIG. 3E illustrates a control signal PDINC generated when the SDRAM operates in the SDR mode and the mode display signal PDDR is disabled at a low level. 3 (f) shows control signals PDINC generated when the SDRAM is operated in the DDR mode and the mode display signal PDDR is enabled at a high level.

Consequently, when the SDRAM capable of selective operation in the DDR mode or the SDR mode operates in the DDR mode, the data is inputted by the write operation display signal PWR in which the SDRAM is enabled only during the write operation by the write command CMD2. The buffer is turned on, minimizing the current drawn by the data input buffer in DDR mode.

As described above, the data input buffer control circuit in the SDRAM according to the present invention is enabled by the write operation indication signal PWR which is enabled only when the SDRAM is in the write operation when the SDRAM operates in the DDR mode. The current consumption is minimized because the data input buffer is turned on only when the RAM is writing. In addition, in the case of the SDRAM operating only in the DDR mode, since the write operation display signal PWR is used as the control signal PDINC, a logic circuit for generating the control signal PDINC is not necessary, thereby simplifying the circuit. have.

Claims (3)

A data input buffer control circuit for receiving data to be written into a memory cell in an SDRAM capable of being selectively operated at a double data rate (DDR) or a single data rate (SDR). A row active display signal enabled when a row is activated, a power down display signal disabled when the SDRAM is in a power down mode, and an output for externally outputting data read while the SDRAM is in a read operation Logical combination of an output buffer enable signal for enabling the buffer, a write operation display signal enabled when the SDRAM is in write operation, and a mode display signal indicating whether the SDRAM is in the DDR mode or the SDR mode Control signal generating means for generating a control signal; And And an input buffer for accepting the data to be written in response to the control signal. The method of claim 1, wherein the control signal generating means First logical means for ANDing the row active display signal and the power down display signal; A first inverter for inverting the output buffer enable signal; A second inverter for inverting the mode display signal; Second logical product means for logically multiplying the signals generated by the first logical means, the first inverter and the second inverter, respectively; Third logical product means for ANDing the mode display signal and the write operation display signal; And And a logical sum means for generating the control signal by ORing the signals generated by the second logical means and the third logical means, respectively. The method of claim 1, wherein the input buffer is characterized in that the differential amplifier, The differential amplifier A third inverter for inverting the control signal to generate an inverted control signal; A first MOS transistor having a gate connected to the inverted control signal and a source connected to a power supply voltage; A second MOS transistor having a gate connected to a reference voltage and a source connected to a ground power source; A third MOS transistor having a source connected to the drain of the first MOS transistor, a drain and a gate connected to the drain of the second MOS transistor; A fourth MOS transistor having a source connected to the drain of the first MOS transistor and a gate connected to the gate of the third MOS transistor; A fifth MOS transistor having a drain connected to the drain of the fourth MOS transistor, a gate connected to the write data, and a drain connected to the ground power source; And And a fourth inverter for inverting a signal generated at the drain of the fourth MOS transistor and outputting the inverted signal as data to be written to the memory array.